Programmable CMOS CNN chip for binary image processing

2004 1st International Conference on Etectrical and Electronics Engineering Programmable CMOS CNN Chip for Binary Image Processing Jesus Ezequiel Molinar-Solis, Felipe G6mez-Castaiieda,Jos6 A. Moreno-Cadenas VLSI Systems Laboratory, Electrical Engineering Department CINWSTAV-IPN, Mexico City - MEXICO e-mail: [email protected] Adstruct-At present, Cellular Neural Networks (C") in VLSI b. If the binary task is linearly separable, the original transfer technology are powerful parallel structures with real-time image h c t i o n can be replaced by a step in the positive semi-plane. processing capabilities. In this context it is necessary to work on c, Since there is no linear region on the new output function, only a simplified CNN idea from the hardware point of view (derived two saturation values, the analog multipliers can be substituted from the original CNN model proposed by Chua et uL) in order by analog multiplexers. to design a more feasible CNN IC with lower complexity d. The training set of states can be modified in order to obtain circuits. unipolar template values. This implies the use of simple current In this work, taking into account that many binary image tasks mirrors to represent such analog values. present a linearly separable feature, the original output function e. The templates are dependent on the transition point of the can be replaced by a step function. Analog multipliers can be transfer function in the CNN cell. substituted by simple analog multiplexers and we take advantage that all the signals can be unipolar. These features reduce the complexity of the circuits but presewing the computation in selected binary-image processing tasks. The circuits in our CMOS integrated circuit belong to the class of those in the design of mixed-signal systems with current-mode representation of signal-flow. The technology for these circuits is based an the n-well, 1.2-micron CMOS process offered by "Jl %J* k MOSlS to research groups in universities. Fig. 1. Chua's Model CNN cell. 1. INTRODUCTION From point d. above, we establish the conditions to be fulfilled in Many CNN analog chips have been developed over the past 15 the numerical determination of the templates. Meanwhile, points b. years. The success o f such CNN structure is due to the local and c. are taken as the argument to defme a binary CNN architecture connectivity between cells, which allow less routing complexity as for unsigned variables. The templates were commonly implemented compared with other artificial neural networks. In our approach, we in early designs in association with four-quadrant multipliers, using identify the complex building blocks responsible for arithmetic large silicon area. Instead, in our approach, a multiplexer chooses a processing, i.e. analog multipliers in the original CNN model [l], to value, which defines the cell state and consequently the cell output. be replaced by multiplexing functions with unipolar signals, where This idea is presented in Fig. 2, where the magnitude of proper only one template namely, feedback A or feedforward B, is read as unidirectional current sources represents template values. The a programmable entity. discrete current fed through a multiplexer makes distinguishable the The templates to be used as an analog program are obtained f om an proposed CNN cell. A full demonstration of the binary CNN model off-line design technique which uses the "Simplex Method" as a is presented in [3]. derivative free optimization procedure [2]. The parallel circuit in our Another important point that allows reducing an important silicon design is a dynamical system useful in real-time applications of area is that most binary tasks use one template and rarely both [4]. image processing that is based on the following tasks: I ) edge This observation suggests implementing one template that can be detection, and 2) shadow extraction. selected as A or B . The fmal block diagram of the proposed CNN The underlying analysis and design methodology is tested on a 4 by cell with the above considerations is shown in Fig. 3. 4 CNN array by extensive electrical and system simulations. We .I,V*l,l show the electrical measurements of the CNN chip in the execution of both tasks for a given input pattern. ,I ., (L d* 2. CNN MODEL FOR VLSI Figure 1, shows the CNN cell with continuous time variables as defined by Chua [2]. The issues below are worth of considering for implementing a low-complexity binary CNN with analog processing. Fig. 2. Multipliers can be reduced to multiplexers a. A set of states describes the initial condition and final m i t i o m for a given task. 02004 IEEE 0-7803-853?4/04/$20.00 21 0  ~gIJW L - _ J Fig. 3. The proposed cell block diagram. a) inputpattern b) CNN Output 3. ELECTRICAL CNN CELL The complete binary CNN cell based on current mode CMOS circuits is in Fig. 4. The adder block is realized by means of Kirchhoff current law. The step function in the positive semi-plane i s implemented by a current mode comparator with a constant current source to shift the input variable [5]. The circuit that enters a constant current to the template multiplexers is the simple current mirror. Although its precision is not high it is enough when the errors of copying are minimized by following matching rules of devices namely, size and geometry [6]. The switches SI and Sz defme independently the central and no central elements as an A or B template, these are achieved by a digital multiplexer. Auxiliary digitaI circuits that couple signals of the CNN cell to external electronics such as output buffers are also included in silicon dealing with propagation delay for maximum clock frequency. c> Fig. 5, Edge extraction, a) input pa", 6) correct rs"output, E) PSPice imnsient analysis simulation results. -a-- a) Input pattern b) CNN output I.LU I . Fig. 4. Electrical CNN cell. 4. PSPICE SIMULATION As a vehicle of performance, a 4 by 4 array is simulated using different input pattems. T h i s demonstrates the capacity of the circuit to support the tasks mentioned above, with a minimal processing time of 10 nsec. The VDD voltage is +5V. A +5V cell output represents a black pixeI and a OV represents a white pixel. The signal V3 controls the initial condition and V4 tums on the cell may. Fig. 5, a) shows one of the input pattems tested for the edge extraction task, Fig. 5, b) presents the correct processed CNN output, and Fig. 5, c) shows the simulation transient response for this input. This is, the four central cells go to a 0 V output. C) For the shadow extraction task, Fig 6, a) shows the input pattern, Fig. 6 . Shadow cxtractioq a) input pattern, b) correct CNN output. c) PSpice Fig. 6. b) shows the correct CNN output and Fig. 6 c) presents the transient analysis simulation results. PSpice simulation resuIt with the cell transition by column. 21 1  5. CMOS CNN lNTECRATED CIRCUIT The microphotography of the CNN integrated circuit with optimized cells is included in Fig. 7. It is a detailed technological representation using a 2.25 by 2.25 square-millimeter area. As a packaged system this one has 40 pins. The CNN IC design was fabricated through the MOSS [7] organization. Fig. 9. V3 and V4 signal measurement. A) EDGE EXTRACTION The task was electrically tested with m y different input pattems, the mast representative one is in Fig. 5 . Can be seen, the four central cells must achieve a transition from black to white output. After V4 goes high, this cell changes its output, correctly. The oscilloscope measurement is shown in Fig. 10. i , m i zzaw c Z ~ E G 1.W Stop C E 5.00~ Fig. 7. Integrated circuit microphotography. "" 6. ELECTRICAL PERFORMANCE The CNN IC was tested on a PCB with auxiliaq circuitry such as Fig. 10. Four central cells transition. op-amp current sources and a microcontroller, Fig. 8. Each task was tested with many different input patterns. Fig. 9 shows the oscilloscope measurement of V3 and V4 signals. T h e cells on the edge of the army keep a black output, Fig. 11, shows this fact after pulse V4 takes place. Fig. 11. Edge cell correct output. The minimal time response for this task is approximately lOns as is observed by the measurement in Fig. 12. This can be compared with other similar CNN implementations [8],[9],[10]. Fig. 8. PCB with auxikiary circuitry for test measurements. 212  7. CONCLUSION We have presented a CNN prototype in CMOS technology, where the central aspect was the optimization of silicon area for specific binary processing. This goal is reached considering that the original transfer function in the CNN model can be substituted for a step with unipolar representation of variables. The analysis of performance was done using electrical simulations with PSpice. We show the electrical response of a CNN prototype chip which has a good settling time in comparison with other works. A new study that includes low power and low voltage standard with submicron Fig. 12. Cell response after V4 pulse. technology is planned for next research on CNN by our group. 8. REFERENCES B) SHADOW EXTRACTION 1. Leon 0.Chua, CNN: A Purudjgm for Complexity.World Similarly, the shadow extraction task was tested with different input Scientific Series on Nonlinear Science, Series A, Vol. 31, patterns. Fig. 6 a), b), shows one of them. T h i s task is an example of World Scientific Publishing (1998) a propagating template, since the information flows in this case from 2. K. Nakai and A. Wshida, “Design Technique of Cellular Neural left to right side through eacb column. After pulse V4 goes high, the Network”, Electronics and Communications in Japan, Part 3, cells belonging to column 2 turns black, afterwards, column 3, and Vol. 78, NO.3 (1995),pp. 97-106 so on. Figures 13, 14, 15, show the time response between cells, 3. J.E. Molinar Solis. Analog CMOS Integrated Circuit with with a total settling time of 3 h , approximately. CelluEar Neural Network Architecture, Master of Science Thesis. Electrical Engineering Dept., CMVESTAV-IPN, Mexico City, Mexico (2002). 4. Roska, T. Kek, L. and Zarandy, A. “CNN software library (templates and algorithms)” version 7.0 (DSN-1-1997). Analogical and Neural Computing Laboratory, Computer Automation Institute, Hungarian Academy of Sciences, Budapest Hungary. 5. H. Traff, “Novel Approach to High Speed CMOS Current Comparator”, Electronics letters, 30 January 1992, vol. 28, no. 3 . p ~310-312. . 6. Marcel J. M. Pelgrom, J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors”, IEEE Journal of Fig. 13. Column 2 cell response after V4 pulse. Solid State Circuits, vol. 24, no. 5, Octuber 1989. 7. MOSIS, Implementation Service, http:// www. mosis. com. 8. An Passio and Kari HaIonen, “A New Cell Output ... ............ Nonlinearity for Dense Cellular Nonlinear Network COIUrrn 2 ....... Integration”, IEEE Trans. on Circuits and Systems, Vol. 48, cell outpld cohmn 3 ....... ... ....... ...... ........... 9. NO.3 (2001), pp. 272-280. M. Anguita, F.J. Pelayo, E. Ros, D. Palomar and A. Prieto, ceu ourput “Focal-Plane and Multiple Chip VLSI Approaches to CNNs”, Analog Integrated Circuits and Signal Processing, 15,263-275, .... 1998. 10. L. Ravezzi, G. F. Dafla Betta and G. Setti, “A New Current Fig. 14 Time response between column 2 and column 3 cells. Mode Programmable Cellular Neural Network” Proc. CNNA 1 =“/ 2 203/ a@!2o.w slw 5 E LOW 1998, London England. I F e n output ... .. ... .. Flg 15 Time response between column 3 and column 4 cells 21 3