Very Large Scale Integration

Architects are faced with the problem of building enterprise scale information systems, with streamlined, automated internal business processes and web-enabled business functions, all across multiple legacy applications. The underlying architectures for such systems are embodied in a range of diverse products known as Enterprise Application Integration (EAI) technologies. In this tutorial, we highlight some of the major problems, approaches and issues in designing EAI architectures and selecting appropriate supporting technology. An architect's perspective on designing large-scale integrated applications is taken, and we discuss requirements elicitation, architecture patterns, EAI technology and features, and risk mitigation. J2EE and .NET technologies are used to illustrate the capabilities of state-or-the-art integration technologies.

Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC techniques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence Ò 90 nm technology. This occupies 1290 lm 2 . Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.

A method that evaluates the delay test effectiveness in four logic groups of several level sensitive scan design (LSSD) chips is presented. Delay test effectiveness measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level. Delay testing of VLSI logic chips has become critical to the quality of VLSI products. Data from failure analysis showed that small-size defects are more likely to occur than large size defects. These small-size defects are mainly responsible for delay defects that cause potentail system failure (1,2). At chip level, various delay test generation methods were developed (3,4) to consider delay faults either in the gate level or path level. Questions were raised (5,6) concerning the accuracy of the delay test effectiveness evaluation methods used in the conventional approach (7,8). It was shown that defect level, system sensitivity and tester accuracy are major factors in determining the quaIity of delay tests. In other words, a 100 percent delay test coverage obtained from conventional test generators and simulators does not guamntee a sufficient delay test quality. Recently, Motika et.. al. ( ) presented a logic-chip delay test method used on IBM system/3090 timing. Their technique divides an LSSD (10) structure into five logic groups and provides delay test sequences by applying stuck-fault test patterns or weighted random patterns. It was reported that, approximately, 80 percent to 90 percent of delay test coverage was obtained using their technique. However, these delay test coverage numbers do not represent the acma.1delay test effectiveness. It is only an indication that much better delay tests were accomplished compared to the stuck-at-fault tests. In this paper, based on the statistics of four test chips, the delay Lest effectiveness of gross strobing hXs and per-pin Permission to copy without fee all or part of this material is granted prowded that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the pubhcation and its date appear, and notice IS given that copying IS by perrmsslon of the Association for Computing Machinery. To copy otherwise, or to republish, requmes a fee and/or specific permission.

A method that evaluates the delay test effectiveness in four logic groups of several level sensitive scan design (LSSD) chips is presented. Delay test effectiveness measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level. Delay testing of VLSI logic chips has become critical to the quality of VLSI products. Data from failure analysis showed that small-size defects are more likely to occur than large size defects. These small-size defects are mainly responsible for delay defects that cause potentail system failure (1,2). At chip level, various delay test generation methods were developed (3,4) to consider delay faults either in the gate level or path level. Questions were raised (5,6) concerning the accuracy of the delay test effectiveness evaluation methods used in the conventional approach (7,8). It was shown that defect level, system sensitivity and tester accuracy are major factors in determining the quaIity of delay tests. In other words, a 100 percent delay test coverage obtained from conventional test generators and simulators does not guamntee a sufficient delay test quality. Recently, Motika et.. al. ( ) presented a logic-chip delay test method used on IBM system/3090 timing. Their technique divides an LSSD (10) structure into five logic groups and provides delay test sequences by applying stuck-fault test patterns or weighted random patterns. It was reported that, approximately, 80 percent to 90 percent of delay test coverage was obtained using their technique. However, these delay test coverage numbers do not represent the acma.1delay test effectiveness. It is only an indication that much better delay tests were accomplished compared to the stuck-at-fault tests. In this paper, based on the statistics of four test chips, the delay Lest effectiveness of gross strobing hXs and per-pin Permission to copy without fee all or part of this material is granted prowded that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the pubhcation and its date appear, and notice IS given that copying IS by perrmsslon of the Association for Computing Machinery. To copy otherwise, or to republish, requmes a fee and/or specific permission.

Single-electron devices (SEDs) are attracting a lot of attention as devices for future large-scale integration because of their inherent low power and small size. We have developed a novel method of fabricating small Si single-electron transistors (SETs) called pattern-dependent oxidation (PADOX) and used it to make many kinds of SEDs. The low power consumption of SEDs is useful for logic circuits. In addition, SETs have two unique features that conventional transistors do not have: multi-input gate capability and conductance that oscillates as a function of gate voltage. We exploit these features to achieve complicated functions for logic circuits, such as multiple-valued logic.

A graph grammar is a generative description of a graph language (a possibly infinite set of graphs). In this paper, we present a novel algorithm for inducing a graph grammar from a given set of 'positive' and 'negative' graphs. The algorithm is guaranteed to produce a grammar that can generate all of the positive and none of the negative input graphs. Driven by a heuristic specific-to-general search process, the algorithm tries to find a small grammar that generalizes beyond the positive input set. During the search, the algorithm employs a graph grammar parser to eliminate the candidate grammars that can generate at least one negative input graph. We validate our method by inducing grammars for chemical structural formulas and flowcharts and thereby show its potential applicability to chemical engineering and visual programming.

Post-training safety alignment in large language models (LLMs) often relies on localized neural gates rather than erasing underlying hazardous capabilities. This review analyzes the transition from white-box safety localization to black-box behavioral emulations that bypass these gates via query-only API access. It synthesizes existing work, including NeuroStrike and GateBreaker, to evaluate the Black-Box Neuron Profiler (BBNP) and the Transferable Single-Neuron Emulator (TSNE), frameworks developed by Dr. Syed Muntasir Mamun (2026). The analysis confirms that safety alignment in dense models can be mediated by a single, causally sufficient refusal neuron. BBNP and TSNE successfully reverse-engineer and emulate the functional effect of single-neuron ablation from external behavior, closing the performance gap with white-box attacks to within 10 percentage points (TSNE Average Attack Success Rate: 82.7%). This demonstrates that behavioral safety testing is insufficient, requiring a regulatory shift toward mechanistic certification and structural defenses, such as SafeNeuron and NeST, to build intrinsically resilient models.

A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130nm lowpower CMOS process, with an operation frequency of 100MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required.

Generalized network flow problems generalize ordinary network flow problems by specifying a flow multiplier for each arc . For every unit of flow entering the arc, units of flow exit. We present parallel algorithms for the all-sources generalized shortest paths problem using Floyd-Warshall and matrix multiplication algorithms and monotonic piecewise-linear functions. The latter algorithm requires polylogarithmic time on a concurrent-read exclusive-write PRAM with a superpolynomial number of algorithms.

As the circuit complexity is increasing in demand for the more computations on a single VLSI chip, low power VLSI design has become important specially for portable devices powered by battery. Digital camera is one of them where realtime image capturing, compression and storage of compressed image data is done. Most of the digital camera implement JPEG baseline algorithm to store highly compressed image in camera memory. In this paper we report and present low cost, low power and computationally efficient circuit design of JPEG for digital camera to get highly compressed image by exploiting removal of subjective redundancy from the image.

Fast Fourier transform (FFT) has become ubiquitous in many engineering applications. Efficient algorithms are being designed to improve the architecture of FFT. Among the different proposed algorithms, split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithms.

Discrete cosine transform (DCT) is widely used in image and video compression standards. This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low hardware circuit cost as well as low power consumption. Low hardware cost is achieved by exploiting redundant computational units in recent literature. A technique to reduce error introduced by sign extension is also presented. The proposed 1-D DCT architecture is implemented in both the Xilinx FPGA and Synopsys DC using TSMC CLN65GPLUS 65nm technology library. For power and hardware cost comparisons, recent DA based DCT architecture is also implemented. The comparison results indicate the considerable power as well as hardware savings in presented architecture. 2-D DCT is implemented using row column decomposition by the proposed 1-D DCT architecture.

In this paper, a new VLSI architecture is provided for the application of quad-input and dual-output Fuzzy Logic Controller (FLC) with maximum seven fuzzy membership functions. Our approach is based on classical three stage implementation process -fuzzification, rule inference and defuzzification cores. An innovative design methodology is proposed by splitting the process between DSP processor and FPGA to implement run time configurable FLC. Since the target application takes a maximum of 4 inputs and 7 membership functions, the rule base comprises of 2401 (7 4 ) rules. It increases the complexity of the overall system. To minimize this effect, rule reduction VLSI architecture is suggested to bind the no of rules to 16 (2 4 ). The Rule inference is designed for seeking the maximum frequency of operation for targeted Virtex 5 LX110T FPGA. The simulation results obtained with Modelsim 6.3g show satisfactory results for all test vectors.

This paper presents delay improved VLSI architecture of S-box for Advance Encryption Standard (AES) algorithm. The proposed architecture is implemented in FPGA. The delay, area and power comparison with some existing S-box architecture have been done. The comparison results show delay improvement along with low power consumption with constant area in terms of FPGA slices. The silicon validity is done by programming the XC2VP30 device of Xilinx FPGA with VHDL code for the proposed architecture. The architecture is also implemented in ASIC using 0.18 µm standard cell technology library which shows delay improvement of about 16 percent.

In this paper, first a comparative simulation study of PSNR is done for two quantization tables, one recommended by JPEG committee and another suitable for hardware simplification. Simulation results indicate that quantization table suitable for hardware simplification can be used for designing JPEG baseline coder circuitry. Then we present a simple finite state machine (FSM) based VLSI architecture and its FPGA implementation from discrete cosine transform (DCT) to zig-zag ordering of transformed coefficients for JPEG baseline coder. 1-D DCT implementation is done for the compressed distributed arithmetic (DA) algorithm reported in previous literature with shifting performed by division operator. Quantizer using only shifter (no adder) and 2-D DCT are combined in single step. Implementation is done on XC2VP30 device on Xilinx Virtex-II Pro FPGA board.

Scaling of CMOS technology improved the speed nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious turn as the scaling extends into ultra-deep-submicron (UDSM) region. These unsolicited leakage currents should be minimized for the smooth functioning of the circuit. Designing of such leakage free nanoscale CMOS circuits turns to be a challenging task. In this work, we address the issue of leakage power that arises with the device channel length scaling to sub-100nm. We present a circuit technique to mitigate the leakage currents of MOSFET through controlling the voltage at the source terminal of the MOSFET. CMOS inverter designed using the proposed technique results in 98% and 30% improvement in static and total power dissipation respectively compared with its conventional design. The simulation results of NAND and NOR gates designed using the same technique indicates 15.89% and 18.83% improvement in the total power compared with their corresponding conventional designs. 11-stage CMOS ring oscillator designed using the proposed technique is analyzed, and corresponding simulation results are reported. Comparison of the proposed circuits in terms of power dissipation and delay with two existing techniques is presented. The circuits designed using the proposed technique results in good Power-Delay Product (PDP).

An applications of signal processing are frequently used everywhere in day-to-day life. “Digital Signal Processing (DSP)” has been basic requirement of efficient and accurate arithmetic operations for performing fast and accurate signal processing. Logarithm arithmetic provides an option of that desire. In this work, it is presented an efficient VLSI implementation of an antilogarithm converter by using 10-region error correction. It provides error efficient implementation with significant hardware gain. VLSI implementation of reported and proposed antilogarithmic converters design created in Xilinx ISE 12.1. Antilogarithmic converters (reported and proposed design) are synthesized by using Synopsys design software perform the RTL Synthesis analysis by using package design compiler. This paper presents 10- region converter which considers design trade-off where proposed demonstrates 19.75%, 31.02%, 12.65%, 44.65% and 29.91% respective reduction in comparison of previous design. Erro...

Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell’s algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell’s algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % l...

Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.

A novel Smart Pixel Opto-VLSI architecture to implement a complete 2-D wavelet transform of real-time captured images is presented. The Smart Pixel architecture enables the realisation of a highly parallel, compact, low power device capable of real-time capture, compression, decompression and display of images suitable for Mobile Multimedia Communication applications.

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit enviromental requirements. The authors present a reformulation based VLSI architecture for threhold selection for Adaptive Viterbi Decoding in wireless applications. Through reformulation of the Adaptive Viterbi Algorithm, the compare operation for threshold selection in Add Compare Select (ACS) unit is simplified from variable based to constant based and the width of path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and Look Up Table (LUT) technologies. The paper describes the reformulation technique, its VLSI Architecture for Adaptive Viterbi Decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in additon to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the Path Metric Memory Unit (PMU).

Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with Multiple Input and Multiple Output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented channel matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.

Multiple Input -Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumption. This paper proposes an area and power efficient VLSI architecture that can serve the dual purpose of minimum norm sorting of rows as well as upper/lower block tri-angularization of matrices. The resources inside the architecture are shared among both operations and only primitive computations are used. Results indicate saving in silicon real estate as well as power consumption compared to previous architecture without degrading performance.

Multiple Input Multiple Output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented channel matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.

Multiple Input -Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumption. This paper proposes an area and power efficient VLSI architecture that can serve the dual purpose of minimum norm sorting of rows as well as upper/lower block tri-angularization of matrices. The resources inside the architecture are shared among both operations and only primitive computations are used. Results indicate saving in silicon real estate as well as power consumption compared to previous architecture without degrading performance.

The primary driver of female death remains breast cancer, highlighting the need for effective screening and accessible diagnostic tools. Digital hardware approaches have demonstrated strong performance but are constrained by high computational and energy demands, limiting their use in real-time portable devices. Analog Artificial Neural Networks (AANNs) offer advantages in speed, power efficiency, and compact hardware, though they remain experimental. This survey reviews AANNs for breast cancer diagnosis, applying a structured methodology to identify and compare studies across architectures, hardware technologies, accuracy, power consumption, and clinical applicability. A framework is proposed to organize the field and examine the dataset. The survey highlights sensitivity to environmental factors as a design challenge, while moderating clinical claims by discussing pathways and deployment barriers. By synthesizing current research, this survey motivates the development of clinically validated solutions that, if attained, could advance medical informatics by enabling the integration of analog models into clinical practice.

In this work, we propose a novel technique for evolving transistor netlists from truth table descriptions of arbitrary digital circuits. The proposed methods incorporate the effective use of Genetic Algorithms (GAs). In typical semi-custom and custom design flows, logic optimization is done at the gate level after Boolean translation of the input truth table. The final transistor netlist is then deduced from the simplified gate logic to be laid out on a chip. However transistor level optimizations after the boolean simplification step would still not lead to the minimum number of transistors. This final optimization level is non-existent in present custom design flows. This work aims to address this need. A salient feature of the proposed technique is the bypassing of gate level representation and optimization in the VLSI design flow. We provide genetic methods to directly optimize truth table inputs using transistor level simplification. This eliminates the intermediate gate level optimization step and provides optimized transistor netlists which could be used for dynamic library cell generation for custom and semi-custom designs on the fly.

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems ...

Complex rotators are used in many important signal processing applications, including Cooley-Tukey and split-radix FFT algorithms. This paper presents methods for designing multiplierless implementations of fixed-point rotators and FFTs, in which multiplications are replaced by additions, subtractions, and shifts. These methods minimise the adder-cost (the number of additions and subtractions), while achieving a specified level of accuracy. FFT designs based on multiplierless rotators are compared with designs based on the multiplierless implementation of DFT matrix multiplication. These techniques make possible VLSI implementations of rotators and FFTs which could achieve very high speed and/or power efficiency. The methods can be used to provide any chosen accuracy; examples are presented for 12 to 26 bit accuracy. On average, rotators are shown to be implementable using 10, 12, or 15 adders to achieve accuracies of 12, 16, or 20 bits, respectively.

NRL is developing compact optic flow sensors for use in a variety of small-scale navigation and collision avoidance tasks. These sensors are being developed for use in micro air vehicles (MAVs), which are autonomous aircraft whose maximum dimension is on the order of 15 cm. To achieve desired weight specifications of 1-2 grams, mixed-signal VLSI circuitry is being used to develop compact focal plane sensors that directly compute optic flow. As an interim proof of principle, we have constructed a sensor comprising a focal plane sensor head with on-chip processing and a back-end PIC microcontroller. This interim sensors weighs approximately 25 grams and is able to measure optic flow with realworld and low-contrast textures. Variations of this sensor have been used to control the flight of a glider in real-time to avoid collisions with walls.

This paper, Volume III in a series on Knowledge Distillation (KD), explores the rigorous theoretical foundations governing Multimodal and Cross-Domain convergence within modern artificial intelligence systems. Moving beyond the initial concept of KD as a compression heuristic for "specialist models" and "dark knowledge," this analysis focuses on the complex integration of these capabilities into unified "generalist architectures" like Vision-Language Models (VLMs). The core challenge addressed is the overcoming of profound architectural barriers, including the geometric misalignment inherent in the "modality gap" and the systemic temporal degradation known as catastrophic forgetting. By investigating underlying principles of Information Theory and Optimization Landscapes, the paper provides a theoretical framework for applied solutions such as Align-KD, Switch-KD, and the Shared Experience Lifelong Learning (SHELL) paradigm.

Architectural thermal modeling of high performance VLSI systems is of special importance in order to achieve reliable and power-saving system designs. In this paper, we present a novel, computation-efficient methodology for architectural level compact thermal modeling. The RC thermal models derived from this methodology are based on the layout of micro-architectural level functional blocks such as caches, execution units, and register files, etc. We utilize the duality between thermal and electrical circuit to perform electro-thermal simulations of both steady state and transient thermal responses of different blocks that dissipate different amounts of power. Temperature profiles derived from this modeling technique are compared with those derived from computation-intensive FEM/FDM tools. The model is both extremely fast and accurate, less than 4% error. This modeling methodology can then be adopted for architectural level VLSI design tools to perform fast electro-thermal simulations.

In this paper we introduce a micro-optical architecture that uses meso-scopic diffractive optical elements ( DOEs) as three dimensional interconnects in a memory system for high level instruction level parallelism (ILP) processors. By using meso-scopic DOEs we can reduce the scale of integration to the VLSI scale, i.e., the micron scale, achieve submicron alignment tolerance, improve reliability due to monolithic integration, facilitate integration into the current manufacturing infrastructure, and offer the ability for higher bandwidth and high interconnect densities. To this the end we are developing the component technologies needed to realize this system. In this paper we present our work in the development of a theoretical and experimental framework for the design and characterization of meso-scopic DOEs, preliminary experimental results of meso-scopic beam splitters, and a large scale demonstration of the ILP memory system.

This paper presents some fundamental issues related to the design and implcmientation of CAD orient4 database sysrcms. Integrating databases i.n sophisticated CAD environments rcquircs functionalilies usually not provided by cxihting syQems. c.g relational or entity-relationship systems. For instance. consistency controls have to provide richer and more flexible features than the former "take it or leave it" paradigm. The basic aspects are 'cxamincd here with rc\pcct to the nature of CAD objects, to their con&cncy states and to their dynamicity. The nature of CAD objects concern3 the complexity of their structure and of their rclationhhipb. The state of CAD objects concerns their completenrs\ with considerations to their consistency. Finally, the dynamicity of CAD objects concern5 the evolving nature of their structure and of their properry values. i.e their behavior, with connections to versions and rcprewntations. These concepts are defined and dctailcd with examplcc drawn from VLSI circuit design. The functionalitics of a prototype CAD database system offering new solutions in these areas are presented, calling upon object-oriented concepts and logic-programming. It is currently being tested for VLSI circuit design in cooperation with the CAD Research Dept at CIVET. Mail : !ntcvar!inria!im!og!rieu or !mcvar!itlriufimo~~!rr~u~en This work is supported in part by the French Deportmc'ttt of Telecommunications (CNET contract 843BO61) and the French Department of Research (contract PRCIBDZ 850222/121 I I).

Successful design of very large scale integration (VLSI) circuits requires the use of various optimizationspower reduction, area, and time optimization. This requires the involvement of AI-based optimization techniques, such as machine learning (ML), deep learning (DL), genetic algorithms (GA), particle swarm optimization (PSO), and reinforcement learning (RL), to fulfill such tasks where traditional approaches fail to do so. The abundant libraries and ease of implementation have made Python a widely used platform in AIbased VLSI optimization. The methodology used in this study is a comparative study of different AI-based optimization algorithms used in the VLSI circuits. This research is structured in the following way: problem definition, data collection & preprocessing, implementation on Python, and performance evaluation. The best number was obtained using DL (CNN) and RL (95%) for the complex tasks (floorplanning and dynamic power management). ML (SVM) achieved high accuracy (90%) on well-defined problems but was not scalable for large designs. GA and PSO were good in performing global optimizations for problems like area minimization and routing but required fine-tuning of parameters. DL and RL had the highest computational complexity (GPU acceleration) and the lowest resource requirements, with easier implementation, with ML techniques. We found that DL and RL are better suited to large and complex designs and are slow for small and simple designs, whereas ML (SVM) and PSO are better suited to small and simple designs and are often slow given large and complex designs. Therefore, additional research is needed on the use of multiple AI techniques in a hybrid way to overcome limitations of the different techniques and enhance design efficiency. The results of this study can be applied in the following areas: AI-based Electronic Design Automation (EDA) tools, Power and performance optimization in semiconductor industries, Automated circuit design for advanced computing and development of Python-based AI stacks for VLSI research.

For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

Over the years different interpretations of Rent's rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expected to be most appropriate for current wirelength estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent characteristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. We also study the impact of the placement approach and placement quality on the geometric Rent characteristics.

This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented.

In recent fabrication technologies, buffered clock distribution networks have become increasingly popular due to increasing on-chip wiring delays. Traditionally, clock distribution networks has been optimized to minimize end-to-end skew of the distribution network. However, since most ICs have an on-chip PLL, we argue that the design goal of minimizing end-to-end jitter is more relevant. In this paper, we present a dynamic programming based approach to synthesize a minimum cost buffered H-tree clock distribution network. Our cost functions are a weighted sum of power and jitter, and a weighted sum of power and end-to-end delay of the distribution network. Our approach is based on precharacterizing the delay, jitter and power of buffered segments of different lengths, topologies, buffer sizes and wire-codes. Using this information, a dynamic programming (DP) engine automatically generates the optimal H-tree that minimizes the appropriate cost function. Compared to a manually constructed buffered H-tree network, our approaches are able to reduce both jitter (by as much as 28%, and power by as much as 46%. When optimizing for minimum jitter, the DP engine generates a H-tree with lower jitter than when optimizing for minimum delay, thereby validating our approach, and proving its usefulness.

 This is done in computers that provide a separate I/O processor (IOP) in addition to the central processing unit (CPU).  The memory communicates with both the CPU and the IOP through a memory bus.  The IOP communicates also with the input and output devices through a separate I/O bus with its own address, data and control lines.  The purpose of the IOP is to provide an independent pathway for the transfer of information between external devices and internal memory. iii. Isolated Versus Memory-Mapped I/O :  Many computers use one common bus to transfer information between memory or I/O and the CPU.  The distinction between a memory transfer and I/O transfer is made through separate read and write lines.  The CPU specifies whether the address on the address lines is for a memory word or for an interface register by enabling one of two possible read or write lines.  The I/O read and I/O write control lines are enabled during an I/O transfer.  The memory read and memory write control lines are enabled during a memory transfer.  In the isolated I/O configuration, the CPU has distinct input and output instructions, and each of these instructions is associated with the address of an interface register.  When the CPU fetches and decodes the operation code of an input or output instruction, it places the address associated with the instruction into the common address lines.  At the same time, it enables the I/O read (for input) or I/O write (for output) control line.  This informs the external components that are attached to the common bus that the address in the address lines is for an interface register and not for a memory word.  On the other hand, when the CPU is fetching an instruction or an operand from memory, it places the memory address on the address lines and enables the memory read or memory write control line.  This informs the external components that the address is for a memory word and not for an I/O interface.  The other alternative is to use the same address space for both memory and I/O.  This is the case in computers that employ only one set of read and write signals and do not distinguish between memory and I/O addresses.  This configuration is referred to as memory mapped I/O.  The computer treats an interface register as being part of the memory system.  In a memory-mapped I/O organization there is no specific input or output instructions.  The CPU can manipulate I/O data residing in interface registers with the same instructions that are used to manipulate memory words.  Each interface is organized as a set of registers that respond to read and write requests in the normal address space.  Typically, a segment of the total address space is reserved for interface registers, but in general, they can be located at any address as long as there is not also a memory word that responds to the same address.  Computers with memory-mapped I/O can use memory-type instructions to access I/O data.  It allows the computer to use the same instructions for either input-output transfers or for memory transfers.  The advantage is that the load and store instructions used for reading and writing from memory can be used to input and output data from I/O registers.  In a typical computer, there are more memory-reference instructions than I/O instructions. With memory mapped I/O all instructions that refer to memory are also available for I/O. iv. Example of I/O Interface: An example of an I/O interface unit is shown in block diagram.  It consists of two data registers called ports, a control register, a status register, bus buffers, and timing and control circuits.  The interface communicates with the CPU through the data bus. The chip select and register select inputs determine the address assigned to the interface.  The I/O read and write are two control lines that specify an input or output, respectively. The four registers communicate directly with the I/O device attached to the interface.  The I/O data to and from the device can be transferred into either port A or Port B.  The interface may operate with an output device or with an input device, or with a device that requires both input and output.  A command is passed to the I/O device by sending a word to the appropriate interface register.  In a system like this, the function code in the I/O bus is not needed because control is sent to the control register, status information is received from the status register, and data are transferred to and from ports A and B registers.  Thus the transfer of data, control, and status information is always via the common data bus. The distinction between data, control, or status information is determined from the particular register with which the CPU communicates.  The control register receives control information from the CPU.

The need for safe and effective medical image communication is growing. Both ends of the connection, the sending and receiving ends, must perform image compression before sending. There are a few different methods for compressing images, but the two most used are the Discrete Cosine Transform (DCT) and the Discrete Wavelet Transform (DWT). In the subject of Very Large Scale Integration (VLSI), logic devices are packed into eversmaller spaces. We find VLSI circuits in our computers, cars, and even the most cuttingedge digital cameras and mobile phones. When it comes to modeling and describing architectures, Hardware Description Language (HDL) is unfailingly correct. Different from conventional programming languages, both the semantics and the rules are radically novel. From the system level down to the gate level, Very High Speed Integrated Chip HDL (VHDL) provides a logical description of the structure and operation of digital systems that may be used as a model language for design and simulation. For VHDL-based circuit synthesis, implementation, and simulation, Xilinx's ISE suite, in conjunction with Modelsim, is the best Electronic Design Automation (EDA) tool you can use. All conceivable logical operations may be implemented by use of Field Programmable Gate Arrays (FPGAs). Many new logic design strategies have emerged as a consequence of the convergence of complementary Metal Oxide Semiconductor (CMOS) and Pass Transistor Logic (PTL) technologies. Eliminating design complexity while creating logic functions is made possible by the Gate Diffusion Input (GDI) approach.

The rapid scaling of deep learning and large language models exposes fundamental theoretical bottlenecks rooted in simplifying assumptions: pairwise graph interactions and flat Euclidean parameter spaces. This report synthesizes two revolutionary frameworks—the Structure-Coupling-Aggregation (SCA) framework and Information Geometry (IG)—to provide a dual-lens for advancing AI foundations. The SCA framework offers a rigorous topological decomposition, proving graphs are universally expressive but incur a severe Aggregation Complexity Gap and BIC-penalty gap when modeling symmetric higher-order interactions (HOIs) due to a combinatorial explosion of parameters. Complementarily, IG treats statistical model spaces as curved Riemannian neuromanifolds governed by the Fisher Information Metric, enabling curvature-aware optimization and explaining phenomena like GNN over-squashing and model generalization. The integration of SCA and IG demonstrates that incorporating HOIs via geometric curvature (e.g., explosive neural networks) significantly boosts capacity and robustness, providing a mathematically optimal path forward for designing coherent and parsimonious machine intelligence architectures.

The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein.

The integration of renewable energy sources (RESs), such as wind and solar, introduces significant uncertainties into power system operations, complicating Available Transfer Capability (ATC) assessment. A key factor in ATC determination, the Transmission Reliability Margin (TRM), accounts for uncertainties like load variations, generation fluctuations, and network dynamics. The traditional deterministic TRM methods often fail to capture the stochastic nature of modern grids, leading to inaccurate estimations. This paper reviews the TRM assessment methodologies, emphasizing probabilistic approaches that enhance accuracy in high-RES environments. It explores adaptive statistical techniques, such as rolling window analysis, for dynamic TRM computation. Key challenges, emerging trends, and potential solutions are discussed to support the development of robust ATC modeling frameworks for secure and efficient renewable energy integration.

In this article we implement a stochastic modeling technique for simulating the communication between processors and arbitration among buses. The stochastic models implemented with queues have been used to estimate through simulation of different arbitration policies the power consumption and delays, as well as estimate average or worst case scenarios that could occur with different architectures and arbitration policies . This idea could then be extended to writing probabalistic test benches to analyze the performance of different architectures as well as device and test arbitration policies which would attempt to optimize the power consumption and buffer lengths with constraints on the average delay.