Current Mode

This study describes a memcapacitor emulator without a multiplier that make use of second-generation current conveyor (CCII), operational transconductance amplifier (OTA) and the fewest possible passive components. The proposed memcapacitor is proved mathematically and verified using several simulation approaches, such as process corner, non-volatile and hysteresis analysis. Also, provided the layout of CCII and OTA as well. The standard CMOS 90 nm technology is used in the Cadence Virtuoso tool to simulate the proposed memcapacitor emulator. This article also includes the use of memcapacitor emulator in the applications of R-C frequency selective network as well as adaptable neuromorphic structure. To investigate the experimental outcomes, an experimental setup was constructed with commercially available integrated circuits (ICs) CCII's AD844AN and OTA's CA3080EZ.

In this paper, current-mode second-order square-root-domain highpass, and allpass filters are proposed by using only a circuit. Literature survey showed that, current-mode second-order highpass and allpass filters are not proposed. The proposed circuit is derived from first-order blocks. The presented of the first-order blocks are based on the state-space synthesis method with two subcircuit; square-root and squarer/divider circuits. The proposed circuit has one input and one output and can realize highpass (HP), and allpass (AP) responses without any changes in the circuit topology. Only MOS transistors and grounded capacitors are required to realize the filter circuit. The center frequency of the filters can be electronically tuned by changing external currents. Time and frequency domain simulations are performed using PSPICE program for the filters to verify the theory and to show the performance of them. For this purpose, the filter is simulated by using TSMC 0.35 ¿m Level 3 CMO...

This paper proposes a new current-mode 5th-order differential type class-AB log-domain elliptic lowpass filter for video frequency applications. The design is based on the state-space synthesis method. The proposed filter has 5.75 MHz cut-off frequency with maximum 0.177 dB passband ripple and attenuation greater than 40 dB at 7.88 MHz. Only BJTs and grounded capacitors were used, and operated with single power supply of 2.5 V. Since the parameters of proposed filter are tunable, it is easy to control of cut-off frequency. This adjustment is accomplished by changing external currents. SPICE simulations are given to confirm the theoretical analysis. For this purpose, the filter is simulated by using both idealized BJT models and AT&T CBIC-U2 type transistors.

Akıllı DA-DA Dönüştürücülerinin özellikle yenilenebilir enerji kaynakları (RES) uygulamalarında artan kullanımı göz önünde bulundurulduğunda, uygun bir kontrol sistemi tasarımı, verim ve güvenilirlik açısından son derece önemlidir. Normal çalışma koşullarında, her DA-DA güç dönüştürücü yapısı, genellikle dönüştürücü çıkışında sabit bir gerilim kontrol bloğuna ve dönüştürücünün yarı iletken güç anahtarı tarafında bir görev döngüsü kontrolü bloğuna sahiptir. Klasik yöntemlerde, geri besleme kontrol döngülerinde orantılı-integral türev (PID) kontrolörü kullanılmaktadır. Bu kontrolör ile ilgili temel sorun, DA-DA dönüştürücüler gibi doğrusal olmayan sistemlerde, davranışlarının yalnızca sistemin çalışma noktasında en uygun olmasıdır. Bulanık mantık denetleyicisi, bu tür sistemlerin büyük sinyal değişimi senaryolarındaki davranışlarını iyileştirmek için kullanılabilir. Ek olarak, normal şartlarda ve dönüştürücüde bir hata olması durumunda, sistemin davranışında önemli bir iyileşme görülmektedir. Bu çalışmada, yükseltici dönüştürücüyü kontrol etmek için bulanık mantık ilkeleri kullanılmıştır. Dönüştürücünün çıkış gerilimi, gürültü, yük değişimleri ve giriş gerilimi değişimleri gibi sistem hatalarına karşı kararlı olmalıdır. Tasarlanan bulanık denetleyicideki yenilik, bu denetleyicinin daha önce tasarlanan kontrolörlerin giriş-çıkış bilgisine ve deneysel olarak zamana bağlı değişkenlere dayanmasıdır. Bulanık mantık denetleyicisini kullanarak, sistem parametreleri bu oynamalara karşı kararlı olması sağlanmaktadır. Performans koşulları MATLAB yazılımı kullanılarak benzetilmiştir. Anahtar Kelimeler: DA-DA dönüştürücüsü, Yenilenebilir enerji uygulamaları, Yüksek kazançlı dönüştürücüler, Yükseltici yapılar.

Mixed-signal sensor interface circuits enable interaction between analog real-world signals and digital processing systems. This paper presents the design and analysis of such circuits for real-time monitoring applications. The study focuses on analog front-end design, signal conditioning, noise considerations, comparator-based threshold detection, and analog-to-digital conversion techniques. Key components such as operational amplifiers, comparators, filters, and analog-to-digital converters are discussed. Design challenges including noise, nonlinearity, offset, power consumption, and layout parasitics are also analyzed. These circuits play a crucial role in improving system accuracy, sensitivity, reliability, and response time in modern electronic applications.

Two new voltage-mode multifunction filters using only one positive-type second generation current conveyor (CCII+) or current feedback op-amp (CFOA, commercially available chip AD844), two resistors and two capacitors are proposed. The proposed filters which have three inputs and one output can generate all biquadratic filtering functions namely: low-pass (LP), band-pass (BP), high-pass (HP), band-reject (BR) and allpass (AP) at the output terminal by selecting different input signal combinations. Literature survey concerning the component number is also discussed. PSpice simulations and experimental results confirm the results of the theoretical analysis.

The Q p weak experiment will measure the parity-violating elastic e-p scattering asymmetry to extract the weak charge of the proton. The experiment employs a toroidal magnet to focus electrons scattered at 8 • ± 2 • , corresponding to Q 2 ∼ 0.03 (GeV/c) 2 , on eight Čerenkov detectors located in the focal plane of the spectrometer. Since the asymmetry is proportional to Q 2 , it is crucial to obtain an accurate measure of the acceptance-averaged value of Q 2 . A tracking system will be used in a low-rate counting mode, allowing individual events to be observed. This will enable a determination of the average Q 2 by measuring the scattering angle and interaction vertex, for mapping the response across the surface of the Čerenkov detectors, and for the dilution of the Čerenkov detector signal by background.

The Q-weak experiment at Jefferson Laboratory measured the parity violating asymmetry (A P V ) in elastic electron-proton scattering at small momentum transfer squared (Q 2 = 0.025 (GeV/c) 2 ), with the aim of extracting the proton's weak charge (Q p W ) to an accuracy of 5%. As one of the major uncertainty contribution sources to Q p W , Q 2 needs to be determined to ∼1% so as to reach the proposed experimental precision. For this purpose, two sets of high resolution tracking chambers were employed in the experiment, to measure tracks before and after the magnetic spectrometer. Data collected by the tracking system were then reconstructed with dedicated software into individual electron trajectories for experimental kinematics determination. The Q-weak kinematics and the analysis scheme for tracking data are briefly described here. The sources that contribute to the uncertainty of Q 2 are discussed, and the current analysis status is reported.

The Q p weak experiment will measure the parity-violating elastic e-p scattering asymmetry to extract the weak charge of the proton. The experiment employs a toroidal magnet to focus electrons scattered at 8 • ± 2 • , corresponding to Q 2 ∼ 0.03 (GeV/c) 2 , on eight Čerenkov detectors located in the focal plane of the spectrometer. Since the asymmetry is proportional to Q 2 , it is crucial to obtain an accurate measure of the acceptance-averaged value of Q 2 . A tracking system will be used in a low-rate counting mode, allowing individual events to be observed. This will enable a determination of the average Q 2 by measuring the scattering angle and interaction vertex, for mapping the response across the surface of the Čerenkov detectors, and for the dilution of the Čerenkov detector signal by background.

The process of uranium stripping from tri-n-butyl phosphate in kerosene by urea solutions was investigated at the volume ratio of the organic and aqueous phases of (1-10) : 1 in the temperature range of 20-60 °C. The stripping of uranium from a loaded organic phase increased with increasing urea content in the solution and with increasing temperature. Maximum recovery of uranium from tributyl phosphate was obtained using a solution that contained 8-12 mol/l of urea. The application of a urea solution for uranium stripping resulted in the strip product solution containing 200-240 g/L of uranium. The process of uranium stripping by dilute nitric acid was also investigated. Results of uranium stripping by the two methods are compared and discussed.

The thermal neutron capture cross section of 88Zr was recently reported to be the second largest in nature with the largest resonance integral measured. Presumably, these very large values are caused by a resonance or resonances very near thermal energy. Determining their energies and widths, and hence the shape of the cross section away from thermal energies,is useful for applications. The short half-life (83.4 days) and associated large background, renders direct measurements of the neutron capture cross section impossible using current techniques. However, it is possible to measure the total neutron cross section, and hence the resonance properties, using the newly commissioned Device for Indirect Capture Experiments on Radionuclides (DICER) at the Los Alamos Neutron Science Center (LANSCE). Transmission measurements are utilized as a surrogate method to perform capture measurements. The 88Zr needed for a DICER measurement was produced at the Isotope Production Facility (IPF) and...

A/D converters for single chip CMOS imagers have often been designed using the column-parallel approach, employing a slow A/D converter for each column of the sensor array. This thesis investigates a serial approach utilizing a single fast A/D converter to process all of the imager pixels. If power scales linearly with frequency in a given A/D architecture, power dissipation for the two approaches should be comparable. However, the serial approach should occupy less area since only the cost of one A/D converter is incurred. A figure ) is introduced to verpowersarea ify this theory by comparing previously reported A/D approaches after appropriate technology, speed, and supply scaling. Camera system specifications require a single serial A/D converter to have 10b resolution at a 3MHz sampling rate for a CIF (352x288) imager array running at 30 frame Area minimization, power minimization, and the ability to build the A/D in a standard CMOS process are extremely important for consumer product applications. A single slope A/D architecture with a subnanosecond time digitizer shows promise for optimizing figure of merit over pipelined and folding interpolating approaches. This work focuses on the design issues of the 3MHz single-slope based A/D converter. Architectures appropriate for extending this A/D converter to 12MHz for four times CIF image arrays (704x576) are discussed. The 3MHz converter was designed, simulated, and laid out in a 0.35um CMOS technology. At 3.3V supply, 25°C and nominal process conditions, the converter dissipates 29 mW while occupying 0.3 mm 2 . A 12MHz trislope extension of this converter is estimated to dissipate 37 mW in 0.4 mm 2

The aim of the paper is to investigate the bifurcation behavior of the power-factor-correction (PFC) boost converter under a conventional peak current-mode control. The converter is operated in continuous-conduction mode. The bifurcation analysis performed by computer simulations reveals interesting effects of variation of some chosen parameters on the stability of the converter. The results are illustrated by time-domain waveforms, discrete-time maps and parameter plots. An analytical investigation confirms the results obtained by computer simulations. Such an analysis allows convenient prediction of stability boundaries and facilitates the selection of parameter values to guarantee stable operation.

In this paper, a novel current mode CMOS four-quadrant analog multiplier circuit is presented. The multiplication is implemented by four translinear loops with MOS transistors operating in weak inversion. Information carrying signals are differential balanced currents. The multiplier circuit has been implemented in a test chip in a standard 0.35 /spl mu/m CMOS technology. The experimental measurements (dc bias current of 250 nA and a power supply of 2.0 V) show a bandwidth of 200 kHz and a THD figure value lower than 0.9 %. The multiplier features a wide signal dynamic range and linearity, low power consumption (the maximum power consumption is of 5.5/spl middot/10/sup -6/ W) and very low area (18.7 /spl middot/10/sup -3/ mm/sup 2/). The multiplier is suitable for a wide range of analog signal processing applications. Due to the low power and silicon area consumption, scalability and modularity can be also easily integrated in massive parallel systems.

In this paper, a novel current mode CMOS four-quadrant analog multiplier circuit is presented. The multiplication is implemented by four translinear loops with MOS transistors operating in weak inversion. Information carrying signals are differential balanced currents. The multiplier circuit has been implemented in a test chip in a standard 0.35 /spl mu/m CMOS technology. The experimental measurements (dc bias current of 250 nA and a power supply of 2.0 V) show a bandwidth of 200 kHz and a THD figure value lower than 0.9 %. The multiplier features a wide signal dynamic range and linearity, low power consumption (the maximum power consumption is of 5.5/spl middot/10/sup -6/ W) and very low area (18.7 /spl middot/10/sup -3/ mm/sup 2/). The multiplier is suitable for a wide range of analog signal processing applications. Due to the low power and silicon area consumption, scalability and modularity can be also easily integrated in massive parallel systems.

A fully electronic medium density DNA micro array is presented using a CMOS process extended by gold electrodes. The chip provides 128 sensor sites, in-sensor site current-mode A/D conversion, peripheral circuitry including bandgap and current references, D/A-converters to provide electrode bias voltages, calibration circuitry, and a 6 pin interface for power supply and serial digital data transfer.

The four terminal Current feedback op-amps (CFOA) with an external compensation pin, such as AD844, have received prominent attention during the past decade as alternative building blocks for analog circuit design because of their significant advantages over the traditional voltage-mode op-amp (VOA). A popular application of CFOAs has been in realizing voltage-mode (VM) and current-mode (CM) biquad filters. Previously known universal CM biquads (i.e. those capable of realizing all the five generic filter functions namely, low-pass, band-pass, high-pass, notch and all-pass) realizable with CFOAs require two to nine CFOAs. Although a few dual-function/three-function single-CFOA-based CM circuits have appeared in literature, no single-CFOA-based canonic universal CM biquad with explicit CM output has been reported in the literature up until now. This paper fills this void by presenting a set of eight minimal universal CM biquads all of which are realizable with only a single CFOA. The non-ideal analysis of the proposed circuits has been presented, their comparative features, advantages and limitations have been brought out. The workability of all the proposed circuits has been confirmed by PSPICE simulations and experimental results based upon AD844 type CFOAs.

This article presents a new dual-mode (i.e. both current-mode and voltage-mode) quadrature sinusoidal oscillator using two Voltage Differencing Current Conveyors (VDCCs), two resistors and two capacitors. The proposed configuration use only grounded passive elements and enjoys independent resistor/electronic tuning of both Condition of Oscillation (CO) as well as Frequency of Oscillation (FO). The quadrature current and voltage mode outputs of this circuit are available at appropriate impedance terminals. The behavior of presented oscillator is also examined under non ideal/parasitic conditions. The validity of the proposed configuration has been confirmed by SPICE simulations with TSMC 0.18μm process parameters.