Papers by Mohammad Sharifkhani
IEEE Journal of Solid-State Circuits, 2009
Based on the dynamic criteria for data stability, we introduce segmented virtual grounding archit... more Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 20 bit eSRAM unit is implemented in a regular 0.13 m CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% noise margin enhancement for this scheme when a subthreshold cell is accessed.
An Analysis of Stepwise Adiabatic Circuits
2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020
In this paper, an analysis on the stepwise adiabatic circuits is presented. In this analysis, the... more In this paper, an analysis on the stepwise adiabatic circuits is presented. In this analysis, the energy consumption of stepwise adiabatic circuits for the case where it is possible to recycle the charge stored on the load capacitor is studied. As a results of the analysis, energy consumption equations are presented which accurately model the efficiency of the stepwise adiabatic circuits. The proposed analysis shows stepwise adiabatic circuits are able to decrease the total energy by a factor of $N$ if the load capacitor is charged in $N$ steps and then discharged in $N$ steps. Energy consumption equations suggest even for small values of the tank capacitors the energy is reduced significantly. For example, if the tank capacitors are equal to the load capacitor, energy is reduced by 40% for N=2, 55% for N=3, and energy saving is increased with N. Simulation results in 0.18µm technology show the errors of the proposed derivations are less than 2% in different scenarios.
Analog Integrated Circuits and Signal Processing, 2020
A high energy-efficiency and low-area switching method is proposed for the successive approximati... more A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-todigital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC switches is lower than the conventional and some other methods, which avoids further complicating the logic circuit as well as increasing wiring and area. Moreover, only one voltage source is used as a reference voltage, which makes us needless to have an extra voltage source that must be very accurate.
Integration, 2020
Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to ach... more Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier o... more A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small crosscoupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process-VDD-temperature corners, and Monte Carlo simulations along with silicon measurements in 0.18 µm. The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input V cm range in f clk = 500 MHz.
AEU - International Journal of Electronics and Communications, 2018
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation ... more A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.
Microelectronics Journal, 2017
In this paper, a method is presented to reduce the power consumption of the two-stage dynamic com... more In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power consumption significantly, the method does not affect the dynamic behavior of the comparator such as speed or offset voltage. This method reduces the power consumption by 30% to 58%. Post Layout Simulations as well as analytical derivations and schematic simulations prove the beneficial performance of the proposed method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedu... more A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching procedure and they are verified using MATLAB simulations. Postlayout simulations in 0.18 µm technology and a fabricated PCB using off-the-shelf components prove the analytical derivations and the benefits of the proposed switching procedure.
AEU - International Journal of Electronics and Communications, 2016
A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage sw... more A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator.
General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016
An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this met... more An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMOS 0.18 μm technology, silicon measurements, and measurements based on discrete components confirm the precision of the analytical derivations. Using the proposed design methodology, a capacitive tank has been designed which reduces the energy consumption by 20% while the total size of the tank capacitors is smaller than 0.4CL. Additionally, a new switching procedure for the SACs is presented. This procedure stabilizes the voltage levels without reverse switching, unlike previously reported methods. Thus preserving the energy efficiency, it improves the speed by a factor of up to two, since the tank recycles its charge inherently. Moreover, the capacitive load can retain its charge after the charging process and let the tank charges another load capacitor. As a result, the proposed switching procedure can be used in multi-cycle circuits such as the capacitive DAC of a SAR ADC in which the load capacitor must hold its charge after charging process is finished.
Electronics Letters, 2016
A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in succ... more A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. This sampling method is proposed to reduce the switching energy. Thanks to the proposed switching method, only one reference voltage (V cm = 1/2V ref) is required which helps to improve the precision of the DAC along with energy reduction compared with those methods that use more than one reference voltage. The switching energy and area of the DAC reduce by 97.66% and 50% compared with the conventional binary weighted DAC.
A 10MHz CTDSM with differential VCO-based quantizer in 90nm
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2013
This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This... more This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in 90nm technology. Obtaining linearity enhancement compared to the conventional design, the modulator achieves the maximum SNDR of 72dB over a 10 MHz bandwidth. The modulator consumes 56.9 mW from a 1.2 V supply.
Bandwidth enhancement of planar EBG structure using dissipative edge termination
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015
ABSTRACT
Low-power CMOS voltage-Mode quaternary latched comparator
2015 23rd Iranian Conference on Electrical Engineering, 2015
In this paper, a low-power CMOS voltage-mode quaternary latched comparator is presented. The prop... more In this paper, a low-power CMOS voltage-mode quaternary latched comparator is presented. The proposed circuit operates in two modes. In comparison mode, it compares the input analog signal with three predefined threshold levels and returns a quaternary digit at the output accordingly, and in latch mode, it saves the output voltage which was generated in the previous mode. In addition to its operation as a quaternary latch in multiple-valued logic (MVL) circuits, the proposed comparator can also be used as a 4-level quantizer in such applications as quaternary data converters. The proposed circuit operates based on three parallel binary comparisons with different comparison characteristics. Designed in a 0.18-μm standard CMOS technology, the circuit exhibits simulation results which show power consumption of 20 μW from 1.8-V power supply while operating at 500 kHz. Also, in order to evaluate the functionality of the proposed quaternary latched comparator, a proof-of-concept functional prototype is built using off-the-shelf components.
A low-power digital to analog converter for SAR ADCs using one reference voltage
2015 23rd Iranian Conference on Electrical Engineering, 2015
A new low-power capacitive structure and its switching scheme for Successive Approximation Regist... more A new low-power capacitive structure and its switching scheme for Successive Approximation Register (SAR) Digital to Analog Converter (DAC) is presented. The proposed method reduces power consumption by 93% and area by 50% compared to the conventional binary-weighted DAC. Moreover, only one reference voltage is used to avoid the effect of common mode voltage (Vcm) non-idealities on precision.
General structure for base-m capacitive digital to analog converter
2015 23rd Iranian Conference on Electrical Engineering, 2015
A general structure for capacitive digital to analog converters (CDACs) is presented in which non... more A general structure for capacitive digital to analog converters (CDACs) is presented in which non-binary, base-m capacitor sizing is introduced. Base-m sizing opens new trade-offs in area and INL/DNL efficiency. A base-4 (i.e., quaternary-weighted) DAC (QWDAC) is designed as an example of the proposed structure. This converter is designed and simulated after being laid out in a 0.18-μm CMOS technology at 1.8V power supply. In a typical 6-bit DAC using base-4 technique, the area reduces by a factor of three as compared to the conventional binary weighted DAC. Several Monte-Carlo simulations suggest that capacitor mismatch effect of the base-m structure is reduced owing to the smaller number of separate capacitors involved in the generation of a desired code. Moreover, the general base-m structure can be generalized to two-stage CDAC and C-2C architectures to improve the area efficiency.
Electronics Letters, 2015
A new switching method for the stabilisation of a one-dimensional capacitor array tank for the st... more A new switching method for the stabilisation of a one-dimensional capacitor array tank for the stepwise charging of a load capacitor is presented. In this method, the tank capacitor configuration is rearranged in a circular manner once the charging process of a load capacitor finishes and before the charging process of a new load capacitor begins. Unlike previously reported methods, this method does not require backward switching for the stabilisation of tank capacitor voltages. Hence, the proposed method reduces the number of charging process steps by a factor of up to 2 compared with the conventional method. Moreover, since the tank recycles its charge inherently, the capacitive load can retain its charge after the charging process finishes without the problem of instability. Systematic MATLAB simulation, post-layout simulation in 0.18 μm technology and a fabricated printed circuit board prove the benefits of the proposed method and the provided analytical derivations.
High throughput, High SNR digital delta sigma modulator for fractional-N frequency synthesizer
2015 23rd Iranian Conference on Electrical Engineering, 2015
In this paper, a high throughput, reduced hardware digital delta sigma modulator (DDSM) for fract... more In this paper, a high throughput, reduced hardware digital delta sigma modulator (DDSM) for fractional frequency synthesizer is presented. To increase the throughput of DDSM, a special bus splitting scheme is applied which consists of a first order error feedback modulator in prior stage and a third order delta sigma modulator using concentrator in subsequent stage. The concentrator reduces the bits number of the modulator output to 1. The single bit output used in the last stage of proposed structure makes it useful as dual modulus divider (DMD) controller in fractional frequency synthesizer. The proposed structure is implemented on Xilinx Virtex 5 FPGA and yields 104 dB SNR while the required hardware is reduced compared to the previous works.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015
The conventional theory of super regenerative systems (SRS) has been divided into distinct modes ... more The conventional theory of super regenerative systems (SRS) has been divided into distinct modes of operation and limiting assumptions. These assumptions make the analysis of these systems inaccurate for wide bandwidth applications. In this paper, a novel theory based on the analysis of time varying systems using Magnus expansion is proposed which unifies all modes of operation and formulates the system response with high accuracy for a wide range of practical applications. Therefore, the theory can be used for the design of systems with wider bandwidth and higher data rates. Using the proposed theory, it is possible to analytically describe the effects of the parasitic elements and inter symbol interference as well as different parameters of the output signal such as instantaneous phase and amplitude. The proposed method is utilized for the design of a UWB pulse transmitter. Moreover, a new super regenerative structure is proposed which operates as a receiver. The accuracy of the proposed model is verified by various simulations and comparisons with the conventional model. Simulations show that the accuracy improved more than 10 times that models systems with quality factor as low as with acceptable precision.
A DLL-based frequency synthesizer for VHF DVB-H/T receivers
2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010
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Papers by Mohammad Sharifkhani