Embedded System Design

In this paper, a new VLSI architecture is provided for the application of quad-input and dual-output Fuzzy Logic Controller (FLC) with maximum seven fuzzy membership functions. Our approach is based on classical three stage implementation process -fuzzification, rule inference and defuzzification cores. An innovative design methodology is proposed by splitting the process between DSP processor and FPGA to implement run time configurable FLC. Since the target application takes a maximum of 4 inputs and 7 membership functions, the rule base comprises of 2401 (7 4 ) rules. It increases the complexity of the overall system. To minimize this effect, rule reduction VLSI architecture is suggested to bind the no of rules to 16 (2 4 ). The Rule inference is designed for seeking the maximum frequency of operation for targeted Virtex 5 LX110T FPGA. The simulation results obtained with Modelsim 6.3g show satisfactory results for all test vectors.

Support for Run-time Verification (RV) has mostly been provided by software mechanisms, via the instrumentation of code for observing (monitor) and handling deviations from specification. Although this approach is fitting for some domains, it can have a nefarious influence in embedded real-time systems, impacting the system from the analysis to the operation stages. A novel alternative to code instrumentation is the embedding of such mechanisms directly in hardware, thus negating the impact in system properties, namely timeliness. The availability of softprocessors and companion System-on-a-Chip (SoC) Intellectual Property cores enable the hardware-based approach to RV. This paper addresses the foundations for RV support via hardware mechanisms. A flexible observer entity is defined, to be merged into a SoC architecture. Monitoring is performed at the SoC bus that interconnects processor and peripherals, enabling the gathering of information regarding events of interest occurring du...

The advancement in technology in transportation sector has widened the risk of traffic mishaps causing loss to property, lives of humans and animals. The proposed system provides a solution to decrease the frequency of death. Infrared sensor, Eye blink sensor, GSM and GPS modules are used in the proposed system. If any accident occur, system informs in the form of message which includes the location of the travelling person using GSM and GPS modules to police, guardians and ambulance and myRIO will control all the operations involved. A drowsiness detection system is congregated in addition to prevention of general road accidents, which continuously monitor the driver's state and if the driver feels sleepy then an alarm is triggered if the time exceeds threshold time and it stops once the driver wakes up. The proposed system is implemented using LabVIEW and the controller is myRIO which can run the operation in stand-alone mode.

Development of future generation computer architectures requires fast and accurate simulation tools that allow to test, verify, and analyze the behavior of the given architecture along with the intended workload. We present a simulation framework based on a structural architecture description language that uses the open source compiler infrastructure LLVM to dynamically translate instruction sequences of the simulated architecture into machine instructions of the host machine. We show that the optimizations in the simulator and the LLVM compiler lead to an outstanding runtime performance: A 5-stage MIPS core is simulated at a peak performance of up to 800 MHz.

Performing flow control inside a network can effectively avoid packet loss due to buffer overflow in switches. IEEE 802.3x exercises a per-hop link-based flow control scheme to achieve this goal. IEEE 802.1Qbb Priority-based Flow Control (PFC) improves IEEE 802.3x by proposing a per-hop perservice-class flow control scheme. Although PFC is better than IEEE 802.3x, it still suffers from several serious problems such as congestion spreading, deadlock, and packet loss. In this work, we propose a perhop per-flow scheme to mitigate these problems. We design, implement, and evaluate the performance of our scheme in P4 hardware switches. Experimental results show that (1) our scheme outperforms PFC in many aspects including avoiding congestion spreading, deadlock, and packet loss, and (2) the bandwidth overhead of our scheme is only slightly higher than that of PFC.

Nowadays, multimedia streaming is a common service on the Internet including both fixed and mobile networks. The RTP protocol is usually used to transfer the media. The RTCP protocol is an accompanying protocol for the RTP and it is used for feedback transmission in order to control multimedia session behaviour. The issue is the bandwidth dedicated for the RTCP protocol. As defined in the RTP specification, it is limited to 5 % of the total allowed bandwidth. This is a limiting factor for large-scale media streaming services based on Source-Specific Multicast (SSM) since the RTCP bandwidth is shared among all the receivers. It causes large delays in sending feedback data from each receiver. For the purpose of solving this issue, a hierarchical structure of receivers with summarisation nodes has been proposed. The paper introduces an optimization of this hierarchical structure in order to achieve the lowest feedback transmission intervals. The proposal is supported by a simulation in...

This document is responding to the MoBIES "Automotive Challenge Problems". It is prepared by the Mobies Phase 1 Berkeley team, whose project is entitled "Process-Based Software Components for Networked Embedded Systems." The problems posed in the "Automotive Challenge Problems" paper are addresses one by one and our views on the problems are presented. As part of the Mobies phase I effort at Berkeley, we are developing a software framework called Ptolemy II. Ptolemy II is a component-oriented modeling and design framework written in Java. It is intended primarily to facilitate experimentation with design techniques and methodologies. We believe that a number of the challenge problems posed by the Mobies phase I team at Berkeley have been already addressed in the Ptolemy project, and for a number of others, we have ideas that we expect will lead to a solution. The Ptolemy project studies heterogeneous modeling, simulation, and design of concurrent systems. The focus is on embedded systems [Lee], particularly those that mix technologies, including for example analog and digital electronics, hardware and software, and electronics and mechanical devices. The focus is also on systems that are complex in the sense that they mix widely different operations, such as signal processing, feedback control, sequential decision making, and user interfaces.

This document is responding to the MoBIES "Automotive Challenge Problems". It is prepared by the Mobies Phase 1 Berkeley team, whose project is entitled "Process-Based Software Components for Networked Embedded Systems." The problems posed in the "Automotive Challenge Problems" paper are addresses one by one and our views on the problems are presented. As part of the Mobies phase I effort at Berkeley, we are developing a software framework called Ptolemy II. Ptolemy II is a component-oriented modeling and design framework written in Java. It is intended primarily to facilitate experimentation with design techniques and methodologies. We believe that a number of the challenge problems posed by the Mobies phase I team at Berkeley have been already addressed in the Ptolemy project, and for a number of others, we have ideas that we expect will lead to a solution. The Ptolemy project studies heterogeneous modeling, simulation, and design of concurrent systems. The focus is on embedded systems [Lee], particularly those that mix technologies, including for example analog and digital electronics, hardware and software, and electronics and mechanical devices. The focus is also on systems that are complex in the sense that they mix widely different operations, such as signal processing, feedback control, sequential decision making, and user interfaces.

The main aim of this bandwidth optimization is to transmit data packets from the sender to the receiver without any time delay and loss of packets. Using high bandwidth utilization we can send data to the users with low delay. In this paper, we discussed many algorithm techniques which can minimize the energy consumption, minimal time delay, avoiding un-usable bandwidth on the routing network, execution time. It makes a flexible network between users, avoid traffic rules and provide good network services between the peer to peer systems. The main purpose of this optimization is to provide quality packets from sender to receiver and vice versa at the same time, like a video or audio data by initializing without loss of any IP address. It builds a large bandwidth to transmission of data from source to destination. And it reduces the unusable bandwidth. We used some logarithms to transfer the data in equal time and increase bandwidth as well as transmission of speed.

The Internet has historically offered a single level of service, that of "best effort," where all data packets are treated with equity in the network. The Internet itself does not offer a single level of service quality, and some areas of the network exhibit high levels of congestion and consequently poor quality, while other areas display consistent levels of high quality service. This is being solved by defining methods of "Quality of Service" (QoS) to TCP. In this document ideas of the concepts for QoS are discussed.

In this paper it is described an algorithm, implemented in a biaxial solar tracker, that can instantly calculate the sun position at the latitude and longitude of a set point. The algorithm can drive up to two engines which are able to change the position of a solar panel, in order to increase its efficiency, for tracking the sun in its movement from east to west (azimuth motion) and in its elevation up to solar noon (tilt motion). The whole system is adaptable to various types of structures as it involves a cycle of self-learning of the structure and consequently the adaptation of calculations to the tracker on which it is installed.

ZUKERMAN, M., and cHAN, s.: 'Congestion control by maintaining fairness in high speed networks'. Proc. Globecom '94, December 1994, CHAN, s., WONG, E., and KO, K.T.: 'Fair packet discarding for controlling ABR traffic in ATM networks', ZEEE Trans. Commun.,

This review explores the current state-of-the-art wireless and mobile optical chemical sensors and biosensors. The review is organised into three sections, each of which investigates a major class of wireless and/or mobile optical chemical sensor: (i) optical sensors integrated with a radio transmitter/transceiver, (ii) wearable optical sensors, and (iii) smartphone camera-based sensors. In each section, the specific challenges and tradeoffs surrounding the (bio)chemical sensing mechanism and material architecture, miniaturisation, integration, power requirements, readout, and sensitivity are explored with detailed examples of sensor systems from the literature. The analysis of 77 original research articles published between 2007 and 2017 reveals that healthcare and medicine, environmental monitoring, food quality, and sport and fitness are the target markets for wireless and mobile optical chemical sensor systems. In particular, the current trend for personal fitness tracking is driving research into novel colourimetric wearable sensors with smartphone readout. We conclude that despite the challenges, mobile and wearable optical chemical sensor systems are set to play a major role in the sensor Internet of Things.

Wireless chemical sensors are increasingly finding use as analytical devices in healthcare diagnostics, wearable sensing (sweat analysis) and in the rapidly emerging area of the Sensor Internet of Things (SIoT). In such wireless scenarios, the application of fluorescencebased sensors is lagging behind other types of transduction mechanisms. In this work a new low-cost and highly portable wireless fluorimeter for optical chemical fluorescence intensity measurements is presented (bill-of-materials approximately €20). The fluorimeter is programmed and communicates wirelessly with mobile devices or personal computers by radio-frequency identification (RFID) or near-field communication (NFC). This novel mobile analytical system is highly adaptable for use with different fluorescent sensor chemistries and analytes. The fluorimeter has been evaluated in the laboratory in two sets of proof-ofconcept experiments: firstly fluorimetry in solution, where the fluorescence intensities of fluorescein were recorded, and secondly chloride sensing via a paper-immobilised quinine sulphate fluorescent indicator. The latter represents the first demonstration of wireless (radio-frequency) fluorescence-based chloride sensing. Satisfactory analytical performance was achieved in the entire range of sweat chloride concentrations. The wireless fluorimeter system presented here could make a significant contribution to several emerging areas of

This review explores the current state-of-the-art wireless and mobile optical chemical sensors and biosensors. The review is organised into three sections, each of which investigates a major class of wireless and/or mobile optical chemical sensor: (i) optical sensors integrated with a radio transmitter/transceiver, (ii) wearable optical sensors, and (iii) smartphone camera-based sensors. In each section, the specific challenges and trade-offs surrounding the (bio)chemical sensing mechanism and material architecture, miniaturisation, integration, power requirements, readout, and sensitivity are explored with detailed examples of sensor systems from the literature. The analysis of 77 original research articles published between 2007 and 2017 reveals that healthcare and medicine, environmental monitoring, food quality, and sport and fitness are the target markets for wireless and mobile optical chemical sensor systems. In particular, the current trend for personal fitness tracking is d...

Traditional supermarkets face several challenges, such as restricted shopping hours and long checkout queues, which negatively impact the consumer experience. To address these issues, this paper proposes an intelligent unmanned supermarket system based on the Internet of Things (IoT) and human hand bionics. The system consists of merchandise shelves, handling trolleys, storage cabinets, and servers, interconnected via a local area network (LAN). Each product is tagged with a barcode, stored in a database, and serves as the smallest IoT node, enabling seamless product identification and tracking.The system integrates multiple technologies, including image recognition, location navigation, Wi-Fi communication, and barcode scanning, with a Raspberry PI 3B and a 32-bit microcontroller serving as the core control units. This architecture resolves key challenges in automation, communication, and inventory management, ultimately enabling autonomous product retrieval, transportation, and real-time stock monitoring.

To satisfy the need for teaching wireless and mobile embedded system design, we have designed a complete laboratory, together with the related curriculum updates. We present the lab infrastructure for developing skills spanning physical design of the devices, protocol and application frameworks, as well as the practical issues in its design and use.

In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.

Increasing heterogeneous software and hardware blocks constitute complex ICs known as System on Chip (SoC). These blocks are conceived as intellectual property (IP) cores. Designers are developing SoCs by using IP cores reuse, which include interconnection architecture and interface to peripheral devices.Because of the SoC growing complexity, some researchers tend to concentrate more on the communication rather than the computation aspect. This area of research has leading to the Network on Chip (NoC) Concepts.The research domain of NoC has many applications needing high communication performances. Therefore NoC offers attractive solutions to these applications.One of the goals of NoC technology is to maintain a required Quality of Service (QoS), defined in terms of acceptable parameters values.This paper proposes a presentation of QoS metrics model based on QoS parameters such as Endto-End Delays (EED) and throughputs (Thp), for different applications. This study is based on dynamic routing simulation of a 4x4 mesh NoC behaviour under three communications processes namely TCP, VBR and CBR.

Single-chip multi-processor embedded system becomes nowadays a feasible and very interesting option. What is needed however is an environment that supports the designer in transforming an algorithmic specification into a suitable parallel implementation. In this paper we present and demonstrate an important component of such an environment -an efficient design space exploration algorithm. The algorithm can be used to semi-automatically find the best parallelization of a given embedded application. It employs functional pipelining and data set partitioning simultaneously with source-to-source program transformations to obtain the most advantageous hierarchical parallelizations.

Audio and video are fast becoming an integral part of new computing environments. These media have transport requirements which differ from the normal bursty computer traffic. There is therefore a need to explore transport protocols that can provide different qualities of service. User-space implementations of such protocols are particularly interesting because they can be easily tested and refined. This paper discusses the design and implementation of a high-speed user-space protocol called A1. Its preliminary performance in an ATM environment is presented and compared with an efficient kernel implementation of TCP/IP.

This paper looks at transport services required by applications and proposes using a QoS vector to specify all transport requirements. These ideas have been pursued in the design and development of a new transport protocol called At. Preliminary performance results for At over ATM are presented and compared with an efficient kernel implementation of TCP lIP.

The primary goal of this paper is to propose rate allocation and regulation schemes for unicast and multicast ATM ABR connections. ATM switches must constantly measure the demand and available capacity, and divide the capacity fairly among the contending ABR connections. In order to compute the fair and efficient allocation for each connection, a switch may need to determine the effective number of active connections. The proposed method eliminates the need for estimation of the effective number of active connections altogether, by relying solely on the maximum allocation tracking to achieve fairness. Analysis and simulation results were used to investigate the performance of this method. From the results, it is clear that the method is max-min fair and not excessively sensitive to the measurement interval length.

Architecture exploration in the SoC era is one of the most crucial optimization tasks. The pressure from the market, the enormous number of possible solutions and the computationally hard nature of the optimization tasks is the pushing force behind the quest for fast and good enough optimization algorithms. In this paper, some hardware optimization tasks are represented as weighted graph coloring and clustering problems. Fast and simple heuristics have been developed that find close to optimal solutions.

Modern embedded systems design relies on heavy use of Intellectual Property (IP) and involves both hardware and software design. Moreover, three is an increasing unitization of a diverse set of I/O ports in embedded systems including video, audio, Ethernet, etc. In order to reflect these trends in education in a hands-on manner, a platform is needed that allows fast integration of hardware and software, rapid prototyping capability, and rich IP library covering processor cores, I/O interface standards, arithmetic and signal processing functions, etc. The t-pad development kit, by Terasic, which is based on the DE2-115 development board, designed around the Altera's Cyclone IV FPGA, provides a suitable platform for hands-on education of modern embedded systems design. We have developed a series of example-driven hands-on tutorials to guide students to a comprehensive embedded system design flow in a bottom-up fashion. These tutorials were developed and verified by summer interns from Cañada College who spent Summer 2011 at San Francisco State University. The tutorials are currently being used in an embedded systems design course at SFSU. A course project realizing a complex embedded system in teams of no more than four students is an integral part of this course. The results show that using this platform not only generates excitement and motivation in students, but also enhances their learning and teaches them skills of modern embedded systems design.

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Block diagrams are often used in embedded system design for modeling both plant and controller, typically with continuous and discrete modeling, respectively. Though easy to use, advanced users and implementers of these languages often run afoul of subtle semantic problems these seemingly simple languages can have. Based on the stream-and state-based approaches, this paper discusses how the specialized state-based semantics of continuous-time block diagrams can interoperate hierarchichally with discrete-time block diagrams. The languages presented may serve as a reference of sorts, helping to clarify some of the underlying choices in block diagram language design, and in the process shedding light on the differences between, and limitations of, existing block diagram languages.

Increasing the connectivity of systems at various levels gives rise to potential benefits that is addressed by trends such as the Internet of Things, Cyber-Physical Systems and Cyber-Biosphere. It is inevitable that the vast global network will consist of computationally constrained units. The ability of such systems to adapt while being connected to a global network presents new opportunities. Qualities such as fault tolerance and load sharing may be extended to nodes in the network that initially were devoid of them. On the other hand, an open adaptable system that does not limit its adaptation to pre-defined and pre-containing states needs to be connected to one or more sources that may provide the necessary behavioral units to switch to the new state. Extending computationally constrained nodes with the ability to adapt is in itself challenging, which increases when timely behavior is required due to real-time requirements. The system must then guarantee all deadlines implying the need for deterministic adaptation. The question of when to adapt becomes an important one with real-time deadlines involved. We present our work on a framework that aims to achieve deterministic runtime adaptation on single processor systems thereby enabling such computationally constrained systems to extend their functionality and non-functional qualities.

The introduction of embedded systems equipped with FPGA having a GPP contained inside them (Reconfigurable SoC (RSoC)) create a lot of challenges to OS for resource management. In distributed RSoCs, different applications may run on different RSoCs with variant resource requirements. Due to the variety of applications, a continuous change in demands from OS services (e.g. expected response-time) may exist, also a continuous change in the availability of resources (power and area). These variations can be managed by enabling the OS services to adapt their execution paths (on FPGA and GPP) depending on the application needs and the availability of resources. In this paper, an algorithm for distributed RSoC systems is introduced that enables OS services to execute on both FPGA and GPP along with a dynamic runtime change in execution paths of these services when needed. The algorithm relies on dynamic programming which provides single-criteria optima by taking each constraint alone. In the second step the algorithm finds a multi-criteria solution by local exchange small parts depending on the single-criteria optima solutions. In total a polynomial time heuristic multi-criteria optimization at runtime is obtained.