FIR filters

We present a novel simple blind adaptive compensation method for in-phase/quadrature (IQ) imbalance in m-ary quadrature amplitude modulation (mQAM) coherent optical fiber communication systems. IQ-imbalance compensation is integrated into butterfly-structured finite impulse response (FIR) filters, resulting in a significant computational effort reduction in comparison to conventional methods. A reduction in hardware complexity by a factor of about 3 is achieved by the proposed joint method. The proposed structure is experimentally validated with a 40Gbit/s 16-QAM signal. A 7-dB power penalty reduction is experimentally achieved at a bit error rate (BER) of 10 -3 in the presence of a 10° phase imbalance, confirming the effectiveness of the proposed algorithm. The equalization capability remains even in the presence of group velocity dispersion along the link, which is numerically confirmed with optical fiber transmission up to 1200 km and 20 phase imbalance.

This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM; and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product, and 78% and 59% less energy per sample than DA-based systolic structure and carry saved adder (CSA)-based structure, respectively for the ASIC implementation. A DRAM-based design is also proposed for the FPGA implementation of the reconfigurable FIR filter which supports up to 91 MHz input sampling frequency, and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively when implemented in Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

Design of a low power FIR filter has always been an area of intense research concern. Application of Coordinate Rotation digital computer (CORDIC) algorithm for designing a low power FIR filter is presented in this paper. CORDIC algorithm helps in the computation of complex trigonometric functions by using shift and adds mechanisms avoiding the need for a separate processor in hardware implementation. The challenge of noise interruption in real time video signal capturing is rejected greatly by using CORDIC LMS filter architecture. Also the area, power, and delay of the LMS filter are reduced to a good extent because of CORDIC multipliers. When compared to the previously discussed filter techniques in various works, the proposed technique shows 21.13% reduction in delay and 90.28% decrease in leakage power. Further improvement in dynamic power savings is obtained through clock gating technique applied to the sequential elements in the circuit, which reduces dynamic power dissipation by 70% from the previous works. The comparative study of benchmark filters with their specifications is presented with a detailed analysis of area, delay, leakage, and dynamic power. The video processing using CORDIC LMS filter is verified with MATLAB R 2021A software. The hardware implementation of the proposed architecture is done on a SPARTAN 3E FPGA kit with Xilinx ISE design suite interface. The design is also verified for delay, area, leakage, and dynamic power using CADENCE with GPDK 180 nm library.

The Distribution STATic COMpensator (DSTAT-COM) has proved to be a useful custom power device to eliminate harmonic components and to compensate reactive power for balanced /unbalanced linear/nonlinear loads. This paper presents a novel control strategy to calculate the reference compensation current of three phase DSTATCOM under distorted utility condition at instantaneous state. In this proposed approach digital FIR filters with cut off frequency 25,100 Hz of direct form structure have been implemented on FPGA to make the process faster. The performance of the system simulated in Matlab Platform and evaluated considering the source current total harmonic distortion. The VHDL design has been implemented using ISE10.1 tool from Xilinx. This is tested on a board with hardware configuration such as FPGA -XC2VP4 with on chip PowerPC-405 Processor, ADC AD9240-14 bit 10MSPS analog input channel, DAC AD7541-12-bit of conversion time-100ns with System clock 40 MHz.

Hybrid form FIR filters have been shown to provide a trade-off between the direct form and transposed direct form FIR filters resulting in a low power implementation. However, the use of multiple constant multiplication (MCM) techniques is less advantageous as it results in several MCM blocks. In this work a method of implementing low-complexity hybrid form FIR filters using matrix multiple constant multiplication blocks is proposed. The utilized filter structure can be seen as a polyphase decomposition with common delay lines for the subfilters.

This paper introduces a new approach based on blind source separation (BSS) to mit igate intentional interference in BFSK d igital co mmun ication systems using frequency hopping spread spectrum technique. The use of BSS is possible thanks to adopting an adequate selection block to distinguish between the useful signal and other undesirable signals, hence, circu mvent the problem of amb iguity of permutation. An analytical calculation of the probability of error to predict the performance is done. The simulat ion results showed the effectiveness of this approach, whatever the level of the JSR and without using the fast frequency hopping alternative or error-correcting codes.

In this paper we present a general approach for the design
of LeGall’s 5/3 linear phase perfect reconstruction filterbank. Using our generalized approach, we can design
the 5/3 filters with the coefficients having different finite
wordlengths (precision) - thus this can be seen as a generalization of the LeGall 5/3 filters. We construct design examples with the filters having different wordlengths, and
also analyze the frequency characteristics of the designed
filters.

In this paper we present a general approach for the design of LeGall's 5/3 linear phase perfect reconstruction filterbank. Using our generalized approach, we can design the 5/3 filters with the coefficients having different finite wordlengths (precision) -thus this can be seen as a generalization of the LeGall 5/3 filters. We construct design examples with the filters having different wordlengths, and also analyze the frequency characteristics of the designed filters.

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.

In Iterative Learning Control, the ideal learning filter is defined as the inverse of the system being learned. Model based learning filters designed from the inverse system transfer function can provide superior performance over single gain, P-type algorithms. These filters, however, can be excessively long if lightly damped zeros are inverted. In this paper, we propose a method for designing model based finite impulse response (FIR) learning filters. Based on the ILC injection point and discrete time system model, these filters are designed using the impulse responses of the inverse transfer function. We compare in simulation the ILC algorithms implemented at two different feedforward injection points and two different modeling methods. We show that the ILC algorithm injected at the reference signal and whose model is generated by discretizing the closed loop continuous time transfer function results in a learning filter with no lightly damped zeros. As a result, the learning filter has only two dominant filter taps much like the PD-type learning filter. We then implement these ILC algorithms on a wafer stage prototype. In this motion control application, we show that the model based ILC algorithm outperforms the P-type system in the plant injection architecture where longer FIR filters are needed for learning stability. We also show that the reference injection architecture provides superior performance to the plant injection for both model based and P-type ILC algorithms.

A low-power, high-performance, compilerfriendly DSP core has been under development in the IBM Communications Research & Development Center, as part of its eLite DSP project. This DSP incorporates instruction-level parallelism through the packing of multiple instructions in 64-bit longinstruction words, while data-level parallelism is realized through the use of SIMD techniques, such that SIMD operations can be applied to both dynamically composed vectors and packed vectors. Dynamic composition of vectors is made possible through the use of a vector pointer mechanism, which permits the addressing in a very flexible way of groups of four 16-bit elements in a large, multiport, scalar register file. This paper provides an overview of the architecture of this DSP core, with a focus on its SIMD features. We describe these features in some detail and discuss how they are used, with a block FIR filter and a radix-4 FFT taken as examples.