Micro Processors

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to run-time errors that are difficult to diagnose, and failure to meet deadlines, which is catastrophic for systems with hard real-time characteristics. Classical software validation methods like simulation and testing with debugging require a lot of effort, are expensive, and do not really help in proving the absence of such errors. AbsInt's tools StackAnalyzer and aiT (timing analyzer) provide a solution to these problems. They use abstract interpretation as a formal method that leads to statements valid for all program runs. Both tools have been used successfully at Hispano-Suiza to analyze applications running on a Motorola PowerPC MPC555. They turned out to be well-suited for analyzing large safety-critical applications developed at Hispano-Suiza. They can be used either during the development phase providing information about stack usage and runtime behavior well in advance of any run of the analyzed application, or during the validation phase for acceptance tests prior to the certification review.

In multiprocessor systems, one of the main factors of systems' performance is task scheduling. The well the task be distributed among the processors the well be the performance. Again finding the optimal solution of scheduling the tasks into the processors is NP-complete, that is, it will take a lot of time to find the optimal solution. Many evolutionary algorithms (e.g. Genetic Algorithm, Simulated annealing) are used to reach the near optimal solution in linear time. In this paper we propose a heuristic for genetic algorithm based task scheduling in multiprocessor systems by choosing the eligible processor on educated guess. From comparison it is found that this new heuristic based GA takes less computation time to reach the suboptimal solution.

Abstract—Optimizing CPU scheduling is crucial for enhancing
the overall performance of operating systems, particularly in environments
that run multiple processes, where responsiveness and
efficient resource utilization are essential. Scheduling algorithms
such as Shortest Job First (SJF) and Shortest Remaining Time
First (SRTF) are theoretically effective in reducing the average
waiting and turnaround times. However, their implementation
in real-world systems is limited due to the need for precise
knowledge of each process’s CPU burst time, which is typically
unavailable during execution. Traditional methods, such as exponential
averaging, often fail to provide accurate or adaptive
predictions for dynamic workloads. This study explores how
Machine Learning (ML) can be applied to accurately predict
CPU burst times, enabling practical use of SJF and SRTF in
real-time systems. This study leverages ML to predict CPU burst
times, using a synthetic dataset mimicking the Grid Workload
Archive (GWA-T-4) to train models including K-Nearest Neighbors
(KNN), Support Vector Machines (SVM), Decision Trees,
Random Forest, XGBoost, and Artificial Neural Networks (ANN).
The ANN and ANN+SVM ensemble achieved superior accuracy
(MAE ˜4.12–4.13 ms, CC ˜0.885), significantly outperforming
the baseline (MAE = 20.67 ms). These predictions enable the
scheduler to make more informed decisions, leading to reduced
context switching, improved resource allocation, and shorter wait
and turnaround times. Moreover, this approach helps alleviate
issues such as process starvation. By embedding ML into CPU
scheduling, the research offers a practical solution to transform
the theoretical benefits of SJF and SRTF into practical, realworld
applications, contributing to the development of intelligent
and adaptive operating systems.

We propose a novel formal method to compute an upper estimation of the WCET that contains the loss of precision and also can be easily parametrized by the hardware architecture. Assuming that there exists an executable timed model of the hardware, we first use symbolic execution [5] to precisely infer the execution time for a given instruction flow. We secondly identify execution states that can be merged with no loss of precision. Depending on the loss of precision we are ready to accept, we finally merge execution paths that have similar execution times.

The buoyancy of the amphibious hybrid vehicle is depending on the parameter of the bottom hull body to keep it afloat every time. Based on the Archimedes principle, the weight of the object float is equal to the volume of water displace. When stimulates on the water surface, there will always resistant that affect the stability of the vehicle. Besides, the stability level of the AHV is very important to ensure the vehicle is on the stable condition and has the ability to face the rollover and pitch effect. Therefore, bottom hull body parameter of the vehicle is not just make it floating, but plays the important role to keep it in the stable state during face the rolling and pitching effect.

In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance lowlevel image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm , which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.

6th International Conference on Advanced Machine Learning (AMLA 2025) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.

Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Computer Science, Engineering and Applications.

Une compréhension approfondie du microprocesseur est indispensable pour les étudiants dans les domaines de l'électricité, de l'électronique, de l'instrumentation et du génie logiciel. A l'issue de ce chapitre, vous serez capable de : structure d'un calculateur, Comprendre Circulation de l'information dans un calculateur, Décrire les différents éléments matériels constituant un microprocesseur, Expliquer le principe de fonctionnement d'un microprocesseur, Expliquer le principe de fonctionnement des mémoires.  Un segment : il représente un bloc de mémoire de taille fixe.  Un offset : il donne la position dans ce segment. Chapitre 2 : La programmation en assembleur À l'issue de ce chapitre, vous serez capable de : Comprendre les concepts de base de la programmation en assembleur. Connaître le jeu d'instructions du processeur et leur utilisation. Appliquer une méthode simple pour écrire des programmes en assembleur pour le microprocesseur 8086. Chapitre 3 : Les interruptions et les interfaces d'entrées/sorties (E/S) A l'issue de ce chapitre, vous serez capable de : Comprendre le rôle des interruptions dans un système à microprocesseur. Savoir comment le 8086 gère les interruptions et comment la table des vecteurs d'interruption est utilisée. Maîtriser les principes de base de l'adressage des ports d'E/S et la communication avec les périphériques. Savoir configurer et utiliser l'interface 8255 pour gérer les ports d'E/S en mode parallèle. Chapitre 4 : Architecture et fonctionnement d'un microcontrôleur A l'issue de ce chapitre, vous serez capable de : Identifier les composants matériels d'un microcontrôleur, Expliquer le rôle des éléments de base d'un microcontrôleur Maîtriser les principes de base de la programmation d'un microcontrôleur, en utilisant les langages assembleur et C. Chapitre 5 : Applications des microprocesseurs et microcontrôleurs A l'issue de ce chapitre, vous serez capable de : Développer des applications basées sur différents microprocesseurs et microcontrôleurs. Programmer des périphériques (LCD, claviers, moteurs) dans des systèmes simulés. Analyser les particularités des codes et des environnements utilisés pour le 8086, Arduino et PIC.

Une compréhension approfondie du microprocesseur est indispensable pour les étudiants dans les domaines de l'électricité, de l'électronique, de l'instrumentation et du génie logiciel. A l'issue de ce chapitre, vous serez capable de : structure d'un calculateur, Comprendre Circulation de l'information dans un calculateur, Décrire les différents éléments matériels constituant un microprocesseur, Expliquer le principe de fonctionnement d'un microprocesseur, Expliquer le principe de fonctionnement des mémoires.  Un segment : il représente un bloc de mémoire de taille fixe.  Un offset : il donne la position dans ce segment. Chapitre 2 : La programmation en assembleur À l'issue de ce chapitre, vous serez capable de : Comprendre les concepts de base de la programmation en assembleur. Connaître le jeu d'instructions du processeur et leur utilisation. Appliquer une méthode simple pour écrire des programmes en assembleur pour le microprocesseur 8086. Chapitre 3 : Les interruptions et les interfaces d'entrées/sorties (E/S) A l'issue de ce chapitre, vous serez capable de : Comprendre le rôle des interruptions dans un système à microprocesseur. Savoir comment le 8086 gère les interruptions et comment la table des vecteurs d'interruption est utilisée. Maîtriser les principes de base de l'adressage des ports d'E/S et la communication avec les périphériques. Savoir configurer et utiliser l'interface 8255 pour gérer les ports d'E/S en mode parallèle. Chapitre 4 : Architecture et fonctionnement d'un microcontrôleur A l'issue de ce chapitre, vous serez capable de : Identifier les composants matériels d'un microcontrôleur, Expliquer le rôle des éléments de base d'un microcontrôleur Maîtriser les principes de base de la programmation d'un microcontrôleur, en utilisant les langages assembleur et C. Chapitre 5 : Applications des microprocesseurs et microcontrôleurs A l'issue de ce chapitre, vous serez capable de : Développer des applications basées sur différents microprocesseurs et microcontrôleurs. Programmer des périphériques (LCD, claviers, moteurs) dans des systèmes simulés. Analyser les particularités des codes et des environnements utilisés pour le 8086, Arduino et PIC.

U radu se analiziraju mikrokontroleri sa posebnim osvrtom na digitalnu elektroniku neophodnu za njihovo funkcionisanje. Mikrokontroleri su elektronski uređaji koji poput računara imaju zadatak da zamene čoveka u upravljanju jednim delom proizvodnog procesa ili skoro celim procesom proizvodnje. Sam termin je izveden iz dve reči, mikro koji predstavlja veličinu uređaja i kontrolera koji označava oblast primene kao što su kontrolne aplikacije. U dizajnu mikrokontrolera postoje dve osnovne arhitekture: Fon Nojmanova arhitektura i Harvardska arhitektura. U nastavku rada opisana su različita kola koja čine današnje mikroračunare. Kombinovana kola koja se sastoje od enkodera, dekodera, multipleksora i demultipleksera. Zatim, sekvencijalna kola koja čine različite memorije i na kraju složena kola koja igraju najveću ulogu u samoj arhitekturi i hardveru mikrokontrolera.

This paper analyzes microcontrollers with special reference to digital electronics necessary for their functioning. Microcontrollers are electronic devices that, like a computer, have the task of replacing a person in the control of one part of the production process or almost the entire production process. The term itself is derived from two words, a micro representing the size of the device, and a controller that denotes an application area such as control applications. In the design of the microcontroller there are two basic architectures: Von Neumann architecture and Harvard architecture. In the continuation of work, various circuits that make up today's microcomputers are described. Combination circuits consisting of encoders, decoders, multiplexers and demultiplexers. Then, sequential circuits that make up different memories and ultimately complex circuits that play the biggest role in the architecture itself and the microcontroller hardware.

Perangkat keras merupakan perangkat yang dapat dilihat dirasah secara langsung oleh manusia. Perangkat keras komputer adalah semua bagian fisik komputer, dibedakan dengan data yang berada didalamnya atau yang beroperasi di dalamnya sedangkan perangkat lunak merupakan perangkat yang dapat dilihat dan tidak dapat disentuh secara langsung oleh manusia, perangkat lunak yang menyediakan instruksi buat perangkat keras untuk menyelesaikan tugasnya.

Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limitations (size, weight, and power). The SIMD Pixel Processor (SIMPil) has been designed at Georgia Tech to address these problems. In SIMPil, an image sensor array (focal plane) is integrated on top of a SIMD computing layer, where processing elements (PEs) are connected in a torus. A prototype processing element has been implemented in 0.8 µm CMOS technology. This paper evaluates the effectiveness of the SIMPil design on a set of important image applications. A target SIMPil system is described, which is capable of operating in the Tops/sec range in Gigascale technology.. Simulation results indicate sustained operation throughput in the range of 100-1000 Gops/sec. These results support the design choices and suggest that more complex, multistage applications can be implemented to execute at real-time frame rates.

Stalks of flax varieties viz., DLV1, Himalini and No55x NL115 were collected from AICRP, MULLARP Scheme, University of Agricultural Sciences, Dharwad for extraction of fibres in water, chemical and enzymatic retting methods. The extracted fibres were assessed for quantity and quality parameters viz., fibre yield, fibre length, microscopic appearance and fibre solubility in different chemicals. The results of the study revealed that, urea retting method yielded higher percentage of fibres, enzyme retted fibres gave longer length of the fibre. The fibre yield was higher in Himalini variety while the fibre length was higher in DLV 1 and No55x NL115 variety. Flax fibres were soluble in 50 per cent sulphuric acid concentrated whereas insoluble in alkalies and solvents.

this paper aims to contribute to the efforts of design community to demonstrate the effectiveness of the state of the art Field Programmable Gate Array (FPGA), in the embedded systems development, taking a case study in the biomedical field. With this design approach, we have developed a System on Chip (SoC) for cardiac monitoring based on the soft processor MicroBlaze and the Xilkernel Real Time Operating System (RTOS), both from Xilinx. The system permits the acquisition and the digitizing of the Electrocardiogram (ECG) analog signal, displaying heart rate on seven segments module and ECG on Video Graphics Adapter (VGA) screen, tracing the heart rate variability (HRV) tachogram, and communication with a Personal Computer (PC) via the serial port. We have used the MIT_BIH Database records to test and evaluate our implementation performance. In terms of the resources utilization, the implementation occupies around 70% of the used FPGA, namely the Xilinx Spartan 6 XC6SLX16. The accuracy of the QRS detection exceeds 96%.

In multiprocessor systems, an efficient scheduling of a parallel program onto the processors that minimizes the entire execution time is vital for achieving a high performance. The problem of multiprocessor scheduling can be stated as finding a schedule for a general task graph to be executed on a multiprocessor system so that the schedule length can be minimize. This scheduling problem is known to be NP-Hard. In multiprocessor scheduling problem, a given program is to be scheduled in a given multiprocessor system such that the program's execution time is minimized. The objective is makespan minimization, i.e. we want the last job to complete as early as possible. The tasks scheduling problem is a key factor for a parallel multiprocessor system to gain better performance. A task can be partitioned into a group of subtasks and represented as a DAG (Directed Acyclic Graph), so the problem can be stated as finding a schedule for a DAG to be executed in a parallel multiprocessor system so that the schedule can e minimized. This helps to reduce processing time and increase processor utilization. Genetic algorithm (GA) is one of the widely used technique for this optimization. But there are some shortcomings which can be reduced by using GA with another optimization technique, such as simulated annealing (SA). This combination of GA and SA is called memetic algorithms. This paper proposes a new algorithm by using this memetic algorithm technique.

Memory-on-logic and sensor-on-logic face-to-face stacking are emerging design approaches that promise a significant increase in the performance of modern systems-on-chip at reasonable costs. In this work, a netlist-to-layout design flow for such heterogeneous 3D systems is proposed. The proposed technique overcomes the severe limitations of existing 3D physical design methodologies. A RISC-V-based multi-core system, implemented in a commercial technology, is used as a case study to evaluate the proposed design flow. The case study is performed for modern/large and small cache sizes to show the superiority of the proposed methodology for a broad set of systems. While previous 3D design flows do not show to optimize performance against 2D baseline designs for processor systems with a significant memory area occupation, the proposed flow shows a performance and power improvement by 20.4-28.2 % and 3.2-3.8 %, respectively.

This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.

We discuss the architecture, implementation and testing of a simplicial Cellular Neural Network (CNN) vector processor core aimed at vision oriented intelligent Internet-of-Things (IoT) devices. The architecture comprises a linear array of 64 processing elements (PE), each connected to a 4 neighbor clique operating on 8-bit input and state data. A 3-bit simplicial parameter, allows multilevel function approximation and extends the functionality over previously reported chips. Input data vectors are stored in two 64 x 64 x 8-bit data caches. The chip is synthesized from a custom designed ultra low voltage CMOS library and fabricated in a 55nm CMOS technology. Dynamic voltage/frequency scaling allows operation at power supplies between 0.5 and 1.2 Volts allowing for a tradeoff between speed and power. The fabricated chip achieves an overall performance of 7.05 TOPS/W at 732fps, with a dynamic energy efficiency of 12.2fJ per operation (OP) at 1.2 Volts.

The buoyancy of the amphibious hybrid vehicle is depending on the parameter of the bottom hull body to keep it afloat every time. Based on the Archimedes principle, the weight of the object float is equal to the volume of water displace. When stimulates on the water surface, there will always resistant that affect the stability of the vehicle. Besides, the stability level of the AHV is very important to ensure the vehicle is on the stable condition and has the ability to face the rollover and pitch effect. Therefore, bottom hull body parameter of the vehicle is not just make it floating, but plays the important role to keep it in the stable state during face the rolling and pitching effect.

Alfa fibres, which are generally extracted from the leaf of a plant belonging to the Poaceae family (Stipa tenacissima L), originating from the center of Tunisia, are mainly used for pulp and paper applications. Their potential use as reinforcement in polymer composites requires the understanding of their microstructure and mechanical properties and a proper control of fibre extraction and transformation processes. This work investigates the morphology of the alfa plant (leaves and fibres) through optical and electron microscopy. The extraction process combining mechanical, chemical and enzymatic stages and the reaction time of the enzymes have been optimised to achieve the highest mechanical properties of fibres. The effect of enzymatic treatments (laccase, pectinases and xylanases) on the morphological, chemical composition and mechanical properties of alfa fibres was investigated and the effectiveness of enzymatic treatments has been evaluated. The chemical compositions of alfa are correlated with its mechanical properties. The result indicates that the tensile properties of isolated fibres were greatly improved when an optimised enzymatic-based process is used to separate the fibres from the leaves. Using pectinase and xylanase activities, results show really high mechanical properties, with an average rigidity and strength up to respectively 66 GPa and 1300 MPa, which make alfa fibre promising reinforcements for load-bearing composite materials. This work also showed that enzymes offer an attractive and ecofriendly approach to efficiently extract high-performance plant fibres.

Computer-assisted vision plays an important role in our society, in various fields such as personal and goods safety, industrial production, telecommunications, robotics, etc. However, technical developments are still rare and slowed down by various factors linked to sensor cost, lack of system flexibility, difficulty of rapidly developing complex and robust applications, and lack of interaction among these systems themselves, or with their environment. This paper describes our proposal for a smart camera with real-time video processing capabilities. A CMOS sensor, processor and, reconfigurable unit associated in the same chip will allow scalability, flexibility, and high performance.

Studi ini mengulas konsep-konsep fundamental dalam arsitektur dan organisasi komputer, dengan fokus pada mode pengalamatan dan teknik pengalamatan. Tiga skenario instruksi pengalamatan - menggunakan 3, 2, dan 1 instruksi pengalamatan - dijelaskan secara rinci, memberikan wawasan tentang kompleksitas dan efisiensi dalam eksekusi perintah komputer.

Dalam kasus mode pengalamatan dengan 3 instruksi, penambahan, pengurangan, dan perkalian diimplementasikan dengan memanfaatkan kombinasi register dan memori. Kasus dengan 2 instruksi pengalamatan mengeksplorasi pemakaian operand langsung dari memori, sementara studi kasus 1 instruksi pengalamatan menyoroti kemungkinan eksekusi perintah dengan overhead yang lebih rendah.

Penerapan mode pengalamatan register dan memory menyoroti teknik pengalamatan seperti Immediate, Direct, Indirect, dan Displacement. Contoh instruksi menggunakan mode pengalamatan ini memberikan pemahaman mendalam tentang bagaimana komputer dapat mengakses dan memanipulasi data.

Dengan merinci contoh penggunaan Immediate Addressing, Direct Addressing, Indirect Addressing, dan Displacement Addressing, studi ini menyediakan landasan untuk memahami bagaimana arsitektur komputer mendukung berbagai operasi dalam lingkungan pemrograman. Pemahaman ini penting untuk pengembangan dan pemahaman lebih lanjut dalam dunia komputasi dan pemrograman.

The study investigated the strength characteristics of two foreign (Cuba 180, Talinum 2) and three locally available varieties of kenaf fibres (Ifeken DI 400, Ifeken 100 and Ifeken 400), with a view to providing insight to optimum conditions for the processing of the fibre into some products. It was observed that Talinum variety recorded the highest values for tensile strength and resistance to load deformation of 62.45×10-1 MPa and 6.3 N respectively while Ifeken 100 was observed to have given the lowest (23.62×10-1 and 2.4 N) values. Ifeken DI 400 exhibited the highest modulus of elasticity of 66.28×10 7 while Ifeken 400 was observed to have the least modulus of elasticity of 17.42×10 7. Cuba 108 was observed to have the highest yield point with the value of 79.81×10-1 mm while Ifeken DI 400 had the least fibre extension with the value of 96.67×10-2 mm. Talinum 2 was also found to have absorbed the highest energy (0.029 J) before rupture with Ifeken 100 variety having the lowest value (0.099 J) for all the kenaf varieties compared. Analysis of variance revealed that the effect of kenaf variety on the fibre strength as well as performance was statistically significant (P ≤ 0.05). The results of the study will be useful in guiding the utilisation of the materials as well serve as a precursor to the design of appropriate machines for further processing of the fibres to preserve the quality of the products.

Model based implementation of a novel nonlinear adaptive filter for extraction of time varying sinusoids using Xilinx system generator has been presented in this work. The practicality of this filter model along with its performance makes it one of the foremost candidates to be applied on nonlinear systems for the purpose of estimation and extraction using reconfigurable hardware like FPGA. A design implementation and verification approach has been discussed for more efficient implementation. Timing and power analysis has been performed and the architecture has been optimized for speed and power to perform at higher frequency when integrated on a Xilinx FPGA. The proposed hardware oriented architecture has been successfully implemented and simulated. The simulation results to track a noisy input have also been shown to demonstrate the exceptional performance of the hardware based architecture developed.

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-m fully digital CMOS technology, contains 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS mm 2 and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions-applications using exposures of about 50 s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device. Index Terms-Focal plane array processors, mixed-signal SIMD vision chips, visual microprocessors. I. INTRODUCTION V ISION is a computation-demanding activity which involves many tasks and data types. These tasks are clustered hierarchically from bottom to top as Fig. 1 illustrates: starting with low-level image processing, (basically 2-D spatial filtering), passing through the estimation of features (segmentation of textures, motion, etc.), and ending with the analysis of images and objects (image classification, identification, 3-D reconstruction, etc.). Low-level tasks consist of simple operations executed on a very large data set; actually the whole set of pixel values. These low-level tasks do not require great accuracy; six to seven equivalent bits are sufficient [1]-[3]. However,

Upcoming groundbreaking applications for always-on tiny interconnected devices steadily demand twofold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 W/MHz. The operating frequency of the core reaches 850MHz at 1.2V.

The WCET computation is one of the main challenges in hard real-time systems, since all further analysis is based on this value. The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET. In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache. We prove that an exact computation does not need to analyze the full exponential number of possible execution paths, but only a bounded subset of them. In the benchmark codes we have studied, the IFC-WCET is up to 62% lower than a bound computed with a widely used approach, and the difference between the number of possible execution paths and the ones relevant for the analysis is extremely large.

Model based implementation of a novel nonlinear adaptive filter for extraction of time varying sinusoids using Xilinx system generator has been presented in this work. The practicality of this filter model along with its performance makes it one of the foremost candidates to be applied on nonlinear systems for the purpose of estimation and extraction using reconfigurable hardware like FPGA. A design implementation and verification approach has been discussed for more efficient implementation. Timing and power analysis has been performed and the architecture has been optimized for speed and power to perform at higher frequency when integrated on a Xilinx FPGA. The proposed hardware oriented architecture has been successfully implemented and simulated. The simulation results to track a noisy input have also been shown to demonstrate the exceptional performance of the hardware based architecture developed.

Enzyme retting can be a viable alternative to water retting, which is the currently utilised method for extracting fibres from kenaf. The advantages of enzyme retting are its greater environmental friendliness, shorter retting time, and more controllable fibre quality. The objective of this study was to determine the efficacy of pectinase produced from locally isolated Aspergillus fumigatus R6 in kenaf retting. A. fumigatus R6 pectinase effectively separated the fibres from non-fibre components. Scanning electron micrographs showed that the surface of pectinase-treated kenaf bast fibres appeared to be smoother and finer. The degree of retting increased with incubation time. A retting time of 32 h produced goodquality kenaf bast fibres with high tensile strength (459 MPa). No significant differences were found between the tensile properties of kenaf bast fibres treated with A. fumigatus R6 pectinase-containing culture filtrate and other sources of commercial pectinase enzyme. Hence, it was concluded that A. fumigatus R6 pectinase was capable of retting kenaf effectively.

Computer cluster is made of some computers which have an unitary processor architecture, generally. The processor architecture gives convenient process on mathematic library development. This study is a preliminary for learning an impact of computer cluster which arranged with different architecture. In terms of the case we use intel core i3-4150 with 4 cores and AMD Athlon (tm) 64 X2 Dual Core Proceasor 4800 with 2 cores. This computer circuits use peer to peer network with 1 master node and 1 compute node. Split methode used for doing some test, the method is we change the master node as compute node and vice versa. The test result is AMD has more stability than intel in calculation system with single core. Although it has some weakness in multi core utilization.

Micro-bump and hybrid bonding technologies have enabled 3D ICs and provided remarkable performance gain, but the memory macro partitioning problem also becomes more complicated due to the limited 3D connection density. In this paper, we evaluate and quantify the impacts of various macro partitioning on the performance and temperature in commercial-grade 3D ICs. In addition, we propose a set of partitioning guidelines and a quick constraint-graph-based approach to create floorplans for logic-on-memory 3D ICs. Experimental results show that the optimized macro partitioning can help improve the performance of logic-on-memory 3D ICs by up to 15%, at the cost of 8°C temperature increase. Assuming air cooling, our simulation shows the 3D ICs are thermally sustainable with 97°C maximum temperature.

This research focuses on designing and implementing a
processor with a five-stage pipeline for educational purposes. The
proposed processor can execute five 16-bit instructions
simultaneously and is designed and simulated using Verilog HDL.
It is implemented on a Cyclone IV FPGA on the DE2i-150 design
board. The processor is suitable for applications that require high
processing speed and low power consumption, including mobile
computers, consumer electronics, security systems, and more. This
RISC-based processor has simple instructions that consume low
power and execute quickly.

In this paper, we present three commercial-grade 3D IC designs based on state-of-the-art design technologies, specifically micro-bumping (3D die stacking), hybrid bonding (wafer-on-wafer bonding) and monolithic 3D IC (M3D). To highlight trade-offs present in these three designs, we perform analyses on power, performance, and area and the clock tree. We also model the tier-to-tier interconnection in each 3D IC methodology and analyze signal integrity to assess the reliability of each design. From our experiments, hybrid bonding design shows the best timing improvement of 81.4% when compared to its 2D counterpart, while micro-bumping shows the best reliability among 3D IC designs.

Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work.. The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.

The WCET computation is one of the main challenges in hard real-time systems, since all further analysis is based on this value. The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET. In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache. We prove that an exact computation does not need to analyze the full exponential number of possible execution paths, but only a bounded subset of them. In the benchmark codes we have studied, the IFC-WCET is up to 62% lower than a bound computed with a widely used approach, and the difference between the number of possible execution paths and the ones relevant for the analysis is extremely large.

The importance of heat sinks in electronic devices will be analyzed in this project, the different types, and the factors that affect the performance of a heat sink, like the geometry, size and number of fins, the speed of the flux, the material the heat sink is made of, the diameter and positions of the channels. To understand the difference between a het sink with a fan and one with microchannels a comparision is made in this project.

We describe the design and analysis of 3D-MAPS, a 64core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μ-diameter, 6 μ-height through-silicon vias (TSVs) and μ-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.