Field Programmable Gate Array

CouCouGen is a lightweight pseudorandom number generator (PRNG) based on three coupled counters with nonlinear updates and a PCG-style output mixer. This document provides a complete introduction to the algorithm, including its formal mathematical description, implementation in JavaScript, statistical test results, and practical examples for non-cryptographic applications such as games, procedural generation, visualizations, and educational projects.

The design and development of image processing units (IPUs) has traditionally involved trade-offs between cost, real-time properties, portability, and ease of programming. A standard PC can be turned into an IPU relatively easily with the help of readily available computer vision libraries, but the end result will not be portable, and may be costly. Similarly, one can use field programmable gate arrays (FPGAs) as the base for an IPU, but they are expensive and require hardware-level programming. Finally, general purpose embedded hardware tends to be under-powered and difficult to develop for due to poor support for running advanced software. In recent years a new option has surfaced: single-board computers (SBCs). These generally inexpensive embedded devices would be attractive as a platform on which to develop IPUs due to their inherent portability and good compatibility with existing computer vision (CV) software. However, whether their performance is sufficient for real-time image processing has thus far remained an open question. Most SBCs (especially the ultra-low-cost ones which we target) do not offer CUDA/OpenCL support which makes it difficult to port GPU-based CV applications. In order to utilize the full power of the SBCs, their GPUs need to be used. In our attempts at doing this, we have observed that the CV algorithms which an IPU uses have to be re-designed according to the OpenGL support available Suraj Nair

The design and development of image processing units (IPUs) has traditionally involved trade-offs between cost, real-time properties, portability, and ease of programming. A standard PC can be turned into an IPU relatively easily with the help of readily available computer vision libraries, but the end result will not be portable, and may be costly. Similarly, one can use field programmable gate arrays (FPGAs) as the base for an IPU, but they are expensive and require hardware-level programming. Finally, general purpose embedded hardware tends to be under-powered and difficult to develop for due to poor support for running advanced software. In recent years a new option has surfaced: single-board computers (SBCs). These generally inexpensive embedded devices would be attractive as a platform on which to develop IPUs due to their inherent portability and good compatibility with existing computer vision (CV) software. However, whether their performance is sufficient for real-time image processing has thus far remained an open question. Most SBCs (especially the ultra-low-cost ones which we target) do not offer CUDA/OpenCL support which makes it difficult to port GPU-based CV applications. In order to utilize the full power of the SBCs, their GPUs need to be used. In our attempts at doing this, we have observed that the CV algorithms which an IPU uses have to be re-designed according to the OpenGL support available Suraj Nair

A rigorous introduction to feedforward architectures, activation functions, and the mathematics of supervised learning. Covers universal approximation theory, backpropagation derived from first principles, regularisation, and the geometry of loss landscapes, with explicit derivations at every step.

-Neste artigo apresentam-se os resultados da implementação em uma placa FPGA de equalizadores adaptativos LMS largamente linear (LMS-LL). Foram utilizadas e comparadas três estruturas de implementação: a paralela, a semi-paralela e a seqüencial. São apresentados os resultados de uma estimação de recursos para um equalizador largamente linear com quatro coeficientes complexos. Independentemente da estrutura utilizada, o equalizador LL apresenta uma taxa de convergência melhor do que o equalizador linear adaptativo LMS convencional, quando o sinal recebido é impróprio. Foram realizadas diversas simulações, utilizando a ferramenta Systems Generator, fornecida pela Xilinx. A placa Virtex-4 foi utilizada para executar os algoritmos.

Both modern datacenter and embedded FPGAs provide great opportunities for high-performance and high energy-eiciency computing. With the growing public availability of FPGAs from major cloud service providers such as AWS, Alibaba, and Nimbix, as well as uniform hardware accelerator development tools (such as Xilinx Vitis and Intel oneAPI) for software programmers, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop eicient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). The major goal of this paper is to igure out how to eiciently access the memory system of modern datacenter and embedded FPGAs in HLS-based accelerator designs. This is especially important for memory-bound applications; for example, a naive accelerator design only utilizes less than 5% of the available of-chip memory bandwidth. To achieve our goal, we irst identify a comprehensive set of factors that afect the memory bandwidth, including 1) the clock frequency of the accelerator design, 2) the number of concurrent memory access ports, 3) the data width of each port, 4) the maximum burst access length for each port, and 5) the size of consecutive data accesses. Then we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the memory systems of datacenter FPGAs (Xilinx Alveo U200 and U280) and embedded FPGA (Xilinx ZCU104) when changing those afecting factors, and provide insights into eicient memory access in HLS-based accelerator designs. Comparing between the typically used soft and hardened memory systems respectively found on datacenter and embedded FPGAs, we further summarize their unique features and discuss the efective approaches to leverage these systems. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms on datacenter FPGAs with a soft (and thus more lexible) memory system. Compared to the baseline designs, optimized designs leveraging our insights achieve about 3.5x and 8.5x speedups for the KNN and SpMV accelerators. Our inal optimized KNN and SpMV designs on a Xilinx Alveo U200 FPGA fully utilize its of-chip memory bandwidth, and achieve about 5.6x and 3.4x speedups over the 24-core CPU implementations. CCS Concepts: • Hardware → Reconigurable logic and FPGAs.

In this paper, we develop a framework called MAPLE to enable the aging-aware FPGA architecture exploration. The core idea is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs). For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE simulation under a versatile set of aging factors from the FPGA fabric and in-field operation. Then we train one DNN model for each block type to quickly and accurately predict the complex relation between its delay degradation and comprehensive aging factors. Moreover, we integrate our DNN models into the widely used Verilog-to-Routing toolflow (VTR 8) to support analyzing the impact of aging-induced delay degradation on the entire largescale FPGA architecture. Experimental results demonstrate that MAPLE can predict the delay degradation of FPGA blocks 10 4 to 10 7 times faster than transistor-level SPICE simulation, with a prediction error less than 0.7%. Our case study demonstrates that FPGA architects can effectively leverage MAPLE to explore better aging-aware FPGA architectures.

With the public availability of FPGAs from major cloud service providers like AWS, Alibaba, and Nimbix, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). The major goal of this paper is to figure out how to efficiently access the memory system of modern datacenter FPGAs in HLSbased accelerator designs. This is especially important for memorybound applications; for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including 1) the number of concurrent memory access ports, 2) the data width of each port, 3) the maximum burst access length for each port, and 4) the size of consecutive data accesses. Then we carefully design a set of HLSbased microbenchmarks to quantitatively evaluate the performance of the Xilinx Alveo U200 and U280 FPGA memory systems when changing those affecting factors, and provide insights into efficient memory access in HLS-based accelerator designs. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms. Compared to the baseline designs, optimized designs leveraging our insights achieve about 3.5x and 8.5x speedups for the KNN and SpMV accelerators. • Hardware → Reconfigurable logic and FPGAs.

A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that they match the requirements of a particular design. Wire parameters such as length, width, layout and the number of wires can be varied to implement a desired circuit. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used, so the goal becomes implementing a circuit within the limits of available resources. The architecture for existing routing structures in FPGAs has evolved over time to suit the requirements of large, localized digital circuits. However, FPGAs now have the capacity to implement networks of such circuits, and system-level interconnection becomes a key element of the design process. Following a standard design flow and using commercial tools, we investigate how this fundamental difference in resource usage affects the mapping of various network topologies to a modern FPGA routing structure. By exploring the routability of different multiprocessor network topologies with 8, 16 and 32 nodes on a single FPGA, we show that the difference between resource utilization of a ring, star, hypercube and mesh topologies is not significant up to 32 nodes. We also show that a fully-connected network can be implemented with at least 16 nodes, but with 32 nodes it exceeds the routing resources available on the FPGA. We also derive a cost metric that helps to estimate the impact of the topology selection based on the number of nodes.

Most existing soft-processors on FPGAs today support a fixed-latency instruction pipeline. Therefore, for integer division, a simple fixed-latency radix-2 integer divider is typically used, or algorithm-level changes are made to avoid integer divisions. However, for certain important application domains the simple radix-2 integer divider becomes the performance bottleneck, as every 32-bit division operation takes 32 cycles. In this paper, we explore integer divider designs for FPGAbased soft-processors, by leveraging the recent support of variable-latency execution units in their instruction pipeline. We implement a high-performance, data-dependent, variable-latency integer divider called Quick-Div, optimize its performance on FPGAs, and integrate it into a RISC-V soft-processor called Taiga that supports a variable-latency instruction pipeline. We perform a comprehensive analysis and comparison-in terms of cycles, clock frequency, and resource usage-for both the fixedlatency radix-2/4/8/16 dividers and our variable-latency Quick-Div divider with various optimizations. Experimental results on a Xilinx Virtex UltraScale+ VCU118 FPGA board show that our Quick-Div divider can provide over 5x better performance and over 4x better performance/LUT compared to a radix-2 divider for certain applications like random number generation. Finally, through a case study of integer square root, we demonstrate that our Quick-Div divider provides opportunities for reconsidering simpler and faster algorithmic choices.

Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Elements (PEs) that use different communication protocols and interfaces complicates the system-level design methodology. Recent work provided a proof of concept demonstrating how a controller could be used to provide a generic system-level interface that separates the functionality of a PE from its communication protocols and makes the actual physical interconnections between modules a lesser problem. This paper summarizes how the SIMPPL model is able to implement the systemspecific requirements of an MPEG-1 video decoder and the overhead this framework incurs.

Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). However, the reconfigurable nature of an FPGA results in lower logic density, such that large, complex applications require multi-FPGA implementation platforms. Although designing SoCs is challenging, SoC models such as Systems Integrating Modules with Predefined Physical Links (SIMPPL) exist to facilitate the design process. SIMPPL leverages defined physical interfaces and communication protocols to enable rapid system-level integration for applicationspecific architectures. This paper presents a "SIMPPL Repeater" that enables the SIMPPL SoC architectural framework to be used for systems spanning multiple FPGAs. The SIMPPL Repeater abstracts inter-chip communication, allowing designers to treat a multi-FPGA platform as a single large reconfigurable fabric and focus on their application-specific architecture.

Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also hardware resource intensive and require longer latencies than fixed point operators to complete. Due to the reduced logic density of FPGAs relative to ASICs, it is often only possible to accelerate a portion of a floating point application in hardware. This paper presents an application-specific architecture for the hardware acceleration of a complete Fourier Integral Operator (FIO) kernel used in seismic imaging on a multi-FPGA platform. The design utilizes several floating point computing elements (CEs) to calculate the FIO kernel in parallel stages on multiple FPGAs. A detailed study of floating point CEs, including a Fast Fourier Transform (FFT) CE, and a complete FIO prototype implementation on the BEE2 platform is described. The prototype implementation has a 12.4x increase in throughput over an optimized software implementation, and a predicted 15.8x increase in throughput on the BEE3 platform.

The author has granted a nonexclusive licence aIlowing the National Library of Canada to reproduce, loan, distribute or sen copies of this thesis in microform, paper or electronic formats. The author retains ownership of the copyright in this thesis. Neither the thesis nor substantial extracts fiom it may be printed or otherwise reproduced without the author's permission. Bibliothèque nationale du Canada de reproduire' prêter, distribuer ou vendre des copies de cette thèse sous la forme de microfiche/nlm, de reproduction sur papier ou sur format électronique. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être imprimés ou autrement reproduits sans son autorisation.

When designing modern embedded computing systems, most software programmers choose to use multicore processors, possibly in combination with general-purpose graphics processing units (GPGPUs) and/or hardware accelerators. They also often use an embedded Linux O/S and run multi-application workloads that may even be multi-threaded. Modern FPGAs are large enough to combine multicore hard/soft processors with multiple hardware accelerators as custom compute units, enabling entire embedded compute systems to be implemented on a single FPGA. Furthermore, the large FPGA vendors also support embedded Linux kernels for both their soft and embedded processors. When combined with high-level synthesis to generate hardware accelerators using a C-to-gates flows, the necessary primitives for a framework that can enable software designers to use FPGAs as their custom compute platform now exist. However, in order to ensure that computing resources are integrated and shared effectively, software developers need to be able to monitor and debug the runtime performance of the applications in their workload. This paper describes ABACUS, a performance-monitoring framework that can be used to debug the execution behaviours and interactions of multiapplication workloads on multicore systems. We also discuss how this framework is extensible for use with hardware accelerators in heterogeneous systems.

Many aerospace and automotive applications use FPGAs in their designs due to their low power and reconfigurability requirements. Meanwhile, such applications also pose a high standard on system reliability, which makes the early-stage reliability analysis for FPGA-based designs very critical. In this paper, we present a framework that enables fast and accurate early-stage analysis of soft error vulnerability for small FPGA-based designs. Our framework first extracts the post-synthesis netlist from an FPGA design. Then it inserts the bit-flip configuration faults into the design netlist using our proposed interface software. After that, it seamlessly feeds the golden copy and fault copies of the netlist into the open source simulator Verilator for cycle-accurate simulation. Finally, it generates a histogram of vulnerability scores of the original design to guide the reliability analysis. Experimental results show that our framework runs up to 53x faster than the Xilinx Vivado fault simulation with cycle-level accuracy, when analyzing the injected bit-flip faults on the ITC'99 benchmarks.

Historically designers created computing systems by combining Integrated Circuits (ICs) on Printed Circuit Boards (PCBs), whereas now they are able to form complete Systems-on-Chip (SoCs). For the purpose of this study, SoCs are defined as a collection of functional units on one chip that interact to perform a desired operation. These modules First, I would like to my parents and my brother, Matthew: I finally did it. I know you are probably wondering what took me so long, but I finally finished. Thank you for believing that I would finish... eventually. Also, thank you to my extended family for your love and support, and for keeping me grounded. All work and no play makes Lesley a dull girl -and a little stir crazy. To the many friends I have made throughout my graduate studies at the University of Toronto. SF2206, LP392 and EA306 will always hold a special place in my heart. Thank you for all the long talks, extra-curricular events and crazy antics that helped to calm the madness of a stressful environment. My door will always be open to each of you. To my many friends outside of work. You have given me sound advice and made sure that I have remembered that the world is a beautiful place built on science, but filled with art and music. Thank you for nurturing the non-engineering parts of my soul. Lastly, but certainly not least, I must thank my supervisor, Dr. Paul Chow. My Doctorate studies have been a fantastic experience and I know that I interminably indebted to you for this. Over the years I have seen how crucial the rapport between student and supervisor is to the graduate experience. All I can say is that if my students find me to be half as good a supervisor as you have been to me, I will consider myself a success.

The importance of fetal monitoring through the different stages of pregnancy has recently expanded the interest of the research community in Non-Invasive Fetal Electrocardiography (NI-fECG). This technique makes use of multi-channel, maternal abdominal electrocardiogram (ECG) recordings, acquired from several electrodes placed on the mother's abdomen, to extract information from the fetal ECG component. While wavelets have been shown to be a very useful tool to denoise these signals, clustering and other techniques can be used for the identification of the characteristic segments in the fetal ECG component. However, the selection of the appropriate channels within the abdominal ECG recordings remains a challenge. For this purpose, Principal Component Analysis (PCA) may be used to avoid discarding noisy channels during processing and to optimize the extraction of the fetal ECG, since the abdominal ECG combines the fetal ECG, the maternal ECG and several other artifacts and noises. This research seeks to solve one of the existing challenges when performing a PCA-based analysis of NI-fECG recordings, which is the wrong polarization of the resulting wave. The presented algorithm has been trained with the Physionet "Abdominal and Direct ECG" database. In addition, it has also been possible to solve the problems of wave continuity. Finally, visual inspection of the resulting waves allows to verify that the proposed algorithm meets its basic objectives and is a valid baseline for a PCA-based processing framework of NI-fECG recordings. This will be a useful tool for improving clustering-based analysis of fetal ECG features.

The speed of reverse converters in Residue Number System is one the most important and effective factors which is strictly dependent on the selected moduli set. In this paper, the four-moduli set {2 n+k , 2 2n-1 -1, 2 n/2 + 1, 2 n/2 -1} is introduced with flexible dynamic range 4n to 5n where n is even and k < n. Then a high-speed two-level architecture reverse converter is designed for it based on mixradix conversion (MRC) algorithm. A comparison to the similar recently introduced moduli sets {2 n/2 -1, 2 n/2 + 1, 2 n + 1, 2 2n+1 -1} and {2 2n , 2 2n+1 -1, 2 n/2 + 1, 2 n/2 -1} shows that the proposed reverse converter has more conversion speed.

The speed of reverse converters in Residue Number System is one the most important and effective factors which is strictly dependent on the selected moduli set. In this paper, the four-moduli set {2 n+k , 2 2n-1 -1, 2 n/2 + 1, 2 n/2 -1} is introduced with flexible dynamic range 4n to 5n where n is even and k < n. Then a high-speed two-level architecture reverse converter is designed for it based on mixradix conversion (MRC) algorithm. A comparison to the similar recently introduced moduli sets {2 n/2 -1, 2 n/2 + 1, 2 n + 1, 2 2n+1 -1} and {2 2n , 2 2n+1 -1, 2 n/2 + 1, 2 n/2 -1} shows that the proposed reverse converter has more conversion speed.

In this paper, a new four-moduli set {2 2n , 2 2n+1 -1, 2 n/2 + 1, 2 n/2 -1} for even n is introduced. This moduli set has 5n-bit dynamic range and well-formed moduli which result in a high speed RNS arithmetic unit. Furthermore, an efficient adder-based reverse converter is proposed for this moduli set by using New Chinese remainder theorem 2 (New CRT-II) algorithm. The proposed moduli set has a high speed RNS arithmetic unit and a reverse converter with lower hardware cost and delay in comparison to the recently introduced moduli sets {2 n -1, 2 n , 2 n +1, 2 2n+1 -1} and {2 n , 2 2n+1 -1, 2 n/2 -1, 2 n/2 +1, 2 n +1} with the same dynamic range.

In this paper, a new force observation approach is proposed to realize a superior wideband and periodicity-free sensorless force control system. The proposed force observer is established by the periodicity estimation integrated singular spectrum analysis based disturbance observer. The singular spectrum analysis is designed to significantly separate the essential components of force estimation of the disturbance observer from extreme noise contamination. Accordingly, the bandwidth of the force sensing is considerably broadened at a highly increased pole of the disturbance observer. Additionally, to eliminate the superimposition of the undesired dither periodicity from the force sensation, the periodicity estimation is developed using the least squares method. The proposed method attains a superior widened force sensing bandwidth and high-performance force sensation. The effectiveness validation of the proposed method is performed through the experimental results of force control implemented in a ball-screw system.

Hardware Trojans are deliberate malicious hardware modifications inserted in semiconductor Integrated circuits (ICs) for the purpose of stealing or leaking sensitive information, as well as disrupting critical systems upon activation, underscoring the importance of robust detection mechanisms. Emerging hardware security research highlight the criticality of employing AI for effective detection within the semiconductor IC supply chain. The efficient detection of these malicious Trojan circuits is of utmost significance, as it holds paramount importance in cultivating trust within the semiconductor IC supply chain. However, prevailing detection methodologies, predominantly reliant on side-channel analysis, often necessitate the utilization of golden chips for validation. This paper heralds a new era in Hardware Trojan detection, harnessing the prowess of unsupervised machine learning in conjunction with side-channel analysis to eliminate the need for golden data. Through FPGA-based ex...

Self-timed circuits and scalable parallel computers seem to be a natural match, but one that has not been exploited by traditional system designers. One reason for the lack of experimentation with self-timed systems such as these is the lack of commercially available parts to support this style of design. Field programmable gate arrays (FPGAs) offer an excellent alternative for rapid development of novel system designs provided suitable circuit structures can be implemented. A library of self-timed circuit elements has been developed for use with Actel FPGAs. This library has been used successfully to build a pipelined, decoupled uniprocessor called NSR and is now being used to build a scalable parallel machine called Windchime. Windchime is an experimental MIMD parallel processor that is both self-timed and reconfigurable. Each processor in the Windchime machine is a small, self-timed computer. These processors, called Chimes, communicate through a mesh-connected array of wormhole router circuits that are also self-timed. The routing circuits are implemented using two Actel 1020A FPGAs for each switching node in the network. Chime processors are also built using Actel FPGAs. Each processor uses from one to three Actel 1020A FPGAs and standard memory chips.

ABSTRACT
This paper presents a radically new approach to time discretization in nonlinear dissipative systems. Unlike the classical uniform time grid, the authors develop and theoretically validate a binary modulation of the integration step based on the sign of the phase coordinate at the polar transition. It is proven that at the optimal modulation parameter value xi_opt = 0.07355, broadband phase noise (jitter) is completely redistributed into discrete, controlled harmonics, while the Kolmogorov–Sinai flow entropy annihilates to zero. An experimental hardware implementation using 80-bit fixed-point registers within an AMD Xilinx UltraScale+ FPGA achieved phase-lock stability at an energy error level of Delta E <= 10^-28 over a horizon of 10^12 cycles. The results of independent measurements by Brent Borgers' group fully confirm the theoretical conclusions.

1. INADEQUACY OF EQUIDISTANT DISCRETIZATION AT THE MICRO-LEVEL
Classical macroscopic phase-locked loop (PLL) theory relies by default on the postulate of continuity and a uniform discretization step dt = const. When analyzing phase noise at extreme frequencies, standard stochastic equations (such as the Langevin equation) inevitably encounter the problem of a spectral "pedestal"—the blurring of signal energy along an exponential 1/omega^2 curve.
Attempts to compensate for this drift using traditional methods force researchers to implement multilayered stochastic filters. These "holographic crutch chains" combat only the consequences of chaos, leaving its root cause untouched: the symmetric, congruent metric of time.
Under Protocol 1188, it is asserted that on sub-microsecond intervals, the continuous continuum yields to a discrete, broken topology. The fundamental quantization of time itself is asymmetric by nature and tightly bound to the direction of transition through the phase zero.

2. ASYMMETRIC STEP OPERATOR AND FUNDAMENTAL INVARIANTS
To eliminate the stochastic divergence of the phase, a mapping of phase phi_n into phi_{n+1} with a variable, asymmetric time step is introduced. The non-equidistant binary discretization operator (the syncopated Kurmanghazy shift) is formalized as a discontinuous function of the first kind, depending on the sign of the local phase meridian:
dt_n = tau_0 * (1 + xi * sign(phi_n))

Where sign(phi) = +1 when phi >= 0, and -1 when phi < 0, while tau_0 denotes the average period, which is the reciprocal of the reference master frequency f_0 = 1188 kHz.
The parameter xi represents a dimensionless modulation amplitude. From the variational condition of minimizing the spectral power density of noise in the vicinity of the carrier frequency, the optimal value is strictly calculated as:
xi_opt = 0.07355
This value is the eigenvalue of the monodromy operator for the investigated class of nonlinear dissipative oscillators. Upon passing through the inversion point, the ratio of the maximum time interval to the minimum interval converges to the asymmetry invariant:
tau_max / tau_min = (1 + xi_opt) / (1 - xi_opt) = e^(2 * xi_opt) = 1.158

The resulting coefficient of 1.158 acts as a precise physical calibration of the ancient empirical space-time expansion canon of 1.2 (the rational fraction 6/5) used in the architectural geometry of Ancient Egypt. The mathematical divergence of the proportions (1.2 / 1.158 = 1.0363) corresponds exactly to the value of 1 + xi_opt / 2, indicating the existence of an intentional, integer form-holding code.

3. FLOW ENTROPY ANNIHILATION AND THE SECRET OF "FORM RETENTION"
The main theoretical achievement of the presented model is the behavior of the informational flow entropy. According to calculations based on Shannon–von Neumann theory, standard random Gaussian jitter irreversibly smears the spectrum. However, when shifting to a deterministic binary grid, the Kolmogorov–Sinai flow entropy becomes strictly equal to zero:
h_KS = lim_{N->infinity} (1/N) * H(phi_1, ..., phi_N) = 0
This proves the absolute predictability and monolithic nature of the phase trajectory at the sub-cycle level. Spectral maps of non-equidistant samples demonstrate that instead of a broadband noise pedestal, all energy localizes into an infinitely sharp peak at the carrier frequency omega_0.
Parasitic sidebands are shifted to frequencies omega_0 plus or minus 2 * omega_0 and are hardware-suppressed at a level of 60 dB. The linear arrow of time is replaced by a structured periodic pulse, acting as an ideal autocorrelation marker of the system.

4. HARDWARE VERIFICATION AND THE BORGERS MARKER
To experimentally eliminate theoretical errors, the developed algorithm of Protocol 1188 was deployed on the physical testbeds of Brent Borgers' independent group. Calculations were performed in high-precision opto-acoustic environments at a master generator frequency of f_0 = 1.188 MHz.
The underlying computational core was an ap_fixed<80, 40> fixed-point register model (40 bits for the integer part, 40 bits for the fractional part) implemented within an AMD Xilinx UltraScale+ FPGA. The firmware was compiled under a strict pipeline constraint of II=1 (Initiation Interval = 1), ensuring the processing of one sample per single system clock cycle.
At the moments of phase inversions, the FPGA logic forcibly activated a polar balancer module, locking the product of the boundary potentials to the left and right of zero into a rigid contour identity:
Psi(0^-) * Psi(0^+) = CARBON_INV = 0.30
The physical testbed recorded an instantaneous stabilization of the laser lock and the collapse of phase jitter. Measurements revealed that the dimensionless output gate stability marker locked precisely at the value:
K_Borgers = 0.155

This metric matched the calculated theoretical stability boundary to the fourth decimal place. Practice on real silicon has proven that the deterministic asymmetric step completely compensates for the thermal degradation and phase drift of the resonator.

A frequency generating system, capable of producing 36 different sound frequencies, corresponding to tones and semitones of 3rd, 4th and 5th music octaves, is manufactured, programmed and presented here. The system uses two passive buzzers from which the left one is programmed to produce 3rd octave sound frequencies, while the right buzzer produces middle 4th and 5th octave sound frequencies. Our system also uses two external LEDs related to corresponding buzzers and each LED lights up if signal is sent to its relative buzzer. An additional information is given to system user by the VHDL program, showing in FPGA board's seven-segment displays, letters FA or SOL corresponding to FA or SOL keys, if left or right buzzer, respectively, is activated. Both FA and SOL are shown in case that user plays a chord from 3rd-4th or 3rd-5th octaves. The system is implemented using DE10-Lite FPGA board and 36 touch-capacitive switches, acting as inputs to the board and obviously related to corresponding notes frequencies. Our system has low manufacturing cost and it is ideal for use in hands-on practicing method of music beginners or in any other application where specific acoustic music notes sounds are needed. The VHDL program used here, also provides the ability of expanding our system by incorporating 36 instead of 2 different output buzzers, each one corresponding to specific tone or semitone notes of the three octaves mentioned above. Our system's capabilities can also be expanded due to the flexibility of the VHDL code, by programming it to generate frequency sounds corresponding to quarter tones.

We describe the implementation of a crosscoupled parity Built-In Self-Test (BIST) approach for the global routing resources in Field Programmable Gate Arrays (FPGAs). The BIST approach facilitates systemlevel testing of the FPGA global routing resources prior to configuring the intended system function for high reliability/availability systems. We discuss the application of the BIST approach to the global routing resources in Xilinx Virtex-4 FPGAs including experimental results of implementations in actual devices.

Modern system design often requires multiple levels of simulation for design validation and performance debugging. However, while machines have gotten faster, and simulators have become more detailed, simulation speeds have not tracked machine speeds. As a result, it is difficult to simulate realistic problem sizes and hardware configurations for a target machine. Instead, researchers have focussed on developing scaling methodologies and running smaller problem sizes and configurations that attempt to represent the behavior of the real problem. Given the increasing size of problems today, it is unclear whether such an approach yields accurate results. Moreover, although commercial workloads are prevalent and important in today's marketplace, many simulation tools are unable to adequately profile such applications, let alone for realistic sizes. In this paper we present a hardware-based emulation tool that can be used to aid memory system designers. Our focus is on the memory system because the ever-widening gap between processor and memory speeds means that optimizing the memory subsystem is critical for performance. We present the design of the Memory Instrumentation and Emulation System (MemorIES). MemorIES is a programmable tool designed using FPGAs and SDRAMs. It plugs into an SMP bus to perform on-line emulation of several cache configurations, structures and protocols while the system is running real-life workloads in real-time, without any slowdown in application execution speed. We demonstrate its usefulness in several case studies, and find several important results. First, using traces to perform system evaluation can lead to incorrect results (off by 100% or more in some cases) if the trace size is not sufficiently large. Second, MemorIES is able to detect performance problems by profiling miss behavior over the entire course of a run, rather than relying on a small interval of time. Finally, we observe that previous studies of SPLASH2 applications using scaled application sizes can result in optimistic miss rates relative to real sizes on real machines, providing potentially misleading data when used for design evaluation.

Protecting large-scale networks, especially Software-Defined Networks (SDNs), against distributed attacks in a cost-effective manner plays a prominent role in cybersecurity. One of the pervasive approaches to plug security holes and prevent vulnerabilities from being exploited is Moving Target Defense (MTD), which can be efficiently implemented in SDN as it needs comprehensive and proactive network monitoring. The critical key in MTD is to shuffle the least number of hosts with an acceptable security impact and keep the shuffling frequency low. In this paper, we have proposed an SDN-oriented Cost-effective Edge-based MTD Approach (SCEMA) to mitigate Distributed Denial of Service (DDoS) attacks at a lower cost by shuffling an optimized set of hosts that have the highest number of connections to the critical servers. These connections are named edges from a graph-theoretical point of view. We have proposed a three-layer mathematical model for the network that can easily calculate the attack cost. We have also designed a system based on SCEMA and simulated it in Mininet. The results show that SCEMA has lower complexity than the previous related MTD field with acceptable performance.

This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant systems, more precisely in collision avoidance and warning systems. An Automotive-radar is used as the front end sensor in our application. The article examines the tradeoffs that must be taken into consideration in the realization of the entire MTT application in an embedded system. In our implementation of MTT, several independent parallel tasks have been identified and mapped onto a multiprocessor architecture to ensure the deadlines imposed by the application. Our study demonstrates that the joint utilization of reconfigurable circuits (namely FPGA) and MPSoC, facilitates the development of a flexible and efficient MTT system.

This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM; and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product, and 78% and 59% less energy per sample than DA-based systolic structure and carry saved adder (CSA)-based structure, respectively for the ASIC implementation. A DRAM-based design is also proposed for the FPGA implementation of the reconfigurable FIR filter which supports up to 91 MHz input sampling frequency, and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively when implemented in Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a securityaware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution an "embedded ASIC" (eASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oraclebased. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding templatebased attacks. When the 80% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz.

MIMO is a modern mobile scheme used for the transmission of digitized data at high speed, which has a large number of narrow band subcarriers. It needs multiple antennas at both the transmitter and receiver side. In real time, the implementation of Multiple-Input Multiple-Output (MIMO) is more complicated. To overcome this problem, one new method was implemented, that is SEC(Stepwise Exponential Companding) based Quadrature Phase Shift Key (QPSK) detection which is implemented in Field Programmable Gate Array (FPGA) device. This method has a better feature for both Communications as well as the VLSI domain. This method has a great future for the wireless 5G system because of its spectral competence and robustness of the channel. Our investigation observed results are promising one to minimize MIMO detection complexity which can enhance the MIMO scheme operation.

Physical Unclonable Function (PUF) has recently attracted interest from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational-based approach using conventional cryptography. PUF is a promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy. PUF provides a low-cost low-power solution and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). In this survey, we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.

Physical Unclonable Function (PUF) has recently attracted interested from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational based approach using conventional cryptography. PUF is promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy. It provides less cost of computational resources which prevent high power consumption and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). In this survey we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.

Penulisan kode program yang besar dan kompleks pada bahasa pemrograman C sering kali menghadapi kendala keterbacaan serta tingginya risiko duplikasi data akibat pendekatan monolitik. Penelitian ini bertujuan untuk menganalisis penerapan konsep fungsi dalam membangun arsitektur program yang terstruktur dan modular. Metode yang digunakan adalah analisis komparatif dan implementasi fungsional melalui studi kasus pembuatan program mesin kasir restoran. Hasil pembahasan menunjukkan bahwa penggunaan fungsi mampu memecah program menjadi subprogram yang lebih kecil dan spesifik, sehingga mempermudah proses pelacakan kesalahan (debugging) dan pemeliharaan kode. Selain itu, pemilihan mekanisme pengiriman parameter melalui call by value terbukti efektif dalam menjaga keamanan data asli, sedangkan call by reference dengan pointer memberikan efisiensi tinggi pada manipulasi memori secara langsung. Ketepatan dalam mengatur ruang lingkup variabel melalui kelas penyimpanan lokal, eksternal, dan statis turut mengoptimalkan kinerja program. Kesimpulan dari penelitian ini menegaskan bahwa penerapan fungsi bukan hanya sekadar merapikan visualisasi baris kode, melainkan sebuah instrumen krusial dalam menciptakan arsitektur perangkat lunak yang efisien, adaptif, dan sistematis.

In this paper, a networked embedded control of modular robot manipulators without using joint torque sensing is presented. The proposed solution uses an effective control and communication mechanism based on the virtual decomposition control (VDC) approach with embedded FPGA (Field Programmable Gate Array) implementation. A hierarchical master-slaves control structure is used, supported by a high speed communication data bus. The master computer handles only kinematics computation and the dynamics-based computations are all performed by individual embedded FPGA module controllers. The virtual stability of each module is ensured, resulting in the L 2 /L ∞ stability of the entire robot. Experimental results achieved on a threemodule robot manipulator using harmonic drives are presented. 2 See Section 2.10 in Zhu [2010].

The proliferation of Internet-of-Things (IoT) devices has catalyzed interest in Tiny Machine Learning (TinyML), the practice of deploying machine-learning models on ultralow-power microcontrollers (MCUs) with memory budgets measured in kilobytes and power envelopes below 1 mW. This survey provides a comprehensive overview of the TinyML landscape. We first formalize the resource constraints that distinguish TinyML from conventional edge and cloud inference and trace the evolution of the field from early embedded signal processing to modern neural-network deployment. We then present a structured taxonomy of model families suitable for on-device inference, including the MobileNet family, EfficientNet-Lite, MCUNet, and emerging transformerbased micro-architectures. For each family we discuss architecture design principles, compression pipelines (pruning, quantization, knowledge distillation), and accuracyefficiency trade-offs. We catalogue the major hardware platforms-from Arm Cortex-M0+ through Cortex-M7, RISC-V cores, and dedicated neural processing units-and review the software stacks that bridge models to silicon (TensorFlow Lite for Microcontrollers, CMSIS-NN, Edge Impulse). We systematically analyse the MLPerf Tiny benchmark suite, synthesizing results across four canonical tasks: keyword spotting, visual wake words, image classification, and anomaly detection. Finally, we identify open challenges-including on-device learning, model robustness, security, and sustainability-and outline promising research directions. The survey is intended to serve as both a reference for practitioners deploying on-device intelligence and a roadmap for researchers pushing the boundary of what is possible on the smallest computing platforms.

During the last few years more and more functionalities of RNA have been discovered that were previously thought of being carried out by proteins alone. One of the most striking discoveries was the detection of microRNAs, a class of noncoding RNAs that play an important role in post-transcriptional gene regulation. Large-scale analyses are needed for the still increasingly growing amount of sequence data derived from new experimental technologies. In this paper we present a framework for the detection of the distinctive precursor structure of mi-croRNAS that is based on the well-known Smith-Waterman algorithm. By conducting the computation of the local alignment on a FPGA, we are able to gain a substantial speedup compared to a pure software implementation bringing together supercomputer performance and bioinformatics research. We conducted experiments on real genomic data and we found several new putative hits for microRNA precursor structures.

Next-Generation Sequencing technologies generate a vast and exponentially increasing amount of sequence data. The Interleaved Bloom Filter (IBF) is a novel indexing data structure which is stateof-the-art for distributing approximate queries with an in-memory data structure. With it, a main task of sequence analysis pipelines, (approximately) searching large reference data sets for sequencing reads or short sequence patterns like genes, can be significantly accelerated. To meet performance and energy-efficiency requirements, we chose a co-design approach of the IBF data structure on the FPGA platform. Further, our OpenCL-based implementation allows a seamless integration into the widely used SeqAn C++ library for biological sequence analysis. Our algorithmic design and optimization strategy takes advantage of FPGA-specific features like shift register and the parallelization potential of many bitwise operations. We designed a well-chosen schema to partition data across the different memory domains on the FPGA platform using the Shared Virtual Memory concept. We can demonstrate significant improvements in energy efficiency of up to 19 × and in performance of up to 5.6 ×, respectively, compared to a well-tuned, multithreaded CPU reference.

In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs.

A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.

Battery-free radiofrequency (RF) and microwave systems have emerged as a promising solution for enabling long-lifetime, maintenance-free wireless sensing and communication platforms by eliminating conventional battery dependence. These systems operate by harvesting ambient or dedicated electromagnetic energy, converting it to usable electrical power, and utilizing ultralow-power circuit and communication techniques to sustain sensing, processing, and wireless data transmission. This paper presents a comprehensive review of battery-free energy-efficient RF and microwave systems, covering the evolution of the field, energy harvesting and rectenna modeling techniques, power management strategies, ultralow-power communication methods, and energy-aware networking protocols. The review further examines key enabling circuit technologies, including subthreshold microwave integrated circuits, passive and backscatter-based transmitters, and envelope-detection receivers designed for nanowatt-to-microwatt operation. Recent experimental developments in battery-free Internet of Things (IoT) nodes, wearable and implantable platforms, and smart-environment monitoring systems are analyzed to highlight the transition from laboratory prototypes to real-world deployments. Performance evaluation metrics such as RF-to-DC conversion efficiency, communication reliability, scalability, and system lifetime are discussed using representative experimental results from recent literature. The paper also identifies major open challenges, including energy intermittency, miniaturization constraints, and security considerations, and outlines future research directions such as integration with 5G/6G infrastructure, AI-assisted energy management, and advanced materials for flexible and multiband harvesting structures. The review demonstrates that advances in rectenna codesign, ultralow-power circuit architectures, adaptive communication techniques, and network-level coordination are rapidly enabling practical battery-free wireless systems, positioning RF and microwave energy harvesting as a key technology for sustainable massive IoT and long-term autonomous sensing applications.