Computer Arithmetic

Since the 17 th century, factoring Fermat numbers (F_n = 2^(2^n) + 1) has been hindered by algorithmic complexity. This paper provides a structural resolution to the problem through the Arithmetic Index Theory (AIT). By modeling the matrix of these numbers via a topology called Absolute Space, we unveil the internal recursivity governing their multipliers. We demonstrate that primality is merely a transient state of spatial vacuity (F_0 to F_4). Starting at F_5 , the matrix undergoes a symmetry breaking forcing the emergence of a Fractal Jump (Diophantine Clasp) to balance the entangled energy. Ultimately, this paper establishes a deterministic proof by contradiction of infinite non-primality: the hypothesis of a return to a prime state for n ≥ 5 causes a triple collapse of the conservation laws of the Absolute Space. This entropic irreversibility definitively proves that all Fermat numbers beyond the temporal initialization point are strictly composite.

The physical limits being reached in silicon-based computing, new ways have to be found to overcome the predicted end of Moore's law. Many applications can tolerate approximations in their computations at several levels without degrading the quality of their output, or degrading it in an acceptable way. This thesis focuses on approximate arithmetic architectures to seize this opportunity. Firstly, a critical study of state-of-the-art approximate adders and multipliers is presented. Then, a model for fixed-point error propagation leveraging power spectral density is proposed, followed by a model for bitwise-error rate propagation of approximate operators. Approximate operators are then used for the reproduction of voltage over-scaling effects in exact arithmetic operators. Leveraging our open-source framework ApxPerf and its synthesizable template-based C++ libraries apx_fixed for approximate operators, and ct_float for low-power floating-point arithmetic, two consecutive studies...

entornos de verificación de manera tal que sus resultados sean de utilidad para el diseñador. Como caso de estudio se presenta la verificación de un modelo digital de un convertidor de potencia para emulación HIL (Hardware in the Loop). En particular, se hace enfásis en la aceleración obtenida al utilizar las técnicas de HIL en la verificación de diseños analógicos-digitales. Continuando con la línea de aritmética presentada en la primer sección, primero se compara el comportamiento de un modelo que utiliza punto fijo para la representación de variables de estado con otro que utiliza representación en punto flotante. La evaluación se realiza considerando diversos escenarios representativos y reales donde se aplicaría el convertidor. Luego de comprobar la funcionalidad del convertidor utilizando técnicas descriptas en la primer parte de la tesis, se utilizan los resultados recopilados para el análisis de resolución de dos variables de estados en el modelo de convertidor de punto fijo. La motivación principal de este análisis es que partiendo de resoluciones óptimas es posible obtener modelos que minimizan el área ocupada en el diseño final y la máxima velocidad de reloj del circuito. A partir de los resultados obtenidos, el diseñador puede apreciar que el aumento de resolución a partir de cierto umbral sólo incrementa el área utilizada y reduce la frecuencia de reloj sin obtener mejoras significativas en la presición. Para el caso de estudio evaluado, es posible apreciar que existe un pequeño intervalo de resolución crítico de las variables de estado donde los errores se reducen drásticamente a cero, sin reducción de la performance o aumentar el consumo de área. Si bien en este trabajo, los resultados completos de las pruebas se presentan en un apéndice, el enfoque propuesto resume un gran volumen de información en gráficas de rápida interpretación por parte del diseñador.

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.

Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.

In this paper we explore the parallelization of the scientific library from GNU both on shared-memory and distributed-memory architectures. A pair of classical operations, arising in sparse linear algebra and discrete mathematics, allow us to identify the major challenges involved in this task, and to analyze the performance, benefits, and drawbacks of two different possible parallelization approaches.

An improved algorithm for computing the three dimensional structure of a scene from pair of stereo images is given. The spatial relationship between the two images is not known, only the "corresponding" points in the two image are known. This problem of 3D scene reconstruction involves: (1) establishing a one to one correspondence between the image plane stereo pairs cm-responding to the spatial points-'the correspondence problem', and (2) determining the relative orientation of the two image planes and the depth relation of spatial points with respect to the image planes. This paper assumes the fmt problem solved [Usikov et al. 1991] and addresses the second problem. There are several approaches to the problem of relative orientation determination [lhompson 1959, Schut 1960, Longuet-Higgins 1981, Horn 1987]. The problem where the two optical axes are parallel and separated by a baselie through the optical centers is well done. The calculation is straight forward using similarity of triangles. For non-parallel stereo systems, closed form solutions may not exist. We present a technique for determining the ciosed form solution to absolute orientation problem when only the projection points are known. This paper presents a heuristic approach which requires at most six stereoscopic pairs of points for determining the relative orientation and spatial points. It is based on solving a linear system of at most three equations. The new approach is intuitive, non-iterative, and enables a clear understanding of the operations performed and inferences drawn.

The problem of determining the geometry of a scene occurs in photographic surveying and binocular vision where non-visual information is not as accurate as the optical information obtained by the human eyes [Ogle 1964]. Thts problem involves determining the relative orientation of the two image planes and the depth relation of spatial points with respect to the image planes. There are several approaches to this problem. The camera information can be derived analytically from knowledge of the camera geometry, or empirically ~m a small number of stereo pain [Strat 1989]. Thompson [1959] developed a technique using five stereo pairs of pointa to caIculatethe structure of the scene, Thomp30nuses a numerical technique to solve five simr.dtsneousnon-linear equations of third degree. Longuet-Higgins gives an elegant technique which uses eight stereoscopic pairs of points. This method requires solving eight simukaneous linear equations. However, it requires calculating the inverse of an 8-by-8 matrix, which can be time consuming and prone to error due to computer arithmetic. This paper presents an efficient, heuristic approach which requires at most six stereoscopic pairs of points and is baaed on solving a linear system of at most three equations. In this paper, the unique solution is determined duectly from the forward coordinates of spatial points instead of applying an iterative procedure [Longuet-Higgins 198 1]. The new approach is intuitive, non-iterative, and enables a clear understanding of the operations performed and inferences drawn.

Enhancing low-light stereo images without supervised data faces significant challenges in effectively recovering brightness while preserving consistency between views. To tackle this, we propose Stereo-IDCE, the first unsupervised low-light stereo enhancement framework built upon interactive dual-curve estimation. Our approach simultaneously estimates pixel-wise curve parameter maps for both views and enforces photometric consistency through coupled feature interaction and specialized loss constraints. Specifically, we introduce a weight-shared IDCE-Net to extract illumination-aware features from both views, along with a cross-view feature interaction module that leverages structural and brightness cues from the opposite view to enable collaborative curve estimation. This design ensures that enhancement operations are coordinated across views rather than learned independently. For loss constraints, we design a joint curve estimation loss CDE-Loss to minimize discrepancies between the left and right curve parameter maps, and a cross-view exposure control loss to align the average brightness of corresponding local regions. These losses explicitly preserve photometric consistency without requiring ground-truth. Extensive experiments on synthetic and in-the-wild datasets demonstrate that our method outperforms existing baselines in enhancing low-light stereo images.

Floating Point Unit is one of the integral unit in the Advanced Processors. The arithmetic operations on floating point unit are quite complicated. They are represented in IEEE 754 format in either 32-bit format (single precision) or 64-bit format (double precision). They are extensively used in high end processors for various applications such as mathematical analysis and formulation, signal processing etc. This paper describes the detailed process for the computation of addition, subtraction and multiplication operations on floating point numbers. It has been designed using VHDL. The design has been simulated and synthesized to identify the area occupied and its performance in terms of delay.

Two’s complement overflow detection is traditionally performed by evaluating the carry into and out of the sign bit after full binary addition, or equivalently by comparing operand and result signs. While exact and efficient in hardware, such methods require complete carry evaluation and are less amenable to bounded or early-termination analysis in software and formal reasoning contexts. This paper presents a conservative upper-bound test for detecting potential overflow in two’s complement binary addition based on vector carry analysis. Binary operands are partitioned into ordered vectors of adjacent bits, preserving bit significance, and carry behavior is analyzed through explicit bitwise propagate and generate relations. In prioritizing analysis of the most significant vectors, the proposed method can terminate early when overflow is either impossible or unavoidable, without requiring full carry computation. The approach does not replace exact overflow detection; rather, it provides a sound sufficient condition that guarantees no false negatives while allowing false positives. Such makes the method suitable for static analysis, formal verification, and pedagogical exposition of carry propagation behavior. The paper formally derives the vector-based carry equations, proves soundness of the upper-bound test, and demonstrates the method through worked examples covering positive and negative overflow and non-overflow cases.

It is widely acknowledged that efficient modular multiplication is a key to high-performance implementation of public-key cryptography, be it classical RSA, Diffie-Hellman, or (hyper-) elliptic curve algorithms. In the recent decade, practitioners have relied mainly on two popular methods: Montgomery Multiplication and regular long-integer multiplication in combination with Barrett's modular reduction technique. In this paper, we propose a modification to Barrett's algorithm that leads to a significant reduction (25% to 75%) in multiplications and additions.

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Traditional integer division constrains the remainder to be non-negative, an assumption that simplifies arithmetic but introduces asymmetries and inefficiencies. The idea of using centered remainder intervals is classical in number theory and widely used in FFT/NTT implementations. The contribution of REIST in this report is therefore not a new algebraic object, but an implementation-oriented framing and a systematic treatment of the remainder as an explicit signed correction term, together with an empirical evaluation on modern CPUs. This work presents REIST Division (Remainder-Extended Inversion and Subtraction Technique) as a generalized framework that allows bounded negative remainders and interprets the remainder as a signed correction term rather than a passive residue. The formalism yields a centered remainder interval, aligns naturally with balanced modular arithmetic and rounding functions, and provides a convenient language for modeling error-feedback and phase-alignment processes in logistics, scheduling, digital signal processing, robotics and CPU micro-architectural correction loops.

We propose a radix-r digit-recurrence algorithm for complex square-root. The operand is prescaled to allow the selection of square-root digits by rounding of the residual. This leads to a simple hardware implementation. Moreover, the use of digit recurrence approach allows correct rounding of the result. The algorithm, compatible with the complex division, and its design are described at a high-level. We also give rough comparisons of its latency and cost with respect to implementation based on standard floating-point instructions as used in software routines for complex square root.

Dieses Beitrag zeigt, dass sich alle vier grundlegenden arithmetischen Operationen-Addition, Subtraktion, Multiplikation und Division-auf eine einzige primitive Operation zurückführen lassen: die Addition unter expliziter Interpretation des Vorzeichens. Trennt man die Operatorsemantik von der Vorzeichensemantik, wird sichtbar, dass Subtraktion, Multiplikation und Division keine eigenständigen Prozesse sind, sondern abgeleitete Formen iterierter oder negierter Addition. Dadurch werden die traditionellen Vorzeichenregeln, die häufig als isolierte Konventionen vermittelt werden, zu direkten Konsequenzen der strukturellen Logik. Zudem spiegelt dieses Reduktionsprinzip die Architektur digitaler Recheneinheiten wider, deren arithmetischer Kern aus der Addition als elementarer Hardwareoperation besteht. Das resultierende Rahmenwerk bietet konzeptionelle Klarheit, didaktische Vorteile und eine strukturelle Kohärenz zwischen mathematischer Theorie und rechnerischer Implementierung.

Most implementations of the modular exponentiation, M E mod N , computation in cryptographic algorithms employ Montgomery multiplication, ABR -1 mod N , instead of modular multiplication, AB mod N , even the former requires some transformational overheads. This is so because a state-of-the-art Montgomery multiplication implementation has a performance advantage over direct modular multiplication based on the Barrett algorithm that more than compensates for the overhead. In this paper, we present a direct modular multiplication method that is comparable in speed to Montgomery multiplication. One consequence is that when the exponent in small, direct computation (which does not incur the transformational overhead) using the modular multiplication algorithm presented here results in practical performance gain. For the exponent 17, for instance, which requires five modular multiplication, a saving of up to 40% can be achieved.

The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic was revised , and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper which are used in a software implementation of the IEEE 754R decimal floatingpoint arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms for the more important or interesting operations of addition, multiplication, division, and conversions between binary and decimal floating-point formats are also outlined. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations.

This paper presents a conceptual and formal reduction of the fundamental arithmetic operations to signed addition. It demonstrates that subtraction, multiplication, and division can each be reformulated as additive processes governed by sign logic. This unified treatment not only simplifies arithmetic at its core but also aligns with principles found in digital computation, algebraic structures, and cognitive heuristics. The work highlights how seemingly complex operations emerge naturally from a single primitive — signed addition — and discusses implications for mathematics, computer science, and models of human reasoning.

The objective nature observed in the development of the computer world makes it possible to predict requests for the development of promising computer systems. The parallelism and fuzziness of the natural world encourages the development of pipeline systems for the processing of approximate data. The progressive development of high-risk objects increases the requirements for safety-related systems in improving the checkable and fault-tolerant solutions used in them. A method for developing a checkable fault-tolerant floatingpoint pipeline system is proposed. Matrix circuits of pipeline sections are unified in the form of lines of identical elements. The operands and floating-point results obtain an additional bit excluded from the calculations. Its movement creates many versions of calculation execution, ensuring the checkability of circuits and their fault tolerance in the form of self-recovery when selecting a version that excludes a faulty element. The method uses the synergy of different types of performed functions to simplify the system and to counter faults.

Helpful discussions with Kazushige Goto and John McCalpin are gratefully acknowledged. Thanks to Dan Stanzione for his notes on cloud computing, Ernie Chan for his notes on scheduling of block algorithms, and John McCalpin for his analysis of the top500. Thanks to Elie de Brauwer, Susan Lindsey, and Lorenzo Pesce for proofreading and many comments. Edmond Chow wrote the chapter on Molecular Dynamics. Robert van de Geijn contributed several sections on dense linear algebra. Contents

We introduce and discuss a concept of approximation of a topological algebraic systemAby finite algebraic systems from a given class. IfAis discrete, this concept agrees with the familiar notion of alocal embeddingofAin a classof algebraic systems. One characterization of this concept states thatAis locally embedded iniff it is a subsystem of an ultraproduct of systems from. In this paper we obtain a similar characterization of approximability of a locally compact systemAby systems fromusing the language of nonstandard analysis.In the signature ofAwe introducepositive boundedformulas and theirapproximations;these are similar to those introduced by Henson [14] for Banach space structures (see also [15, 16]). We prove that a positive bounded formula φ holds inAif and only if all precise enough approximations of φ hold in all precise enough approximations ofA.We also prove that a locally compact field cannot be approximated arbitrarily closely by finite (associative) rings (even if the...

Nous proposons un algorithme itératif de racine carrée de base r. L'opérande est préalablement mise à l'échelle afin de permettre une sélection élémentaire des chiffres du résultat. Ceci permet une implantation matérielle simple. De plus, l'algorithme autorise un arrondi correct du résultat. Nous décrivons cet algorithme (compatible avec un algorithme de division complexe que nous avons proposé auparavant) à un haut niveau, et donnons des estimations grossière de son délai et de son coût, afin de le comparer à des algorithmes utilisant des instructions virgule flottante conventionnelles.

This paper presents upper bounds on the number of zeros and ones after the rounding bit for algebraic functions. These functions include reciprocal, division, square root, and inverse square root, which have been considered in previous work. We here propose simpler proofs for the previously given bounds given and generalize to all algebraic functions. We also determine cases for which the bound is achieved for square root. As is mentioned in the previous work, these bounds are useful for determining the precision required in the computation of approximations in order to be able to perform correct rounding.

Arithmetic and Logic Unit (ALU) is a critical component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. Research started in late 1950s on designing efficient adder algorithms and their hardware implementation. Many designs based on serial and parallel structures have been proposed to optimize different parameters from time to time. The first contribution of this thesis is the development of an efficient adder architecture that addresses the problems for higher bit operand lengths like fan-out, wiring complexity, etc. Another important element in an ALU after adder is a multiplier. In multipliers, for reducing partial products and computing final result, multi-operand adders and fast adders are required. A special structure known as counters/compressors are typ...

We present the comprehensive mathematical structure underlying the Crystal Harmonics Computer. Five subsystems-magnet-coil induction, LC resonance, piezoelectric oscillation, grid-logic networks, and ternary encoding-are each formulated with rigorous derivations. We then assemble a coupled system of ordinary differential equations capturing their interplay. This framework provides a foundation for analytical studies, numerical simulations, and experimental validation in emergent computing paradigms.

Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compar...

This article addresses the multiplication of one data sample with multiple constants using addition/subtraction and shift operations, i.e., the multiple constant multiplications (MCM) operation. In the last two decades, many efficient algorithms have been proposed to implement the MCM operation using the fewest number of addition and subtraction operations. However, due to the NP-hardness of the problem, almost all the existing algorithms have been heuristics. The main contribution of this article is the proposal of an exact depth-first search algorithm that, using lower and upper bound values of the search space for the MCM problem instance, finds the minimum solution consuming less computational resources than the previously proposed exact breadth-first search algorithm. We start by describing the exact breadth-first search algorithm that can be applied on real mid-size instances. We also present our recently proposed approximate algorithm that finds solutions close to the minimum and is able to compute better bounds for the MCM problem. The experimental results clearly indicate that the exact depth-first search algorithm can be efficiently applied to large size hard instances that the exact breadth-first search algorithm cannot handle and the heuristics can only find suboptimal solutions.

This paper addresses the multiplication of one data sample with multiple constants using addition/subtraction and shift operations, i.e., the multiple constant multiplications (MCM) problem. The MCM problem finds itself and its variants in many applications, such as digital finite impulse response (FIR) filters, linear signal transforms, and computer arithmetic. Although many efficient algorithms have been proposed to implement the MCM using the fewest number of operations, due to the NP-hardness of the problem, they have been heuristics, i.e., they cannot guarantee the minimum solution. In this work, we propose an exact algorithm based on the breadth-first search that finds the minimum number of operations solution of midsize MCM instances in a reasonable time. The proposed exact algorithm has been tested on a set of instances including FIR filter and randomly generated instances, and compared with the previously proposed efficient heuristics. It is observed from the experimental results that, even though the previously proposed heuristics obtain similar results with the minimum number of operations solutions, there are instances for which the exact algorithm finds better solutions than the prominent heuristics.

This paper addresses the problem of realizing hazard-free singleoutput Boolean functions through a network of customized complex CMOS gates tailored to a given asynchronous controller specification. A customized CMOS gate network can either be a single CMOS gate or a multilevel network of CMOS gates. It is shown that hazard-free requirements for such networks are less restrictive than for simple gate networks. Analysis and efficient synthesis methods to generate such networks under a multiple-input change assumption (MIC) will be presented.

This paper proposed an efficient implementation of digital circuit based on the Euclidean Algorithm with modular arithmetic to find Greatest Common Divisor (GCD) of two Binary Numbers given as input to the circuit. Output of the circuit is the GCD of the given inputs. In this paper subtraction-based narrative defined by Euclid is described, the remainder calculation replaced by repeated subtraction. The selection of the Division Method using subtractor is due to ease of implementation and less complexity in connection with reduced hardware. The circuit is built using basic digital electronic components like Multiplexers & comparator (A<B) as control function and Registers, Full subtractor as Register transfer components. Although the circuit is developed to handle 4-bit of data, it can be easily extended to handle any number of bits just by increasing capacity of basic components (Multiplexer, Registers, Full Subtractor and comparator).

This paper proposed an efficient implementation of digital circuit based on the Euclidean Algorithm with modular arithmetic to find Greatest Common Divisor (GCD) of two Binary Numbers given as input to the circuit. Output of the circuit is the GCD of the given inputs. In this paper subtraction-based narrative defined by Euclid is described, the remainder calculation replaced by repeated subtraction. The selection of the Division Method using subtractor is due to ease of implementation and less complexity in connection with reduced hardware. The circuit is built using basic digital electronic components like Multiplexers & comparator (A<B) as control function and Registers, Full subtractor as Register transfer components. Although the circuit is developed to handle 4-bit of data, it can be easily extended to handle any number of bits just by increasing capacity of basic components (Multiplexer, Registers, Full Subtractor and comparator).

El proyecto que se presenta es una herramienta grafica didáctica utilizando el complemento Guide de Matlab. Para esto hemos dividido la interfaz en dos partes: la primera que será de comparación visual, donde la persona aplica los diferentes operadores morfológicos conocidos (dilatación, erosión, cierre y apertura), a una imagen con su respectivo elemento estructurante, y observara de manera visual el efecto que produce el operador morfológico en la imagen resultante y la parte de aplicación, en la cual podremos obtener la cantidad de objetos que presenta la imagen, con sus respectivas áreas y perímetros de cada forma o estructura que muestre la imagen.

Over the last few years, neural networks have started penetrating safety critical systems to take decisions in robots, rockets, autonomous driving car, etc. A problem is that these critical systems often have limited computing resources. Often, they use the fixed-point arithmetic for its many advantages (rapidity, compatibility with small memory devices.) In this article, a new technique is introduced to tune the formats (precision) of already trained neural networks using fixed-point arithmetic, which can be implemented using integer operations only. The new optimized neural network computes the output with fixed-point numbers without modifying the accuracy up to a threshold fixed by the user. A fixed-point code is synthesized for the new optimized neural network ensuring the respect of the threshold for any input vector belonging the range [xmin, xmax] determined during the analysis. From a technical point of view, we do a preliminary analysis of our floating neural network to determine the worst cases, then we generate a system of linear constraints among integer variables that we can solve by linear programming. The solution of this system is the new fixed-point format of each neuron. The experimental results obtained show the efficiency of our method which can ensure that the new fixed-point neural network has the same behavior as the initial floating-point neural network.