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Phase locked loop (PLL)

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lightbulbAbout this topic
A phase locked loop (PLL) is an electronic control system that synchronizes an output signal's phase with a reference signal's phase. It consists of a phase detector, a low-pass filter, and a voltage-controlled oscillator, enabling frequency synthesis, modulation, and demodulation in communication systems.
lightbulbAbout this topic
A phase locked loop (PLL) is an electronic control system that synchronizes an output signal's phase with a reference signal's phase. It consists of a phase detector, a low-pass filter, and a voltage-controlled oscillator, enabling frequency synthesis, modulation, and demodulation in communication systems.

Key research themes

1. How can all-digital phase-locked loops (ADPLLs) be systematically designed to replicate and improve upon analog PLL performance?

This theme explores design methodologies that adapt the well-established analog PLL theory to all-digital implementations for improved scalability, noise immunity, and process portability. It addresses systematic design procedures, component-level digital architectures (e.g., digital loop filters, digitally controlled oscillators), and the impact of crucial parameters such as time-to-digital converter (TDC) resolution on the PLL stability and bandwidth. The theme is vital because all-digital PLLs promise better performance and integration with modern digital IC technologies, yet lack standardized design approaches that guarantee desired stability and frequency response.

Key finding: This paper proposes a systematic design procedure for type-II second-order all-digital PLLs by drawing an analogy with second-order analog charge-pump PLLs (CPPLLs). It demonstrates that the all-digital PLL inherits frequency... Read more
Key finding: This work develops an ADPLL with a digitally controlled oscillator (DCO) implemented in 45 nm CMOS technology, emphasizing low power consumption and wide frequency resolution. It verifies that control bits generated by a... Read more
Key finding: This paper pioneers modeling PLLs purely in digital simulation environments using Verilog, emphasizing the analog-digital mixed signal nature of PLLs. It provides a method to represent nonlinear behaviors such as cycle slips... Read more

2. What are the key mechanisms affecting stability and dynamic performance in PLL-synchronized grid-tied inverter systems, and how can control strategies mitigate these impacts?

This research theme focuses on the challenges posed by PLLs in power electronics interfacing renewable energy sources to weak or complex grids. It investigates the influence of PLL bandwidth, parameter mismatches between parallel converters, and nonlinear interactions that may reduce system stability margins or introduce oscillations. The theme further evaluates enhanced control techniques, including disturbance compensation and intelligent controllers, to improve transient response, synchronization accuracy, and robustness, which are crucial for grid stability and power quality in renewable-integrated power systems.

Key finding: This paper identifies that PLL controllers introduce additional disturbance components in the inverter control loop, degrading stability in weak grid conditions. By establishing a small-signal PLL model in complex variables,... Read more
Key finding: This study develops a CCM-based state-space model and eigenvalue analysis to reveal how mismatches in PLL parameters (especially PLL bandwidth) and power injection between two parallel grid-connected converters affect overall... Read more
Key finding: This paper presents the design and modeling of a fuzzy logic controller (FLC) as an alternative to conventional PI control in synchronous reference frame PLLs for grid-connected inverters. By integrating the FLC within a 1 MW... Read more

3. How do the specific components and noise sources, such as VCO characteristics and power supply noise, impact PLL jitter, phase noise, and overall loop stability?

This theme delves into the physical and electrical noise contributions to PLL phase noise and timing jitter, emphasizing the characterization of voltage-controlled oscillator (VCO) behavior, supply noise modeling, and noise injection effects on loop dynamics. It includes circuit-level design optimization of VCOs for low phase noise, detailed noise source modeling, and approaches for noise mitigation. Understanding these noise coupling mechanisms is critical for the design of high-performance PLLs used in communication systems and high-frequency synthesis.

Key finding: Though this paper primarily addresses inverter synchronization, it contextualizes PLL performance under noisy grid conditions, highlighting that measurement noise can desynchronize inverter-grid signals, impacting PLL... Read more
Key finding: This paper presents a comprehensive stochastic and statistical model quantifying timing jitter in PLLs caused by power supply noise. It links power supply noise characteristics and on-chip decoupling capacitance to VCO phase... Read more
Key finding: This study investigates low-power design techniques for CMOS ring oscillators used as VCOs in PLLs across various nanometer nodes (180nm to 45nm). It demonstrates that employing the sleepy keeper technique in a 5-stage ring... Read more
Key finding: This work documents the implementation of a type-II wideband PLL in 22nm FD-SOI CMOS with a novel linear differential tuning I/Q VCO achieving an 8 GHz linear tuning range and exceptionally low measured phase noise down to... Read more

All papers in Phase locked loop (PLL)

This article addresses one of the most serious issues in electricity: frequency and voltage anomalies. Actually, because renewable energy production is intermittent, the frequency and voltage of electricity produced are unstable and... more
ABSTRACT This paper presents a radically new approach to time discretization in nonlinear dissipative systems. Unlike the classical uniform time grid, the authors develop and theoretically validate a binary modulation of the integration... more
Background: Traditional quantum mechanics and continuous-media thermodynamics suffer from fundamental indeterminism and structural chaos. This paper addresses these limitations by introducing a novel architectural approach to physical... more
Предлагается новый подход к анализу гравитационных явлений в рамках Σ-парадигмы, основанный на понятии фазовой когерентности фундаментальных осцилляторов. Вводится понятие спектральной томографии гравитации — метода решения обратной... more
1. LEGAL & REGULATORY FRAMEWORK 1.1. Right to Diagnostic Accuracy: Under the Consumer Protection Act, 2019 and the Clinical Establishments Act, 2010, medical facilities in India have the inherent right to maintain diagnostic equipment at... more
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This study presents a novel prototype of an induction heating dryer integrating hysteresis control with phase-shifted pulse width modulation (PWM) for the first time. The system replaces conventional resistance heating, improving energy... more
Integration of renewable energy systems (RESs) to the grid leads to various power quality issues. A proper control approach for the interfaced inverter is required to mitigate the uncertainties caused in the grid due to the RESs... more
With the increased prevalence of power converters in power systems, especially three-phase voltage source converters (VSCs), the stability analysis of power electronics-based power systems has received much attention recently. To this... more
This article addresses one of the most serious issues in electricity: frequency and voltage anomalies. Actually, because renewable energy production is intermittent, the frequency and voltage of electricity produced are unstable and... more
The grid-tied inverter synchronizes with the network on the basis of the instantaneous voltage phase angle. This angle is computed by the so-called synchronization algorithms. During grid disturbances, it is estimated with a certain... more
In this paper, a Johnson up-counter was designed by using the different types of flip flops. Here the D-flip flop was designed using the DML type_A NAND gate, and TSPC D-flip flop using the DML( Dual Mode logic) logic in order to reduce... more
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