C. Cahill

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Fully stacked 3D devices in electron beam recrystallised material

Proceedings. SOS/SOI Technology Workshop, 1988

Summary form only given. The use of a dual-electron-beam recrystallization system to form the SOI... more Summary form only given. The use of a dual-electron-beam recrystallization system to form the SOI material for the fabrication of fully stacked devices is described. One electron beam is rapidly raster scanned across the underside of the wafer to provide uniform, isothermal heating to a background temperature of 950°C. The second electron beam is incident from above and is formed into a line by scanning with a 100-kHz triangle-wave deflection signal. One row of die is recrystallized with each sweep of the beam, and the wafer is mechanically stepped sideways between sweeps to recrystallize complete wafers, with the background heating following to maintain thermal uniformity. The best quality material results when the regrowth from the melt is seeded from the underlying substrate through windows cut in the isolating oxide. The structure of the fully stacked devices fabricated (SMOS) is illustrated. This structure contains p-channel MOS transistors in the bulk silicon and n-channel devices in the SOI layer directly above. An example of a transfer characteristic from a stacked inverter is given, showing that the recrystallization step does not significantly affect the bulk device performance

Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985

The method of extracting MOSI<-ET model parameters using optimization offers signifi cant advanta... more The method of extracting MOSI<-ET model parameters using optimization offers signifi cant advantages over classical methods of extracting model parameters sequentially. Previous work in this field has concentrated on speed of convergence rather than general appli cability. Gradient following methods have been applied to this problem but difficulties arise because of parameter redundancy, singularities in the objective function, and the necessity of providing very good initial estimates of the model parameters. These factors can seriously hinder the application of the technique. This paper describes the application of the simplex direct search optimization method to this problem. This algorithm, in wide use for general optimization problems, needs no de rivative calculation and has proved highly stable for MOS model pa rameter extraction. Its basis is described and an example of its use given.

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Thermal characterization of vertical multichip modules MCM-V

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1995

This paper describes the thermal characterization of a vertical multichip module (MCM-V) technolo... more This paper describes the thermal characterization of a vertical multichip module (MCM-V) technology. The MCM-V technology encloses a stack of IC&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;#x27;s in a three dimensional cube of plastic molding compound, with the inter-chip electrical connections made on the outside faces of the tube. Thermal measurements mere carried out on two different sized modules containing eight specially designed package evaluation test

Analysis of distributed resistance effects in MOS transistors

by Colin Lyden and C. Cahill

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989

This paper presents a method of modeling the distributed source and drain resistance effects in M... more This paper presents a method of modeling the distributed source and drain resistance effects in MOS transistors. Simulations done using this technique are validated by comparisons with purposebuilt test structures. The method is then used to examine a problem which arises with the use of high temperature interconnect in 3-D silicon-on-insulator (3-D S . 0 . I ) technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology and outlines the benefits achievable through further development of the existing interconnect technologies. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices and results are presented which give general guidelines to the extent of the effect.

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