Papers by Michael Trakimas
A 0.8 V asynchronous ADC for energy constrained sensing applications
2008 IEEE Custom Integrated Circuits Conference, 2008
This paper discusses the design of an asynchronous analog-to-digital converter targeted for low-p... more This paper discusses the design of an asynchronous analog-to-digital converter targeted for low-power sensing applications. The asynchronous sampling scheme will save power because it only samples the input signal when it is changing. The idea of using an adaptive resolution to increase the maximum input frequency of the ADC is introduced. A prototype chip has been fabricated in a 0.18 mum CMOS process. Initial measurement results are presented.
Adaptive asynchronous analog to digital conversion for compressed biomedical sensing
2009 IEEE Biomedical Circuits and Systems Conference, 2009
Compressed sensing enables direct analog to digital information conversion of signals at rates mu... more Compressed sensing enables direct analog to digital information conversion of signals at rates much lower than the Nyquist rate. This eliminates the need for computationally intensive, high speed data acquisition and digital signal processing for compression. We illustrate the use of an asynchronous analog to digital converter (ADC) as a low power, low complexity compressed sensing digitizer of biomedical signals
A low-power asynchronous ECG acquisition system in CMOS technology
2010 Annual International Conference of the IEEE Engineering in Medicine and Biology, 2010
An asynchronous electrocardiogram (ECG) acquisition system is presented for wearable ambulatory m... more An asynchronous electrocardiogram (ECG) acquisition system is presented for wearable ambulatory monitoring. The proposed system consists of a low noise front-end amplifier (AFE) with tunable bandwidth, an asynchronous analog-to-digital converter (ADC), and digital signal processing (DSP). Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. This makes the system attractive for compact wearable ECG monitoring applications. The AFE and ADC were fabricated in a 0.18 microm CMOS technology and consume a total of 79 microW. Measured results demonstrating ECG monitoring are presented.
Low Power Asynchronous Data Acquisition Front End for Wireless Body Sensor Area Network
2011 24th Internatioal Conference on VLSI Design, 2011
Wireless body sensor area networks (WBAN) is one of the key technologies to solve the rising heal... more Wireless body sensor area networks (WBAN) is one of the key technologies to solve the rising healthcare costs through early detection, and point-of-care diagnosis and health management. However there is a stringent power requirement on individual sensor nodes in such networks. Consequently traditional signal chain of amplify-digitize-transmit generates large amounts of data that cannot be sustained due to limited energy
Compressed sensing of EEG using a random sampling ADC in 90nm CMOS
2013 IEEE International Conference on Body Sensor Networks, 2013
ABSTRACT Wireless physiological sensors are often limited by energy consumption of the hardware. ... more ABSTRACT Wireless physiological sensors are often limited by energy consumption of the hardware. Power consumption is typically related to the amount of data being transmitted, conventionally the Nyquist rate which is twice the bandwidth of the signal. However, if the signals are sparse in a known basis, compressed sensing facilitates accurate reconstruction of data when sampled below the Nyquist rate. Thus, power consumption at the sensor node could be improved, which would allow long-term use of wireless physiological sensors. We have implemented a random sampling based compressed analog to information converter (AIC) in 90nm CMOS technology. Sufficiently sparse signals were reconstructed using the ℓ1-minimization algorithm. Here we present experimental results that demonstrate reconstruction of non-sparse signals, in this case EEG, by using an ℓ1, 2 regularization algorithm exploiting group sparsity. These results demonstrate the performance achievable by physical compressed sensing AIC systems for brain computer interface applications.
Experimental results on wideband spectrum sensing using random sampling ADC in 90nm CMOS
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
ABSTRACT Applications that require wireless wideband spectrum sensing are often limited by energy... more ABSTRACT Applications that require wireless wideband spectrum sensing are often limited by energy consumption of the sensing hardware. The power consumption is typically directly related to the amount of data transmitted. The emerging theory of compressed sensing provides a framework for reconstructing the sensed spectrum with fewer samples than are produced from Nyquist rate sampling. We have implemented a compressed sensing analog-to-information converter (AIC) in 90nm CMOS technology that allows complete reconstruction of a sparse spectrum consisting of discrete frequency bands. Typically, ℓ1-minimization based algorithms are used to reconstruct the original signal for compressed sensing. However, these algorithms do not perform well as signal sparsity decreases. This limitation can be mitigated by using ℓ1,2 regularization based algorithms that exploit group sparsity. We present experimental results comparing the performance of both types of algorithms for reconstructing discrete frequency bands sampled with this AIC. These results demonstrate the performance achievable by physical AIC systems that utilize compressed sensing theory.
A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core
IEEE Transactions on Circuits and Systems I: Regular Papers, 2000
ABSTRACT This paper presents the design and implementation of an analog-to-information converter ... more ABSTRACT This paper presents the design and implementation of an analog-to-information converter (AIC) capable of Nyquist and compressed sensing modes of operation. The core of the AIC is a 10-bit edge-triggered charge-sharing SAR ADC with a figure of merit (FOM) of 55 fJ/conversion-step and Nyquist-sampling rate of 9.5 Msample/s. The integration of a pseudorandom clock generator enables compressed sensing operation via random sampling and subsequent asynchronous successive approximation conversion by the core ADC. The AIC allows complete reconstruction of a spectrum consisting of sparse single tones or sparse frequency bands using compressed sensing algorithms based on $ell_{{{1}}}$-minimization as well as $ell_{{{1,2}}}$ regularization, which exploits group sparsity. Implemented in 90 nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5 MS/s, an ENOB of 9.3 bits, and consumes 550 $mu$W from a 1.2 V supply. Measurement results of the AIC demonstrate an effective bandwidth of 25 MHz, which is $5times$ greater than Nyquist-sampling rate with an improved effective FOM of 12.2 fJ/conversion-step for signals with sparse frequency support.
An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications
IEEE Transactions on Circuits and Systems I: Regular Papers, 2000
... This causes the ADC to stop tracking the input signal for two cycles after the ampli-tude ...... more ... This causes the ADC to stop tracking the input signal for two cycles after the ampli-tude ... This becomes more of a con-cern in asynchronous designs where the time between when the ... cur-rents were low enough to avoid degrading the output resolution of the ADC when the ...
Analog Integrated Circuits and Signal Processing, 2009
This paper presents the design of a two-stage pseudo-differential operational transconductance am... more This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA) and its application in low-frequency continuous time filters. The OTA was designed in a 0.18 lm, 0.45 V V T CMOS process. An improved bulk-mode commonmode feedback (CMFB) circuit has been designed which does not load the OTA compared to prior art. A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their threshold voltages (V T ) and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 lW of power. Rail-to-rail input is made possible by using the transistor's bulk terminal as the input. For a load of 20 pF the OTA has a measured DC gain of 63 dB and a gain-bandwidth product of 570 kHz. To demonstrate the use of the OTA in practical circuits, three active RC filters were designed: a 10 kHz Butterworth filter, a 10 kHz Bessel filter, and a 2.5 kHz Tschebycheff filter.
2007 IEEE International Symposium on Circuits and Systems, 2007
This paper presents the design of a two-stage pseudodifferential operational transconductance amp... more This paper presents the design of a two-stage pseudodifferential operational transconductance amplifier (OTA). The circuit was designed in a standard 0.18 µm, 0.5 V V T digital CMOS process.
Uploads
Papers by Michael Trakimas