Papers by Cristian Raducan
Comparison of four design environments employed to analyze a switched-capacitor DC-DC converter
This paper compares the performance of four popular design environments for analog and mixed-sign... more This paper compares the performance of four popular design environments for analog and mixed-signal applications - Virtuoso from Cadence Inc., SIMetrix/SIMPLIS, Simulink and CppSim - when used for system level analysis of a standard switched capacitor DC-DC converter. Virtuoso is the most expensive of the four but it has the best user interface and its Spice-level circuit simulators provide very good accuracy. Also, it allows complete top-down design, from system- to circuit-level within the same environment. However, it may not be best suited for first-pass system-level analysis of switching circuits such as DC-DC converters due to its long simulation time and convergence issues. Numerical solvers such as MATLAB - Simulink and CppSim represent functional blocks by input-state-output relationships, thus avoiding the solving of large sets of simultaneous equations. This reduces dramatically the simulation time at the expense of poorer accuracy. SIMetrix/SIMPLIS converts non-linear models to a piecewise linear straight-line model achieving a fast simulation time for switching circuits. For a fair comparison, the same circuit was analyzed under the same conditions by using the four design environments; the trade-offs between cost, accuracy and simulation time are highlighted.
Capacitorless LDO with fast transient response based on a high slew-rate error amplifier
This paper presents a high slew-rate error amplifier (EA) used to implement a capacitorless low-d... more This paper presents a high slew-rate error amplifier (EA) used to implement a capacitorless low-dropout voltage regulator (LDO) with a very fast transient response. The proposed EA improves a recently published OA structure, by employing high-swing input buffers and a local common mode feedback. Thus, the figures-of-merit related to the EA gain-bandwidth and slew-rate are 2.75, respectively 24 times better than for the initial OA. The EA was used to implement a LDO that requires only 1.1uA quiescent current but has an output current capability of 100mA. The high slew-rate of the EA helps this LDO to achieve low overshoot/undershoot (200mV/274mV) in case of a fast (1us) load step of 100mA, while employing only an on-chip load capacitance of 100pF. Compared with similar implementations, the proposed LDO yields same or better transient performance while requiring significantly less quiescent current. Thus its figure of merit results at least three times better than for its counterparts. The line and load regulation are 0.07mV/V, respectively 0.0028mV/mA.
IEEE Access, 2022
This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to l... more This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C L = 0 and under 60 mV for C L = 1 µF, when the load current varies between 1 µA and 100 mA in 1 µs. The LDO requires only 6.2 µA of quiescent current and occupies 0.018 mm 2 of die area.
This paper presents three circuit implementations of a low-dropout voltage regulator (LDO) struct... more This paper presents three circuit implementations of a low-dropout voltage regulator (LDO) structure that supplies a rail-to-rail voltage controlled oscillator (VCO) operating at 2.5GHz. The LDOs comprise only a small decoupling capacitor that can be integrated but they are still able to deal with the large and fast variations of the supply current required by the VCO. For a fair and direct comparison, all three LDO versions use the same pass transistor and are designed to maintain the output voltage ripple at the same level. Two symmetrical OTAs-one optimized for low-power consumption and the other for higher-bandwidth and lower noise-and one folded-cascode OTA optimized for low noise were employed successively to implement the error amplifier within the LDO. The comparison focuses on the effect the LDOs have on the phase noise of the VCO they supply. It was found that the VCO phase noise can be improved by reducing the level of high-frequency noise on the VCO supply line, caused by the LDOs.
Verilog-A Model for a Switched-Capacitor DC-DC Converter
This paper presents the development and validation of a Verilog-A behavioral model for a switched... more This paper presents the development and validation of a Verilog-A behavioral model for a switched capacitor DC-DC converter. For each converter component block, a behavioral model was created and validated, comparing simulation results with the correspondent transistor level implementation. The model was developed to allow the control of the switches ON resistance and dead time between operation phases. Using the behavioral model, the impact on the output voltage ripple amplitude of the switches RON, dead time, capacitors ESR and output track parasitic resistance was evaluated.
Comparative study of two LDOs for supplying a 2.5GHz rail-to-rail VCO
ABSTRACT This paper presents a comparative study of two low dropout voltage regulators (LDO) for ... more ABSTRACT This paper presents a comparative study of two low dropout voltage regulators (LDO) for supplying a 2.5GHz rail-to-rail voltage controlled oscillator (VCO). The effect of the two LDOs noise on the phase noise of the VCO is presented while keeping the supply ripple the same. Both LDO structures are implemented by using the same error amplifier and the same pass transistor, but the classical LDO uses a large off chip decoupling capacitor while the capacitorless LDO employs a current amplifier which forms high bandwidth around the pass transistors to reduce the supply ripple. Post layout simulation results show a -88dBc/Hz and -83dBc/Hz VCO phase noise at 1MHz for the classical and capacitorless LDO. The LDOs and the VCO were designed in 0.18μm CMOS process.
Sensors, Feb 16, 2022
This article is an open access article distributed under the terms and conditions of the Creative... more This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY
IEEE Transactions on Circuits and Systems I-regular Papers, 2022
This paper presents circuit topologies and implementations for SC DC-DC converters with controlle... more This paper presents circuit topologies and implementations for SC DC-DC converters with controlled charging current. It focuses on the power current mirror that regulates the charging current of the flying capacitor and on the switch drivers. The bandwidth and transient response of the power mirror are improved by inserting an auxiliary current mirror in its input signal path. Conventional switch drivers need power supplies with fast response to load transients; the driver presented here is less demanding, as only its core is biased internally, while the output stage is supplied directly by the converter input voltage. The circuit has an additional "Linear Regulator" mode of operation, whereby the power mirror is turned into a pass transistor. This expands the low-end limit of the converter input voltage. These solutions were used to design in a 130nm BCD technology an automotive SC DC-DC converter. Simulations and measurements performed over the entire automotive temperature range (−40C to +150C), for supply voltages between 8V and 28V, demonstrate that the converter meets all requirements: it can operate with output capacitors as small as 1µF; it provides regulated 5V output voltage for load currents up to 200mA, ensuring a low output voltage ripple, of 35mV and 9mV for output capacitors of 1µF and 10µF, respectively; its efficiency peaks at 81.3% for the typical battery voltage level, 12V.
An area-efficient automotive LDO with scalable maximum load current exhibits excellent response to line and load transients
AEU - International Journal of Electronics and Communications, 2022
Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs
IEEE Transactions on Circuits and Systems I-regular Papers, 2022
This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. T... more This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. The proposed circuit addresses three major LDO design challenges: frequency compensation for a wide range of output currents and load capacitors, fast response to load transients and reduced sensitivity to the supply variations. It was used to implement an LDO that provides a 5V output voltage and up to 50mA output current over a wide range of supply voltages – from 5.25V to 40V – and temperatures, −40<sup>o</sup>C to +150<sup>o</sup>C, while burning as little as <inline-formula> <tex-math notation="LaTeX">$30\mu \text{A}$ </tex-math></inline-formula>. The slew-rate booster ensures that the output voltage overshoot and undershoot caused by load jumps of 50mA/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> remain below 4% of the nominal Vout value. Moreover, the LDO meets the E-06 test requirements within the LV124 automotive standard: the output voltage varies within 10% of its nominal value when sinusoidal voltages with amplitudes up to 20V peak-to-peak and frequency varying between 15Hz and 100kHz are injected into the LDO supply line. This feature is achieved while using a capacitor of only <inline-formula> <tex-math notation="LaTeX">$1\mu \text{F}$ </tex-math></inline-formula> at the output, up to 10 times smaller than the decoupling capacitors used by similar LDOs reported previously.
IEEE Access, 2022
This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to l... more This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for CL = 0 and under 60 mV for CL =1 μF, when the load current varies between 1 μA and 100 mA in 1 μs. The LDO requires only 6.2 μA of quiescent current and occupies 0.018 mm 2 of die area.
Sensors (Basel, Switzerland), 2022
This paper proposes a high-precision LDO with low-temperature drift suitable for sensitive time-d... more This paper proposes a high-precision LDO with low-temperature drift suitable for sensitive time-domain temperature sensors. Its topology is based on multiple feedback loops and a novel approach to frequency compensation, that allows the LDO to maintain a large DC gain while handling capacitive loads that vary over a wide range. The key design constraints are derived by using a simplified, yet intuitive and effective, small-signal analysis devised for LDOs with multiple feedback loops. Simulation and measurement results are presented for implementation in a standard 130 nm CMOS process: the LDO outputs a stable 1 V voltage, when the input voltage varies between 1.25 V to 1.5 V, the load current between 0 and 100 mA, and the load capacitor between zero and 400 pF. It exhibits a DC load regulation of 1 µV/mA, a 288 µV output offset with a standard deviation of 9.5 mV. A key feature for the envisaged application is the very low thermal drift of the output offset: only 14.4 mV across the...
This paper presents three circuit implementations of a low-dropout voltage regulator (LDO) struct... more This paper presents three circuit implementations of a low-dropout voltage regulator (LDO) structure that supplies a rail-to-rail voltage controlled oscillator (VCO) operating at 2.5GHz. The LDOs comprise only a small decoupling capacitor that can be integrated but they are still able to deal with the large and fast variations of the supply current required by the VCO. For a fair and direct comparison, all three LDO versions use the same pass transistor and are designed to maintain the output voltage ripple at the same level. Two symmetrical OTAs – one optimized for low-power consumption and the other for higher-bandwidth and lower noise – and one folded-cascode OTA optimized for low noise were employed successively to implement the error amplifier within the LDO. The comparison focuses on the effect the LDOs have on the phase noise of the VCO they supply. It was found that the VCO phase noise can be improved by reducing the level of high-frequency noise on the VCO supply line, caus...
IEEE Access, 2022
This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to l... more This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C L = 0 and under 60 mV for C L = 1 µF, when the load current varies between 1 µA and 100 mA in 1 µs. The LDO requires only 6.2 µA of quiescent current and occupies 0.018 mm 2 of die area.
Precise and robust enable control circuitry for LDO voltage regulators
This paper presents novel circuit solutions for two issues related to the Enable control of low-d... more This paper presents novel circuit solutions for two issues related to the Enable control of low-dropout (LDO) voltage regulators: setting precise voltage thresholds for the ON/OFF states of the LDO and ensuring that in the OFF state the LDO output is not affected by fast variations of the supply voltage. First, an Enable circuit with hysteresis and temperature compensated thresholds is described: the accuracy of its threshold voltages - including their low temperature coefficients - are predicted by analytical analysis and validated by measurements performed on a silicon implementation. Second, a simple yet effective comparator is proposed, able to significantly reduce the effect the supply voltage variations have on the output voltage when the regulator is in OFF state. Simulation results show that, when the supply voltage varies from 0 to 28V in 28μs, the overshoot of the output voltage is reduced from 5.5V to under 200mV, that is by a factor of 35.
Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. T... more This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. The proposed circuit addresses three major LDO design challenges: frequency compensation for a wide range of output currents and load capacitors, fast response to load transients and reduced sensitivity to the supply variations. It was used to implement an LDO that provides a 5V output voltage and up to 50mA output current over a wide range of supply voltages - from 5.25V to 40V - and temperatures, -40°C to +150°C, while burning as little as 30μA. The slew-rate booster ensures that the output voltage overshoot and undershoot caused by load jumps of 50mA/μs remain below 4% of the nominal Vout value. Moreover, the LDO meets the E-06 test requirements within the LV124 automotive standard: the output voltage varies within 10% of its nominal value when sinusoidal voltages with amplitudes up to 20V peak-to-peak and frequency varying between 15Hz and 100kHz are injected into the LDO supply line. This feature is achieved while using a capacitor of only 1μF at the output, up to 10 times smaller than the decoupling capacitors used by similar LDOs reported previously.
Automotive Switched-Capacitor DC-DC Converter With High BW Power Mirror and Dual Supply Driver
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Novel current limit circuitry for LDOs
IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017
This paper presents a novel circuit implementation for overcurrent protection of low-dropout volt... more This paper presents a novel circuit implementation for overcurrent protection of low-dropout voltage regulators, that is able to limit the maximum current the regulator can source into the load to a value set by the user and to keep the current limit value fairly independent of process variation and output voltage, as well as maintaining its temperature drift over the wide temperature range of −50°C to +185°C to below 15%. This is achieved by using an open loop Widlar bandgap structure supplied by an additional current branch, placed in parallel with the power transistor. Design equations are presented in the paper along with electro-thermal simulations that identify the hot spots of the power transistor, thus optimizing the placement of the sense transistor and improving the current sensing accuracy. The proposed circuit is implemented in a standard bipolar junction transistor process. Measurement results — including thermal test scenarios are in good correlation with simulations, ...
A Capacitor-less LDO with High PSR over a wide frequency range
2021 International Semiconductor Conference (CAS)
Verilog-A Model for a Switched-Capacitor DC-DC Converter
2019 International Semiconductor Conference (CAS)
Uploads
Papers by Cristian Raducan