Compact fixed-threshold and two-vector Hamming comparators

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues.

In this paper three different techniques are used for designing a 1-bit comparator and then a comparison is made about area and power consumption. First one is autogenerated comparator, second one is semi-custom comparator and the third one is fully custom design. Today"s technology demands to develop various new design methodologies to reduce the area and power consumption as small saving in area and power of a circuit yield a large overall saving. From the given comparison, we found that full-custom design saves about 50%in area and 35%in power consumption when compared with autogenerated design and saves 37% in area and 98% power saving when compared with semicustom design.

Analog Integrated Circuits and Signal Processing, 1996

Many practical applications require a comparison of the Hamming weights of two N-bit binary vectors. This comparison can be performed in a fully digital manner or by a mix of analog and digital techniques. In this paper, we propose a design in the latter category that exhibits advantages in speed and power dissipation compared with the best previous designs. The proposed design comprises of two switched-capacitor arrays associated with two comparators placed in parallel, collectively providing a complete comparison outcome of ''['', ''\'', or ''=''. The switchedcapacitor array circuit is composed of uniform capacitances, thus associating identical charges with all bits, independent of their positions in the input bit-vectors. Once charge accumulation has occurred based on the asserted inputs, the two comparators release the final decision concurrently. The structure is shown to support wide input vectors on the order of 64 bits, while requiring a small silicon area for capacitor array structures, CMOS switches, and latched comparators to compute and store the comparison outcome. HSPICE simulation shows a total power consumption of 1.136 mW, evaluated at the operating frequency of 1 GHz (based on input-to-decision delay) for 16 bit input vectors under 0.15 lm TSMC technology.

IJMER

In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed. This design needs less area and less number of transistors, also discussed about power and execution time. The circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit comparator has been extended to implement an 8-bit comparator by connecting in series with pass transistor between them. The design has been implemented in Microwind3.1, is tested successfully and has been validated using Pspice for different measurable parameter.

International Journal of Engineering Sciences & Research Technology, 2014

This paper provides an experience of new comparator model gives large range, with faster operation by converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003

The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a tine cost-performance ratio comparator design. Based on modified 1's complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay. Post-layout simulations based on TSMC 0.6um lP3M CMOS process has completed. It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 4.211s. Index Termmagnitude comparator, digital comparator, sorter, 1's complement, conditional sum adder, CMOS, digital IC and VLSI.

—ASIC implementation of a parallel binary comparator based on radix-2 tree structure, utilizing Carry Look Ahead (CLA) technique is proposed in this brief. This novel comparator architecture achieves both low power and high-speed operation, particularly at low-input data activity environments. The proposed comparator is designed using VHDL code and synthesized using ALTERA QUARTUS-II. Experimental evaluation of the proposed and state of-the-art designs revealed that the proposed comparator design exhibits a reduction in delay by 49.8% and gate count by 42.6% for a 16 bit design, compared to the best of the schemes used for comparison.

Analog Integrated Circuits and Signal Processing, 2015

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018

An Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. The approach minimizes the transistor count and benefits from a generalized definition of threshold logic functions. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of rational weights is proposed. Process variations, transistor aging, and circuit parasitics are taken into consideration. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOSbased threshold logic implementation.

2016

The real world signals are mostly analog in nature and hence, an analog to digital converter is needed to transmit effectively the analog signals to digital signals. This paper describes the comparator circuits used in most of the analog circuits now-adays. Comparators play a vital role in most of the analog circuits like Flash ADC’s and the performance of these circuits is greatly influenced by the choice of comparators. In this paper, first a “ Open loop comparator” is designed and its analysis is done followed by a “TIQ comparator”, “Quantized Differential Comparator”, “Two stage CMOS amplifier with an output inverter” and “CMOS-LTE Comparator” and all of these circuits are used for implementing a lot low power analog circuits. After implementing all the comparator circuits, power and delay analysis has been done on the basis of which Power-Delay-Product (PDP) has been calculated. All the above circuits are implemented using 180nm CMOS technology using a supply voltage of 1.8v. T...