Digitally Enhanced Analog Circuits: System Aspects
Boris Murmann Christian Vogel Heinz Koeppl
Stanford University Graz University of Technology EPFL
Department of Electrical Engineering Signal Processing and Speech School of Communication and
Stanford, CA, USA Communication Laboratory Computer Sciences
[email protected] Graz, Austria Lausanne, Switzerland
[email protected] [email protected]
Abstract— An overview of digital enhancement techniques for correction; one that looks at block interplay, and specific
analog circuits is presented. Recent research suggests that the system and signal attributes. Figure 1 shows a general block
high density and low energy of digital circuits can be leveraged diagram of a digitally enhanced electronic system in which
to enable a new generation of interface electronics that is based additional digital resources are allocated either to assist
on minimal precision, low complexity analog blocks. Today, individual blocks or to facilitate the system-wide interaction of
examples of enhancement schemes can be found in diverse previously isolated blocks.
applications and include nonlinearity compensation of ADCs,
predistortion of power amplifiers and mismatch calibration in Digital Enhancement
radio receivers. Since it is often difficult to identify
commonalities among these different, but conceptually related
Signal
schemes, this tutorial paper aims to provide a unified and A/D
Conditioning
system-oriented perspective of the field. Digital
Analog Media Signal
CLK
and Processing
I. INTRODUCTION Transducers
Signal
D/A
The continuing downscaling of feature sizes in integrated Conditioning
circuits has enabled the realization of ever more complex
Digital Enhancement
electronic devices. In addition to purely digital functions such
as microprocessors, we have seen an extraordinary growth in Figure 1. Block diagram of a generic electronic system with digital
wireless and wireline communications. Since most enhancement.
communication channels are “analog” in nature, such
applications are typically partitioned into an analog front-end The purpose of this paper is to provide an overview of the
and a digital back-end processing unit. state-of-the-art in digital enhancement techniques,
highlighting challenges and opportunities from a system-level
Since the analog and digital system elements usually obey perspective. We begin our discussion by outlining the
different limits and technology trends, proper partitioning is an tradeoffs and scaling trends of analog and digital circuits in
important challenge. This is particularly so in cases where the Section II. Section III identifies the different hierarchical
analog interface constitutes the system’s bottleneck. In recent levels at which digital enhancement can be used. Section IV
years, we have seen growing efforts to push the digital provides additional examples and insight into specific
processing functions “closer to the antenna,” aiming for a applications.
reduction in the complexity of performance-limiting analog
elements. In addition to minimizing analog content, there has II. CIRCUIT LEVEL CONSIDERATIONS
been a clear trend toward digitally enhanced analog design,
aiming to leverage digital correction and calibration A. Digital Logic
techniques to improve the analog performance. Over the past decades, integrated circuit technology has
Historically, digital enhancements to analog circuits have been scaled according to Moore’s law, aiming to double the
evolved at the block level of specific functions, as for example number of transistors per die every two years. A direct result
linearity calibration in A/D converters. In this classical of this scaling trajectory has been the tremendous
scenario, digital correction is more or less applied as an improvement in the performance of digital circuits. For
afterthought and without considering the overall system. With instance, lead microprocessors have shown a doubling in their
the growing complexity in today’s applications, there exists an computing power roughly every 15 months. Alongside with
opportunity to explore a more holistic view of digital these improvements in speed comes a significant reduction in
energy per logic operation. As explained in [1] the typical 0.7x logic gates (see Table 1). These data suggest that at low signal
scaling of features along with aggressive reductions in supply fidelity, e.g. SNDR=30dB, a single A/D conversion consumes
voltage have led to a 65% reduction in energy per logic as much energy as toggling 4,679 logic gates. On the other
transition for each technology generation. The survey data hand, at 90dB SNDR, more than two million logic gates
presented in [2] suggests that a 2-input NAND gate dissipates would need to transition to consume the energy of an A/D
roughly 1.3pJ per logic operation in a 0.5-µm CMOS process. conversion.
The same gate dissipates only 4.5fJ in a more recent 90-nm
The data of [2] also states a progress rate for the energy
process; this amounts to a ~300x improvement in only 10
used in A/D converters. According to published results from
years.
ISSCC 1997-2007, the average energy across all resolutions
B. Analog Circuits has decreased by a factor of 35. Relative to the previously
stated 300x improvement in logic gates, this means that the
Unlike their digital counterparts, most analog circuits are relative “cost” of digital computation has reduced roughly by
constrained by electronic noise, linearity and matching a factor of ten over the past decade.
requirements; factors that at best conditionally benefit from
technology scaling. Generally, the achievable performance
and power dissipation of an analog circuit is a complex TABLE I. ENERGY/CONVERSION IN A/D CONVERTERS (EADC)
RELATIVE TO LOGIC GATE ENERGY (ENAND=4.5FJ) IN 90NM CMOS.
function of specifications, technology, implementation and
architecture. However, several basic trends can be identified SNDR [dB] EADC EADC/ENAND
as a function of the “signal fidelity” that an analog circuit must 30 21 nJ 4,679
deliver.
50 168 nJ 37,432
Circuits that operate at low resolutions, e.g., 6-bit A/D
converters, are usually not impaired by thermal noise. A 70 1.35 µJ 299,479
significant limitation in this class of circuits stems from 90 10.8 µJ 2,396,045
matching. With appropriate mismatch calibration techniques
in place, low resolution circuits do reasonably well at
extracting a scaling benefit that is close to that of digital logic. While the numbers in Table 1 present no hard bounds or
In recent high-speed flash ADCs we have seen conversion fundamental limits, they provide a general feel for how many
rates on the order of 5GS/s, approaching speeds seen in lead logic gates can be used today for digital enhancement. For
microprocessors. instance, in a system with fairly low SNR, it is unlikely that
At the high end of signal fidelity, say at 16-bit resolution tens of thousand of gates can be used for digital enhancement
for audio, thermal noise is the main culprit. Much of the without exceeding reasonable energy or power limits. A large
energy dissipated in such analog circuits is spent driving large number of gates may be affordable only if the involved gates
capacitances and/or low resistances that facilitate low noise operate at a low activity factor or if they can be shared within
operation. Additional constraints arise in such circuits due to the system.
the need for high linearity. For instance, using large gain in Conversely, in very high fidelity circuits, each analog
analog feedback loops amounts to additional power that is operation is very energy consuming and even a large amount
spent to achieve highly linear operation. Between the two of digital processing can typically be accommodated in the
outlined extremes of “low” and “high” fidelity circuits exists a overall power budget. A well-known example that reflects this
space that obeys a complex mix of the described tradeoffs. case is a high-resolution sigma-delta A/D converter. Even in
Due to the large variety in analog circuits and the fairly old technologies, it was reasonable to justify high gate
complexity of the involved dependencies, it is hard to identify counts in the converter’s decimation filter; simply because the
clear and universal trends in performance. In [3] it was overall energy per sample in the analog portion of the circuit is
suggested that the throughput of A/D converters, measured very high.
through their speed-resolution product, doubles every 5 years; In light of the above analysis it becomes clear that a key
an improvement rate much slower than that of task in energy and power-limited mixed-signal systems is the
microprocessors. In recent years, analog speed improvements careful allocation of signal processing in either domain. A
have become hard to identify. This is primarily so for two widely accepted strategy in circuits with moderate to high
reasons. First, a large fraction of analog circuits is designed signal fidelity (e.g., SNDR>50dB) is to either minimize
for “fixed bandwidth” standards, i.e. no attempt is made to analog content or to relax the precision requirements on
optimize the circuit speed beyond a given spec. Second, power analog functions, e.g., using digital enhancements. The
dissipation has become a hard limiter for realizable throughput resulting approaches can be classified as discussed in the
levels; the achievable speed of a circuit may be larger than the following section.
power-limited bound.
III. HIERARCHICAL AND CONCEPTUAL CLASSIFICATION
Especially since power dissipation has become one of the
OF ENHANCEMENT SCHEMES
most dominant system limitations, it is more interesting to
compare the two domains – analog versus digital – in terms of As outlined above, optimum usage and synergistic
their relative energy per operation. Such a comparison was interplay of analog and digital functions is a must for meeting
carried out in [2] for typical A/D converter realizations and the requirements of next generation devices. Instead of
designing a collection of individual blocks, future devices are Efficient digital enhancement of analog circuits is only
likely to employ a holistic approach in which the functionality possible if their analog behavior is sufficiently well
of a traditionally isolated block is provided through the characterized. We have to identify an appropriate model as
support of other blocks and superposed protocols [4]. well as its corresponding parameters. The model is often based
on a priori knowledge about the system. The key parameters
Holistic Enhancement Approach that influence the system and their time behavior are typical
examples. However, in principle, we can also derive and
System Level
modify the model itself adaptively, which is the central topic
Enhancement of adaptive control theory. The parameters of the model are
tuned during the fabrication of the chip or during its operation.
Since fabrication-based calibration methods are limited, we
have to employ algorithms that adapt to a non-stationary
environment during operation. However, specifying and
Block Level Block Level Block Level
Enhancement Enhancement Enhancement
implementing robust adaptation algorithms that guarantee a
certain performance levels is a challenging task. Furthermore,
the design of, e.g., an A/D converter cannot be separated from
the system design anymore, since the calibration algorithms
Digital signal Mixed signal Analog signal rely on particular properties of the system. Therefore, a
processing processing processing
holistic approach to system and block design becomes
essential.
Figure 2. Holistic approach to digital enhancement of mixed-signal and
analog circuits. IV. EXAMPLES
As illustrated in Figure 2, a typical electronic system can A. Digitally Enhanced A/D Converter
be divided into analog, digital and mixed-signal blocks. The A specific example of a system-synergistic enhancement
mixed-signal blocks are essentially the data converter in the concept was reported in [6]. The scheme of Figure 3 uses the
system, where due to additional digital post- or pre-processing pilot tones of an OFDM system to measure and cancel offsets
the boundaries between analog signal processing and digital in a time-interleaved ADC array. With a proper ratio between
signal processing become blurred. Because of the increasing the number of channels and FFT size, the error signal due to
analog/digital performance gap and the flexibility of digital offsets is spread across the entire FFT spectrum. Since the
circuits, performance supporting digital circuits will become pilot bins of the FFT are modulated with a known pseudo-
an intrinsic part of mixed-signal and analog circuits. random sequence, errors due to the offsets can be extracted via
Digital enhancements of analog and mixed signal a correlation-based measurement. The measured errors feed
functions can be classified into system-level and block-level into a gradient descend algorithm, which applies offset
schemes. Block level enhancement refers to the improvement corrections until optimum performance is achieved.
of the overall performance of a particular block in the system,
e.g., the A/D converter. System level enhancement uses ADC7
system knowledge to improve or simplify block level baseband processor
enhancement tasks. Typical examples are crest factor pilot
+ ADC6 estim.
optimization in multicarrier systems [5], I/Q channel -
calibration in communication systems, and ADC calibration in -
FFT +
OFDM systems [6]. Vin pilots pilot
errors
Digital enhancement at the block level can be loosely + ADC2
categorized into digitally enhanced, digitally guided, and - calibration
digitally emulated circuits. Digitally enhanced circuits use logic
+ ADC1
digital signal processing to overcome shortcomings of the - offset adjustments
analog design and intentionally exploit the advantages of a
minimalistic analog design [7]. Therefore, the digital signal Figure 3. Block diagram of a digitally enhanced, time-interleaved A/D
processing is not necessary for the functionality of the overall converter using a system-synergistic approach. Specific system resources
block but significantly enhances its performance. Digital (FFT block, pilot tones) are used to facilitate background calibration.
calibration of A/D converters is an example [8-10]. Digital
guided circuits need the digital signal processing as an An advantage of this holistic enhancement is that costly
intrinsic part for the functionality of the overall system. Delta- resources, such as the system’s FFT block, are efficiently re-
sigma converters are examples of digital guided devices. The used for background calibration. While the specific goal of [6]
final group is the digital emulated analog circuits. Here, the was to calibrate offsets, many other possibilities exist for
digital signal processing is mainly responsible for the “training” the ADC and other system hardware using pilot
functionality. Digitally switched power amplifiers and all- tones. Furthermore, future systems could incorporate special
digital PLLs can be assigned to this category [11]. calibration signals that are different from existing pilot tones
and show superior properties for the purpose of hardware self-
calibration.
B. Digitally Enhanced Power Amplifiers analog and mixed-signal circuits is a multi-disciplinary
Due to their pervasiveness in today’s RF systems, power research field with many open questions and opportunities.
amplifiers represent a very promising field of application for
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Christian Vogel
