MPSoC Design Research Papers

Power- and performance-aware IP mapping for NoC-based MPSoC platforms

2026, 2010 17th IEEE International Conference on Electronics, Circuits and Systems

In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media... more

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Model-driven reliability evaluation for MPSoC design

by Anthony Mouraud

2025, 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or... more

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Random Task Scheduler Algorithms as a Comparison and Access to the Best to Use in Real Time

by Haeder Talib Mahde Alahmar

2024

Today's real-time systems are the core of most ICT applications. The rapid development of such systems has attracted researchers' attention to optimize performance and to minimize as much as possible the problems and disadvantages they... more

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New voter design enabling hot redundancy for asynchronous network nodes

by Omar A.Emam

2024, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

In this paper, a novel voter design is presented which allows the voting of asynchronous network streams in flow-controlled networks. The voter synchronises incoming data streams automatically and is able to handle failure modes that... more

Modern payload data processing approaches on board spacecraft demand increased processing capabilities. In best case, data can be processed in real time while being streamed from a data source to a data sink, e.g. from a camera to a mass memory device. On its way, the data is possibly processed by several processor nodes in series. Fig. 1. Example for an image processing pipeline. An example would be an image processing pipeline as outlined in Figure | in which video data is first filtered, then -ompressed and finally encrypted. To make such a processing dipeline adaptable in terms of functionality and reliability, he different processing steps can be implemented on recon- igurable Field Programmable Gate Arrays (FPGAs). Since fast hardware implementations of the processing steps can be rather resource-demanding, techniques are necessary to also >xploit Multi-FPGA systems. An example for such a system is the Dynamically Reconfigurable Processing Module (DRPM) Jeveloped by University of Braunschweig and Airbus Defence and Space, UK [1]. This hardware development platform comprises a scalable number of payload data processing units with two reconfigurable SRAM-based Virtex-4 FPGAs and one LEON3 microprocessor per unit. The development platform is available for our own research on an adaptive Fault Detection,

Fig. 2. Stream Processor Architecture. In the proposed FDIR framework, the aforementioned processing steps are executed by dedicated stream processors which can process incoming data streams independently. A typical architecture of such a stream processor is shown in Figure 2. An IP core of the desired functionality is em- bedded into a wrapper. This wrapper comprises a Network on Chip (NoC) interface for the data exchange, some state machine logic and a memory for state variables. Input control words are interpreted by the state machine while input data words are directly fed into the IP core. An additional memory holds all variables necessary to configure the IP core. If the processing pipeline uses a specific protocol, a protocol parser and/or protocol generator may be added to the input and output of the core. Partitions which can host such a stream processor are implemented on SRAM-based FPGAs. They are connected to a packet-switched, flow-controlled NoC and can be reconfigured during operation by means of dynamic partial reconfiguration.

Fig. 8. State diagram of the voter sub-module. Fig. 7. Circuit of the non-blocking broadcast mechanism. by the embedded Word-Voter [12] which is implemented as follows:

Fig. 5. Different failure modes that can be observed in network streams. [V. FAILURE MODES AND THEIR EFFECTS

Fig. 9. Fault injection system. The voter module has been successfully implemented on a Xilinx Virtex-4 SX55 FPGA as part of the DRPM hardware system, see Section I. If the network data width is chosen to be 16 bit wide, the design occupies 1,237 slices (5%) and the achievable clock frequency (after place & route and without further timing constraints) is ca. 107 MHz, i.e. the design can easily handle data streams with throughput rates of 1.6 and more Gbit/s. The utilisation of logic resources is ruled by the four NoC interfaces.

The signal slot_status(3:1) is a register which stores the health status of each slot and which can also be updated by an external instance. The registration of the new status is done in several steps. If a write enable signal is active, the new status is temporarily stored and a pending flag is set for each updated slot.

repaired processor into the running voting process as soon as possible. Fig. 6. Block diagram of the voter module.

Fig. 3. Flow-control mechanism between two network nodes.

‘ig. 4. Distributed Failure Detection: Example network topology. The paper is structured as follows. In Section II, the motivation for the development of the new voter design is explained. In Section II, a brief overview of related work is given. In Section IV, different failure modes are analysed which must be anticipated to occur in the output network streams of processors. Based on this analysis, a robust voter design is proposed in Section V which is able to cope with all failure modes found. Finally, in Section VI, a hardware imple- mentation is evaluated by means of fault injection experiments.

3) State S3: This state is entered once the timeout has expired in state S2, i.e. not every healthy slot received a packet. The state is left under three possible conditions. If only two slots were healthy before, all slots must be marked as faulty and the state machine moves to idle state $1. If all slots were healthy and two packets arrived, the slot without packet is marked as faulty and the state machine moves on to state S4. If three slots were healthy and only one packet arrived, the slot in which this packet arrived is marked as faulty and the Last Resort Timeout value is loaded into the timer. Then, the state machine moves back to state S2.

TABLE I. VARIABLE DEFINITIONS: BROADCAST

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Security in MPSoCs: A NoC Firewall and an Evaluation Framework

by Polydoros Petrakis

2024, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur.... more

Fig. 2. Range search data structures using register-based parallel search.

Fig. 8. NoC delay for all setups of Table II, when firewall is on (scale is logarithmic).

IMPACT OF THE FINE-GRAIN NOC FIREWALL ON NOC PERFORMANCE AND POWER CONSUMPTION FOR DIFFERENT SCENARIOS IN THE 2CPU2MEM SETUuP. INJECTION RATE Is 0.1 PACKETS PER CYCLE IN EACH CPU. NOC IS SATURATED IN ALL SCENARIOS Fig. 10. NoC firewall implemented in a Xilinx Zynq-7020 FPGA.

Fig. 6. Power consumption at the routers for all setups of Table II, when firewall is on or off.

Fig. 7. NoC delay for all setups of Table II, when firewall is on or off (scale is logarithmic).

Fig. 5. We use different configurations to study the effect of security. We perform experiments for up to 32-nodes connected to STNoC. Case (a) corresponds to two different configurations; either both CPUs or only one CPU can be active. (a) 4-node STNoC. (b) 8-node STNoC.

Fig. 9. Network latency measured from NI-to-NI. Figure illustrates all com- ponents found in the path of a packet transfer; NI source buffering, routers, NI at the destination. We propose integrating the security mechanism at the NI source.

EFFECT OF SECURITY ON QUEUE DELAY, NETWORK DELAY AND POWEI AT THE STNOC LEVEL. SCENARIO CONCERNS 4CPU/4MEM SETUP WITH 1S2M REQUESTS

LATENCY IN CLOCK CYCLES (3.3 ns) FOR READ/WRITE ACCESS USING THE NOC FIREWALL ATTACHED TO AXI4-COMPLIANT BRIDGE ON Zynq7020 FPGA

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Mapping functional behavior onto architectural model in a model driven embedded system design

by Prachi Joshi

2023, Proceedings of the 30th Annual ACM Symposium on Applied Computing

The ever-increasing complexity in embedded systems especially in the automobile industry in the recent years has necessitated model-driven engineering. In this paper, we consider the problem of mapping functional behavior onto an... more

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New voter design enabling hot redundancy for asynchronous network nodes

by Omar Emam

2023, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

In this paper, a novel voter design is presented which allows the voting of asynchronous network streams in flow-controlled networks. The voter synchronises incoming data streams automatically and is able to handle failure modes that... more

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Bandwidth Management in Router for DHCP Protocol

by Md. Abdullah Yusuf Imam

2023, International Journal of Scientific & Engineering Research

Network management and Performance management can be categorized as Bandwidth management. The process of administering and managing computer networks are Network management (NM) [1]. Ensuring that goals in an effective and efficient... more

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Model-driven reliability evaluation for MPSoC design

by Tien Thanh Nguyen

2023, 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE)... more

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Collaborative Routing Algorithm for Fault Tolerance in Network on Chip CRAFT NoC

by chakib nehnouh

2023, International Journal of Advanced Computer Science and Applications

Many fault tolerance techniques have been proposed in Network on Chip to cope with defects during fabrication or faults during product lifetime. Fault tolerance routing algorithm provide reliable mechanisms for continue delivering their... more

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Model-driven reliability evaluation for MPSoC design

by tien thanh nguyen

2023, 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE)... more

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A Review: Latency Comparison Between 2D Noc and 3D Noc

by Dr.Sarika Khandelwal

2023, Journal of emerging technologies and innovative research

3D integration technologies gives new opportunities for Network-on-chip architecture. Customized NoCs are the need of today’s SoCs as they offer optimized quality of service and enhanced performances because they are designed to support... more

Figure1: Comparison of Latency between optimized mapping same sized 3D and 2D Mesh topologies with similar traffic conditions The graph plotted in in fig.1 clearly shows that average latency per flit has reduced by a reasonable amount in the intelligently mapped 3D Mesh NoC in comparison to intelligently mapped 2D Mesh NoC as well.

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New voter design enabling hot redundancy for asynchronous network nodes

by Jørgen Ilstad

2023, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

In this paper, a novel voter design is presented which allows the voting of asynchronous network streams in flow-controlled networks. The voter synchronises incoming data streams automatically and is able to handle failure modes that... more

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Evaluating The Short Comings of Edge Detection Techniques

by Parul Anand

2023

Edge detection is one of the imperative concerns of vision transforming, in this paper; various traditional edge detection techniques are explored. Edge detection segments a given image where more honed change exists i.e. the limits of... more

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Runtime fault recovery protocol for NoC-based MPSoCs

by Fernando G . Moraes

2022, Fifteenth International Symposium on Quality Electronic Design

 Permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination.  The proposed approach determines new paths quickly, and the costs of extra... more

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An MDE Approach for Energy Consumption Estimation In MPSoC Design

by Smail Niar

2022

An MDE Approach for Energy Consumption Estimation in MPSoC Design Chiraz Trabelsi INRIA Lille Nord Europe France [email protected] Samy Meftali INRIA Lille Nord Europe France [email protected] Rabie Ben Atitallah INRIA Lille Nord... more

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Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems

by Geancarlo Abich

2022, 2018 IEEE International Symposium on Circuits and Systems (ISCAS)

Software reliability is an essential design metric in emerging large-scale multiprocessor embedded systems. Designers should identify soft error susceptibility of multiple applications executing in parallel early in the design time to... more

Fig. 6: Fault propagation to other PEs when injecting faults at a target PE.

Fig. 3: Task graph and mapping (color/fill) for all applications. PEC is the manager processor, not executing applications’ tasks. The experiments adopt a 2x2 HeMPS platform, with four PEs. From those, one is the MP (PEO) and the remaining SPs (PE1, PE2, and PE3), which are able of executing two tasks simultaneously. The experiments consider three applications: DTW, Dijkstra, and MPEG. The MP maps the applications’ tasks onto the SPs. Fig. 3 presents the task graph of each application, as well as their task mapping. Each application is evaluated separately, with the injection of a single-bit flip per simulation. Moreover, the experiments consider that faults can be injected in any of the available PEs individually.

Fig. 4: Evaluation of fault occurrence precision according to the number of fault injection simulations (executed application: MPEG).

Fig. 5: Fault injection campaign results grouped according to where the fault is injected (PE) for each application: (I) DTW, (I) Dijkstra, and (II) MPEG.

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An MDE Approach for Energy Consumption Estimation In MPSoC Design

by jean-luc Dekeyser

2022

An MDE Approach for Energy Consumption Estimation in MPSoC Design Chiraz Trabelsi INRIA Lille Nord Europe France [email protected] Samy Meftali INRIA Lille Nord Europe France [email protected] Rabie Ben Atitallah INRIA Lille Nord... more

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An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks

by Muhammad Khalil Afzal

2022, Applied Intelligence

In this paper, we propose an optimized, search based near-optimal mapping heuristic, named as ONMAP for mapping real time embedded application workloads on 2D based on-chip interconnection network platforms. ONMAP exploits NMAP, a... more

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A Review: Latency Comparison Between 2D Noc and 3D Noc

by Dr. Mayank Patel

2022

3D integration technologies gives new opportunities for Network-on-chip architecture. Customized NoCs are the need of today’s SoCs as they offer optimized quality of service and enhanced performances because they are designed to support... more

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An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture

by Dr. Tariq Umer

2022, IEEE Access

Network-on-chip (NoC) has appeared to be an impending substitute for the communication paradigm in modern very large scale integration embedded systems. Apart from many design challenges, application mapping on the NoC system is one of... more

FIGURE 4. Mapping of Context Adaptive Variable Length Coding (CAVLC) application on NoC architecture, with BEMAP algorithm

FIGURE 7. Performance comparison of BEMAP algorithm with traffic workloads. (a) Power versus traffic injection rate. (b) Throughput versus traffic injection rate. (c) Power versus CBR and VBR traffic. (d) Throughput versus CBR and VBR traffic.

TABLE 1. Platform description for simulation environment. applications are collected from literature and used for the analysis and evaluation of BEMAP algorithm [9], [22].

FIGURE 5. NoC performance parameters of 2D mesh topology, normalized to BB. (a) Network power consumption. (b) Network communication cost. (c) Network latency. (d) Network throughput.

FIGURE 2. Reduction in simulation speed with system size.

TABLE 5. Network power, communication cost and latency of torus topology.

TABLE 2. Network power, communication cost and latency of 2D mesh topology. The absolute values in Table 2 show that BEMAP per- forms better as compared to BB and NMAP algorithms and produces improved results for the network power consump- tion and communication cost. BEMAP has 0.83%, 13.97%, 1.83%, and 0.29% improvement in power consumption than BB under CAVLC, AUTO-IND, TELECOM, MMS and VOPD applications, respectively as shown in Table 3. The

TABLE 7. Simulation time and network throughput of torus topology. BEMAP algorithm is very impressive that goes up to 45.50% and 61.10% as compared to BB and NMAP algorithms, respectively. The improvement in latency is due to the inher- ent characteristics of the bypass links in the torus topology.

TABLE 3. Network power, communication cost and latency savings of 2D mesh topology. TABLE 4. Simulation time and network throughput of 2D mesh topology.

TABLE 6. Network power, communication cost and latency savings of torus topology. to the NMAP algorithm. The communication cost savings are up to 4.64% and 3.05% for BB and NMAP algorithms, respectively. The latency improvement by the application of

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Application Mapping using Cuckoo Search Optimization with Lévy Flight for NoC based system

by Fawad Hussain

2022, IEEE Access

Network on chip (NoC) is a promising communication infrastructure for multiple cores on a chip to exchange data efficiently. In such NoC architecture, application mapping is the process of assigning tasks to the processing cores. An... more

FIGURE 6: Throughput vs Flit Injection Rate network. Throughput of the network is calculated using (5) with NoCtweak. We have compared the throughput of the proposed algorithm with existing heuristics for standard ap- plications with different injection rates. Figure 6a-d represent the performance of throughput for different flit injection rates in the network. The results show that the proposed algorithm gives better throughput than NMAP, CastNet, SBMAP, and BEMAP at a higher traffic injection rate in most cases. VI. CONCLUSION In this paper, we have proposed a Cuckoo Search Optimiza- tion algorithm for the application mapping problem on the NoC systems. CSO algorithm is inspired by obligate brood parasitism of some cuckoo species by laying their eggs in the nests of other host birds and the Levy Flight behavior of some birds and fruit flies. In this technique, the initial population is generated with a Greedy random algorithm which is then optimized iteratively by applying Cuckoo Search via Lévy

Author et a/.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: L EE AnaAaAcmre 10.1109/ACCESS.2021.3120079, IEEE Access (d) mp3encmp3dec

TABLE 2: Rectangular mesh size. for MPEG4 is 2.94% for NMAP, 5.75% for GA, 7.99% for CastNet, 25.43% for SBMAP, and 5.76% for BEMAP. For MWD, CSO has 17.14% better results in cost than NMAP, 17.95% than GA, 14.29% than CastNet, SBMAP, and BE- MAP 0.18% than SCSO algorithm. CSO also perform: than PSO and SCSO in some applications. For exam s better ple, for DVOPD, CSO has 2.42% savings in cost compared to PSO and 0.18% compared to SCSO for MWD application. On average, CSO has an improvement of 11.02% over NMAP, 5.33% over GA, 4.28% over CastNet, 5.95% over S BMAP, 2.16% over BEMAP, 0.30% over PSO, and 0.03% over SCSO algorithm. BEMAP performs better in 802.1 larx and CAVLC applications but has more computation time t proposed algorithm. han the

TABLE 5: CSO saving in communication cost for rectangular mesh (%).

TABLE 1: Square mesh size. The Greedy algorithm is leveraged to generate the ini- tial population by placing maximum communicating tasks in close vicinity. In the initial population, a relatively pre- processed base is furnished to the main algorithm, and Lévy flight is utilized as a local search strategy which eventually provides the foundation for the fast convergence of the al- gorithm. Moreover, the probability of worst solutions P,, abound balances the global and local search, which implicitly generates new quality solutions as the algorithm progresses iteratively. Therefore, the CSO algorithm provides an optimal solution against each benchmark in relatively low computa- tional overhead, which makes the proposed algorithm more efficient among other state-of-the-art algorithms.

Author et al/.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS In light of these rules, cuckoo search via Lévy flight can be potted as the flow chart in Figure 1. Lévy flight is applied to generate a new solution x**1 for the i“” cuckoo, is represented as

FIGURE 2: Generation of i” nest in initial population for PIP benchmark. this article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: I Cc i= A rraAom 10.1109/ACCESS.2021.3120079, IEEE Access Algorithm |. The fitness of newly built nests is evaluated, and the best solution is updated accordingly. This procedure is repeated until maximum criteria are achieved. The proposed CSO mapping algorithm is implemented in the SystemC- based NoCtweak simulator to assess and analyze the results. Algorithm 2: Cuckoo search via Lévy flight.

TABLE 4: CSO saving in communication cost for square Mesh.

TABLE 3: Communication cost for square mesh. TABLE 6: CSO saving in computation overhead. Author et a/.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS

CSO algorithm saves computation overhead from existing bio-inspired algorithms like GA, PSO, and SCSO. Compu- tation time savings of the proposed algorithm for VOPD, MPEG4, MWD, 263encMP3dec, MP3encMP3dec and 263decMP3dec are 121.75%, 169.5%, 202.65%, 242.47%, 172.99%, and 223.88% respectively, in comparison with GA. Savings of CSO in computation time with respect to PSO are 113.84%, 188.75%, 203.72%, 242.47%, 172.99%, and 225.31% for above mentioned applications. Likewise, the computation time savings of CSO over SCSO are 26.04%, 67.5%, 76.64%, 64.19%, 52.56% and 54.18% respectively for these standard benchmarks.

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Communication Optimizations for Multithreaded Code Generation from Simulink Models

by Lisane Brisolara

2022, ACM Transactions on Embedded Computing Systems

Communication frequency is increasing with the growing complexity of emerging embedded applications and the number of processors in the implemented multiprocessor SoC architectures. In this article, we consider the issue of communication... more

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Data Flow and Control Optimizations for Hardware and Software Co-synthesis in Embedded Systems

by Alberto Sangiovanni Vincentelli

2022

Current co-design methodologies of control dominated hardware software systems su er from inecient hardware HW and software SW synthesis of the various reactive system tasks. In order to improve synthesis quality, we propose a methodology... more

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Security in MPSoCs: A NoC Firewall and an Evaluation Framework

by Kyprianos Papadimitriou

2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur.... more

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Security in MPSoCs: A NoC Firewall and an Evaluation Framework

by Antonis Papagrigoriou

2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur.... more

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Tiny – optimised 3D mesh NoC for area and latency minimisation

by Leticia Poehls

2022, Electronics Letters

Tiny is a scalable and efficient three-dimensional (3D) network-onchip (NoC) designed to reduce latency and area. A theoretical analysis demonstrates its efficiency when compared with a basic 3D mesh NoC. Mapping independent traffics with... more

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Integration and Implimentation System-Ona-Programmable-Chip ( Sopc ) in Fpga

by Mohammed ALareqi

2022

The real-time hardware application is developed around a FPGA hardware architecture that includes embedded processor MicroBlaze on the field programmable gate array (FPGA).This paper introduces a design of a Micro Blaze soft-core... more

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Security in MPSoCs: A NoC Firewall and an Evaluation Framework

by George Tsamis

2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur.... more

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A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

by Steve Kerrison

2022, Computer Safety, Reliability, and Security

In the sandbox world of cyber-physical systems and internetof-things a number of applications is only eclipsed by a number of products that provide solutions for specific problem or set of problems. Initiatives like the European project... more

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Enhancing virtual switching system of on-chip networks

by Rony Kassam

2022

the huge datacenters in the world used in the social networks, researching and computing centers, and storage devices have faced fundamental problem reflected in the need for high throughput to switch between the large numbers of virtual... more

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Multi-objective Design Space Exploration based on UML

by assis nascimento

2022, Workshop on UML for SoC (UMLSoC��06), San Francisco

Abstract. This paper proposes a Design Space Exploration (DSE) framework using UML-based estimation and a multi-objective design exploration mechanism. This framework allows the designer to automatically select the most adequate modeling... more

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Formal verification for embedded systems design based on MDE

by Francisco Nascimento

2021, Analysis, Architectures and Modelling of Embedded Systems

This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By... more

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Formal Verification for Embedded Systems Design Based on MDE

by Francisco Assis Nascimento

2021, IFIP Advances in Information and Communication Technology

This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By... more

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Exploiting the model-driven engineering approach to improve design space exploration of embedded systems

by Francisco Assis Nascimento

2021, Proceedings of the …

This paper proposes a design space abstraction, in order to decouple the exploration algorithm from the design space, which allows the application of the design space exploration (DSE) tool in different design scenarios and is appropriate... more

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A model-driven engineering framework for embedded systems design

by Francisco Assis Nascimento

2021, Innovations in Systems and Software Engineering

This work presents a Model-Driven Engineering (MDE) framework to improve embedded system design. The framework adopts concepts from MDE for the automatic generation of a control and data flow internal representation, starting from the... more

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Multi-objective Design Space Exploration based on UML

by Francisco Assis Nascimento

2021, Workshop on UML for SoC (UMLSoC��06), San Francisco

Abstract. This paper proposes a Design Space Exploration (DSE) framework using UML-based estimation and a multi-objective design exploration mechanism. This framework allows the designer to automatically select the most adequate modeling... more

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Formal verification for embedded systems design based on MDE

by Francisco Assis Nascimento

2021, Analysis, Architectures and Modelling of Embedded Systems

This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By... more

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Model driven engineering for MPSOC design space exploration

by Francisco Assis Nascimento

2021, Journal of Integrated Circuits and Systems

This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the... more

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Early embedded software design space exploration using UML-based estimation

by Marcio Araújo Oliveira

2021, Proceedings of the International Workshop on Rapid System Prototyping

In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: Platform-based Design, which maximizes the reuse of components; and Model Driven Development, which rises the... more

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Improving topological mapping on NoCs

by Juan M. Orduña

2021, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)

Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of networkon-chip (NoCs) include several key issues, and one of them is the decision of where... more

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Formal verification for embedded systems design based on MDE

by Francisco Assis Moreira do Nascimento

2021, Analysis, Architectures and Modelling of Embedded Systems

This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By... more

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Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC

by Juan Pedro Dominguez-Morales

2021, Electronics

The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their operations... more

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Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

by Adnan zahid Adnan zahid

2021, Electronics

This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to... more

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An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

by omar ahmed

2021, VLSI Design

Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem... more

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CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip

by Mostafa Moazzen

2021, 2012 15th Euromicro Conference on Digital System Design

Researches demonstrate that overheating can raise the risk of failure in electrical chips. Also, increasing processing demand of applications increase the number of IPCores inside the chips and subsequently make them being tightly... more

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CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip

by Mostafa Moazzen

2021

Researches demonstrate that overheating can raise the risk of failure in electrical chips. Also, increasing processing demand of applications increase the number of IPCores inside the chips and subsequently make them being tightly... more

communication flow. circles and black unidirectional arrows denote c,;eC. We can map them onto ways (figure | (b),(c),(d),(e)). By considering the therma model described at [6], on the topology is a ile and summation neighbor tiles due to n figures 1(b-e), Figure l(a) shows an Application Task Graph(ATG) consists four IPCores which includes a chain o In this ATG n,€N is indicated by he NoC mesh topology in differen the main portion of tile temperature function of energy consumed at tha of thermal correlation inducted by their vicinities and shorter distance. the red bidirectional arrows show existence of correlation for each couple of adjacent PCores. Moreover, figure 1(f) represents the normalized peak temperature of each mapping obtained using HotSpots [18]. According to the figure 1(f), the best shape with minimum correlation and without any overhead on the communication cost for our instance application graph, is a straight line, as you can see in figure 1(e). Therefore, based on the example, we search the application graph for finding a chain of IPCores that have high communication flow and place them on the nested squares, adopted to the topology as you can see in figure 2.

Figure3: inside_mapping strategy(a), around_mapping strategy(b) a ee eee ee ee ee Ee eee ee The mapping process starts with mapping first two IPCores of MFCG in order to assign mapping strategy to the ChainMap (figure 3 yellow tiles), then remaining IPCores of the MFCG are mapped based on the selected strategy. In our pseudo code, if the selected strategy is inside_mapping, then some columns which are not involved in this plan, should be preserved (figure 3(a) red tiles). The Occupied(t,) routine, preserves those columns by setting occupation parameters of appropriate tiles to “True”.

Figure 7: Improvement percentage of our mapping algorithm in contrast to NMAP algorithm We evaluate our temperature-aware mapping algorithm under four video processing applications including: MPEG4, VOPD, MWD and PIP. The simulation results are compared with NMAP algorithm for presenting a fair comparison. Our evaluation is done on three parameters including: tile temperature, communication cost and global atency. The simulation is applied to a mesh topology with 2mmxX2mm tile size, XY routing algorithm and wormhole switching. In our simulation, we use Noxim[18] and HotSpot[18] simulators. Noxim takes mesh scale and the traffic scenario as its input and returns per router energy consumption and also delay and throughput and some other useful parameters. Then we feed the power trace to he HotSpot5 for computing the router temperature. minimize thermal correlation consequently. The steps of GeneralMap are described at figure 6. After every stage of this phase, the mapped IPCore adds to the graph R, so the graph R denotes mapped JIPCores at GeneralMap’s description.

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Networked Power-Gated MRAMs for Memory-Based Computing

by Mostafa Rizk

2020

Emerging nonvolatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed... more

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Model driven engineering for MPSOC design space exploration

by Francisco Assis Moreira do Nascimento

2019, Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07

This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the... more

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Runtime Fault Recovery Protocol for NoC-based MPSoCs

by Alexandre M Amory and

2017

The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative... more

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MPSoC Design

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