Microelectronics

An industrially applicable process flow for the formation of rear side passivated solar cells has been suggested by IMEC in 2005. Since then considerable improvements in solar cell efficiencies have been obtained with that type of process. In parallel simplifications and cost reductions were needed to bring it to production. IMEC's Industrial Affiliate Programme (IIAP) offers industrial partners the possibility to actively join development efforts with IMEC and other partners sending residents to work at IMEC as part of a research team. Selected development results of this IIAP are presented here. On large area homogeneous emitter CZ-Si solar cells FhG-SE Cal-Lab confirmed solar cell efficiencies of 20.0 and 20.3% for screen printed Ag and reliable plated Cu front contacts, respectively. Fill factors of 80% have been achieved for fully screen printed (front and rear) solar cells with low cost rear side dielectric stack layers. Cu plated contacts show reliable module data in IEC ...

In this paper, a numerical solution for a plasmonic absorption modulator is presented with a six-layer structure consisting of an air superstrate, a gold layer, a barium titanate layer, a n type silicon layer, a gold layer and a thin-shell nanolattice aluminium oxide substrate. Regarding the suggested structure, the parameters related to the absorption modulation are investigated at different thicknesses. Here, the Pockels effect and the free carrier dispersion effect are considered simultaneously. The dispersion relation of this structure is analytically obtained and numerically solved by the Nelder-Mead method. The maximum calculated figure of merit is 12.79. Furthermore, according to our results, it is understood that this modulator has a high ability to be utilized in optical communication systems. Also, it could be integrated to the microelectronic systems and it is compatible with CMOS technology.

High reliability users of microelectronic devices have been derating junction temperature and other critical stress parameters to improve device reliability and extend operating life. The reliability of a semiconductor is determined by junction temperature. This paper gives a useful analysis on mathematical approach which can be implemented to predict temperature of a silicon die. The problem could be modeled as heat conduction equation. In this study, numerical approach based on implicit scheme and Arithmetic Mean (AM) iterative method will be applied to solve the governing heat conduction equation. Numerical results are also included in order to assert the effectiveness of the proposed technique.

In this paper, the realization of a fractional-order inductor of order less than 0.5 has been realized, where, semiconducting Quantum dots of Zirconium (Zr QDs) is the key component. When a TEM (Transverse Electromagnetic Mode) is used to design a fractional-inductor using a conducting core, it yields a fractional order of 0.5 which is also mathematically derived in this work. Here, in place of conducting fluid, different concentrations of Zr QDs in ethanol have been used which show different phase shifts of the current (less than 45 • ) with respect to voltages. These experimentally found results, confirm the realization of fractional-inductor of order α < 0.5.The fabricated device works perfectly with a temperature range of -10 • C to 45 • C with an aging of ≈ 1.5 years. Also, the fabricated inductor has been used in an integrating circuit, which shows the change in roll-off-rate, and cutoff-frequency variations with respect to the variation in concentration of Zr QDs in the ethanol solution as the core of fractional-inductor. These experimental values show a good agreement with the simulation with a maximum error percentage of 10 %.

Functional materials that combine mechanical robustness with autonomous self-healing are highly desirable for coatings and structural materials operating in aqueous environments. Here we report amphiphilic polyurethane-urea (PUU) networks incorporating polyethylene glycol (PEG) and polydimethylsiloxane (PDMS) segments together with dynamic urea linkages and aromatic disulfide bonds introduced via 4,4′-diaminodiphenyl disulfide (DPDS), further reinforced with amine-functionalized montmorillonite nanoclay. Density functional theory calculations establish the energetic hierarchy of the relevant dynamic bond reactions in vacuum and water, indicating that urea-related and disulfide pathways are kinetically accessible under moderate conditions, whereas urethane exchange is substantially less favorable. Guided by these insights, PUU networks and nanoclay composites were synthesized and characterized structurally and mechanically. The nanoclay was well dispersed within the amphiphilic matrix and significantly increased the storage modulus of the materials. Remarkably, incorporation of amine-functionalized nanoclay accelerated healing kinetics despite substantially increasing the modulus of the network, mitigating the conventional trade-off between stiffness and self-healing. Tensile healing experiments showed that nanoclay-reinforced PUU-DPDS networks achieved nearly complete mechanical recovery, with toughness reaching 94% in air and 81% under water after 24 h. At elevated temperature, the strength recovered to about 90% after 8 h at 60 °C. These results demonstrate that reactive nanoclay nanoparticles can simultaneously reinforce polyurethane-urea networks and promote dynamic bond exchange, enabling mechanically robust coatings with efficient self-repair in both dry and aqueous environments.

Semiconductor surface cleaning, passivation and functionalization are critical steps for applications such as microelectronics, MEMS, sensors, and solar energy harvesting. Progress has relied in part on the development of surface chemical treatments. However, the ability to characterize surfaces at all steps of processing has also been essential and will be emphasized here. This work focuses on the chemical modification of oxide-free, hydrogen-passivated silicon, including wet chemical treatments, atomic layer deposition, and physical deposition. Characterization methods include in-situ infrared absorption spectroscopy, low energy ion scattering, x-ray photoelectron spectroscopy and mass spectrometry, and is complemented by ex-situ spectroscopic ellipsometry and atomic force microscopy.

We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.

Microtechnology becomes a versatile tool for biological and biomedical applications. Microwells have been established long but remained non-intelligent up to now. Merging new fabrication techniques and handling concepts with microelectronics enables to realize intelligent microwells suitable for future improved cancer treatment. The described technology depicts the basis for the fabrication of electronically enhanced microwell. Thin aluminium sheets are structured by laser micro machining and laminated successively to obtain registration tolerances of the respective layers of <5µm. The microwells lasermachined into the laminate are with 50…350µm diameter, allowing to contain individual cells within the microwell as well as provide access holes for the layer-to-layer contacting A permeable membrane attached to the bottom of the microwell plate is used for fluid handling. The individual process steps are described and results on the microstructuring as well as on biocompatibility of the materials are given.

Dense and aligned single-walled carbon nanotubes (SWCNTs) were synthesised in nano-sized silicon dioxide holes patterned using electron beam lithography for microelectronics applications. Carbon nanotubes are new materials with potential uses for interconnects and field effect transistors (FETs) of LSI. As single-walled carbon nanotubes have lower resistance than multi-walled carbon nanotubes in close-packed arrangements and show both metallic and semiconducting behaviour, there is a great deal of interest in using dense SWCNTs for low resistive interconnects and high current transistors. Here, we report not only a method for fabrication of SWCNTs in nano-sized holes, but also differences in growth rate and Raman spectroscopy of CNTs in holes of various sizes. The growth rate of CNTs in the holes decreased as the hole size was reduced, due to the amount of carbon radicals diffusing to the catalyst particles at the bottom of the holes.

Now a days, mobile networks is increasingly becoming important part of everyday life due which there is a rapid evolution mobile phone. Mobile phone comes into a powerful sensing platform. There are many scientists which are engaged in the emerging field of mobile sensing from a variety of existing communities, such as, mobile systems, machine learning and human computer interaction. The research and development in this field is rapid resulting in indispensable carry-on of daily life. But with the increase in development, data integrity and security has also become an important factor to take into consideration. Importantly, today's smart phones are programmable and come with a growing set of cheap powerful embedded sensors, which are enabling the emergence of personal, group, and community scale sensing applications. The mobile sensing platform provides many facilities like, it helps to communicate to Wireless sensor networks through a mobile sensor router Which attached to a users mobile phone. It helps in analysis of the sensed data which is derived from networks by cooperating with sensor middle-ware on a remote server to capture ones contexts. It also helps in providing context aware services for mobile users of cellular telephones. In this paper, we will discuss about different mobile sensing platforms that provides context-aware services for mobile users by accessing the surrounding wireless sensor networks. Along with this, we will briefly discuss some of the emerging sensing paradigms.

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. To address the limitations imposed on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design processes, in this paper we introduce physical synthesis concept in quantum circuits to improve the objectives by manipulating layout or netlist locally considering layout information. We propose a technique for physical synthesis in quantum circuits using gate-exchanging heuristic to improve the latency of quantum circuits. Moreover, a physical design flow enhanced by the technique is proposed. Our experimental results show that the proposed physical design flow empowered by the gate exchanging technique decreases the average latency objective of quantum circuits by about 24% for the attempted benchmarks.

The recent development of data-intensive applications using artificial intelligence (AI) has exposed the fundamental flaws in traditional electronic computing designs, including latency, bandwidth constraints, and excessive power consumption. A possible paradigm that blends the adaptability and experience of electronic systems with the speed, parallelism, and minimal loss of photonics is hybrid photonic-electronic structures. With a focus on AI-driven photonic design techniques, this article provides an extensive analysis of next-generation hybrid architectures intended for intelligent embedded systems. We investigate electronic-photonic co-design techniques, silicon photonic integration, photonic neural networks, and system-level designs. Additionally, the use of AI to inverse photonic optimization and design is examined. When compared to traditional systems, its performance studies show notable gains in throughput, latency, and energy economy Future research opportunities for fully scaled photonic computer ecosystems are outlined, along with challenges including integration complexity, conversion overhead, and optical nonlinearity.

The final cost of an integrated circuit (IC) is proportional to its testing time. One of the main goals of test engineers when building an IC test solution is to reduce test time. Reduction of Test time is achieved by multi-site testing where multiple ICs are tested simultaneously using automated test equipment (ATE). During multi-site testing, if a certain test requires abundant resources, it is accomplished by testing one set of ICs at a time while the other ICs remain idle, thus lengthening the total test time. In digital-analog hybrid ICs, both analog and digital tests need to be performed, increasing the tester resource requirement and causing digital resource shortage. This paper describes a hardware interface board (HIB) design for a test case of a digital analog IC on Teradyne’s ETS-364 ATE. The HIB's design allows the ATE to perform multi-site I2C based tests, which usually require lot of tester resources, utilizing only two digital resources and one measurement resource. This design achieves halving the I2C test time while lowering the number of resources necessary for multi-site testing compared to set-by-set testing. The proposed work has achieved up to 90.625% of resource reduction for multi site testing for a single test.

Direct Digital Synthesizers (DDSs) or Numerically Controlled Oscillators (NCOs) are nowadays prominently used in the applications of RF signal processing, satellite communications, etc. This paper brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed design, which is based on pipelined CORDIC, has considerable improvement in terms of spurious free dynamic range (SFDR) compared to other existing designs at reduced hardware. The design is implemented on Xilinx XC3S500E-4FG320 FPGA, fabricated in 90 nm process technology. The design has utilized 487 slices and 967 4-input look up tables (LUTs) as its hardware count. The maximum sampling frequency of the proposed design is 107.216 MHz. The SFDR of proposed DDS is -96.31 dBc.

The drive to faster data transmission speeds, more integration, smaller form factors and higher signal integrity all favor the eventual adoption of optical transmission schemes in data buses. This contribution will discuss emerging technologies from Rohm and Haas Electronic Materials LLC 1 to address the needs of optoelectronic signal transmission. In particular, the discussion will focus on materials and processes that are in development to function within existing printed circuit board (PCB) & microelectronic manufacturing schemes. One topic that is described in detail involves photo-patternable, polymer interconnect technologies. Another topic describes progress in Rohm and Haas Electronic Materials ability to integrate these interconnects into prototypical PCB processes. Progress in connecting the planar waveguides to connectorization schemes will be also be described. Other topics include lithographic and patterning metrics, optical characteristics of interconnects, morphological features of patterned waveguides, integration and coupling considerations, thermal and mechanical properties of the system and general assembly processes.

New statistical properties of optical waves due to multiple elastI c scattering will be presented . An analysis will be given of the effect of the vector nature of the wave and restricted geometries on fluctuation and correlation phenomena . In particular . we will discuss the following effects: (i) polarization and angular memory effects. (ii) microstatistics . and (iii) non-Rayleigh statistics .

TUTOR is an application that aims to provide incorporation of entrepreneurial characteristics and self-knowledge to users. Thus, is proposed the suggestion of groups where low competence characteristics must be mitigated by other users in the group. This process is related to Independent Set problem and requires exponential time. In this context, a heuristic algorithm was developed based on GLP heuristic and presented good results, finding best solutions in polynomial time frequently. Despite the small amount of data in TUTOR, the algorithm is able to suggest groups with a few undesirable cases. Conjunto Independente e demanda tempo exponencial. Neste contexto, foi desenvolvido um algoritmo heurístico, baseado na heurística GLP, que apresentou bons resultados, encontrando as melhores soluções conhecidas em tempo polinomial. Apesar do pouco volume de dados no TUTOR, o algoritmo foi capaz de sugerir grupos, apresentado poucos casos indesejáveis. McClelland (1972) mostrou que empreendedores de sucesso possuem algumas características comportamentais que os diferem dos demais. Estas foram organizadas em três grandes grupos, sendo eles: (i) Conjunto de realização; (ii) Conjunto de planejamento; e (iii) Conjunto de poder. Neste contexto, a ferramenta TUTOR, proposta por Pessoa (2011), tem por objetivo monitorar e proporcionar a incorporação de tais características nos usuários, possibilitando a compreensão das mesmas e relacionando-as com atividades cotidianas. Desta forma, a ferramenta proporciona autoconhecimento aos usuários, o qual é a base para o processo de desenvolvimento. Sendo assim, o TUTOR fornece ao usuário a compreensão de características fortes e fracas em seu comportamento, permitindo que o mesmo trabalhe para compensar vulnerabilidades. Este trabalho propõe a ampliação da ferramenta TUTOR, desenvolvendo uma funcionalidade que possibilite a sugestão de equipes de empreendedores com características complementares, de modo a amenizar os pontos fracos de cada

A charge pump for phase locked loops (PLL) with a novel current mismatch com pensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The pro posed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

Moving away from their in-house computing capabilities, Italian SME Ergolines is employing supercomputing facilities provided by PRACE to radically improve the steel casting process. The SHAPE Project was jointly led by Dr Ahmet Duran and Dr Yakup Hundur from Istanbul Technical University (ITU), and Ergolines’ scientific team, to simulate the complex geometries that will help to improve Ergolines’ design and product development

Mixed-signal sensor interface circuits enable interaction between analog real-world signals and digital processing systems. This paper presents the design and analysis of such circuits for real-time monitoring applications. The study focuses on analog front-end design, signal conditioning, noise considerations, comparator-based threshold detection, and analog-to-digital conversion techniques. Key components such as operational amplifiers, comparators, filters, and analog-to-digital converters are discussed. Design challenges including noise, nonlinearity, offset, power consumption, and layout parasitics are also analyzed. These circuits play a crucial role in improving system accuracy, sensitivity, reliability, and response time in modern electronic applications.

Since its introduction, focused ion beam (FIB) technology has expanded from micro/nanofabrication in the semiconductor industry to the field of multimodal characterization of metallic material microstructures. This article systematically reviews the latest research advances in FIB-SEM technology in the field of metallic materials science. The fundamental principles and system functions of FIB-SEM are introduced, with an emphasis on its key applications in two-dimensional and three-dimensional morphological characterization, as well as specimen preparation for transmission electron microscopy (TEM) and atom probe tomography (APT). The combined strategies of FIB-SEM with electron backscatter diffraction (EBSD), time-of-flight secondary ion mass spectrometry (TOF-SIMS), and other characterization techniques are also discussed. Current developments indicate that FIB-SEM technology is advancing toward multi-ion-source synergy and multimodal integration. In the future, combined with artificial intelligence and big data analysis, it is expected to enable high-throughput, correlative measurements of multidimensional properties at the micro scale, providing important technical support for "materials genome" research in metallic materials.

We discuss deep reactive ion etching (DRIE) as a promising technology that can be readily applied in the micromanufacturing of low-thrust propulsion systems to be used on future generations of micro-and nanosatellites. This dry processing technique permits the fabrication of high-aspect-ratio silicon structures and intricate morphologies, both with tight tolerances, in a repetitive and controllable fashion that lightweight space vehicles will exploit with the introduction of smaller thrust components for precise maneuvering and attitude control. The etching approach described herein is counted among the present state of the art techniques utilized in the current trend toward miniaturization of sensors and actuators. This trend is being propelled by the increased technological capability as the enabling factor for size reduction. Scaling laws, especially the cube-square law, can be successfully applied for obtaining macropower from microdevices manufactured with the silicon technology that has developed for microelectronics applications, including DRIE. The application of this plasma etching technique in the fabrication and testing of silicon supersonic micronozzles is also described.

There are recorded downtime in the current testing processes of microelectronic packages. The available test equipment, the isolation of the power supply modules, and the processes of testing must be changed in order to minimize the downtime. This study presents the design and development of a voltage monitoring device made of a 14-bit analog to digital converter (ADC) interfaced through inter-integrated circuit (I2C) for power supply module 6 (PS6). It is built to address the downtime in isolation and testing process of PS6. This setup is able to monitor and display three output voltages operating in 4-12 V signals through a thin film transistor (TFT) monitor. Tests were conducted for the nominal voltage and current settings called the three-point tests. In result, the fault detection and calibration process of PS6 are able to minimize downtimes. The developed voltage monitoring device has an acceptable percentage of 0.04572% which also can be a replacement for digital multimeters (DMMs) for specific applications to PS6.

In this work, a comparative analysis by simulation using MATLAB in order to examine the MgxZn1-xO/ZnO and AlxGa1-xN/GaN high electron mobility transistors (HEMTs), with an emphasis on the impact of material composition and structural parameters on their electronic performance. Through the investigation of sheet carrier density (ns) in relation to gate voltage (Vgs) across various molar fractions (x) and its dependence on barrier thickness for different donor concentrations (ND), this study highlights the responsiveness of two-dimensional electron gas (2DEG) formation to both intrinsic polarization effects and extrinsic design considerations. The simulation framework incorporates both spontaneous and piezoelectric polarizations that are characteristic of the wurtzite crystal structure, which are crucial in influencing charge transport at the heterointerface. The current voltage (I-V) behavior clearly illustrates how modifying material properties can influence the shift between linear and saturation regions. Findings indicate that MgxZn1-xO/ZnO structures provide greater control in specific scenarios, underscoring the critical role of material selection in developing future wide-band gap semiconductor technologies.

Achieving high stable Power Transfer Efficiency (PTE) in Wireless Power Transfer (WPT) systems remains challenging due to the nonlinear, multimodal nature of the optimization space. Conventional algorithms such as Genetic Algorithms (GA), Differential Evolution (DE), and Simulated Annealing (SA) often face premature convergence, sensitivity to parameter settings, and inconsistent performance across runs. To overcome these issues, this study introduces the Evolutionary-Swarm Hybrid Algorithm (ESHA), which integrates DE for directional exploration, GA crossover for population diversity, SA for adaptive convergence, and Lévy Flights for stochastic global search. ESHA was implemented on a WPT system with a fixed 20 cm transmission distance and compared with GA, DE, and SA using three performance indicators: PTE, convergence speed, and computational efficiency. Results show that ESHA achieved a maximum PTE of 97.18%, surpassing GA (96.81%), DE (96.65%), and SA (96.19%), while maintaining zero variance across independent runs. It converged in an average of 31.2 iterations, slightly faster than GA (33.15) and SA (32.1), and comparable to DE (31.3). Execution time was 0.4738 s, close to GA (0.4654 s) and only marginally higher than DE (0.4262 s) and SA (0.4329 s). Statistical validation confirmed significant improvements in PTE (p < 0.05).

Power dissipation is becoming a limiting factor in the realization of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design technique,'; are now emerging. This paper provides an overview of the techniques and methodologies that have emerged in the past few years for DSP system design. These include techniques for minimizing power at architectural ~.nd algorithmic levels including DSP programming issues. In addition, the paper indicates some potential design directions.

The increasing die size, package dimensions and operating heat flux of AI chips impose stringent requirements on the mechanical compliance and reliability of chip-level thermal interface materials (TIMs). Polymer-based TIMs, particularly silicone gels, offer advantages such as mechanical flexibility, automated dispensability, and warpage accommodation in large packages; however, their application is limited by weak interfacial adhesion and siloxane volatilization. Therefore, it is essential to develop advanced non-silicone thermal gels. This study reports a poly(ionic liquid) (PIL)-based thermally gel TIM. The TIM was fabricated by dispensing a mixture of ionic liquid monomer, Al 2 O 3 thermal filler, and initiator, followed by thermal curing, making it compatible with FCBGA dispensing processes (the viscosity before curing was 225 Pa•s). With 70 vol% Al 2 O 3 filler, the PIL-based TIM exhibited a low storage modulus of 255 kPa and high interfacial adhesion strengths of 0.95 MPa to Cu and 0.91 MPa to Si. The intrinsic thermal resistance reached 2.4 × 10-5 m 2 •K/W, comparable to that of conventional silicone systems. Notably, the interfacial contact thermal resistance with Si (R c = 1.95 ± 0.87 × 10-7 m 2 •K/W) was an order of magnitude lower than that of silicone-based TIMs. Reliability tests showed > 98% coverage after three accelerated aging tests, with no leakage or volatilization. The proof-of-concept study validates the feasibility of PIL-based TIMs and highlights their significant potential for further optimization in next-generation AI thermal management.

Conductive hydrogels have emerged as crucial components for sophisticated flexible energy storage devices, such as batteries and supercapacitors, because of their customizable microstructures, mechanical versatility, and integrated electronic/ionic conductivity. Conventional fabrication methods face persistent challenges in balancing electrical performance with mechanical durability and constructing complex three-dimensional (3D) geometries. Three-dimensional-Printed addresses these limitations by enabling precise spatial control over material deposition customized, commercially viable flexible energy storage technologies.

Persistent wide-area intelligence, surveillance, and reconnaissance (ISR) operations increasingly require decisionsupport architectures capable of integrating heterogeneous sensor observations, behavioural inference models, and
civilian-protection constraints within supervised autonomy frameworks. This paper presents a hybrid probabilistic
ISR decision-support architecture designed to enhance engagement-priority estimation reliability during enduranceclass corridor-monitoring missions using lightweight delta-wing unmanned aerial platforms. The proposed
framework combines Bayesian intent estimation, trajectory-based anomaly detection, multi-sensor features fusion,
and probabilistic engagement ranking within a confidence-weighted inference pipeline that supports humanmachine teaming (HMT) oversight. A civilian-risk suppression mechanism is introduced to ensure that automated
prioritisation outputs remain consistent with humanitarian-protection requirements in populated or infrastructuresensitive monitoring environments. The architecture further incorporates supervisory validation thresholds that
preserve operator authority while reducing cognitive workload during persistent surveillance operations.
Experimental validation conducted using the HATSABIBI-26A long-range delta-wing UAV demonstrates
measurable improvements in behavioural inference stability, engagement-priority convergence, and operator
decision-support efficiency. Results indicate reductions in decision latency of 31%, improvements in engagementranking stability of 26%, and increases in target-discrimination accuracy of 22%, together with an 18% reduction
in supervisory workload under multi-modal sensing conditions. The findings confirm that probabilistic multi-sensor
fusion combined with civilian-risk-aware prioritisation provides a robust foundation for responsible supervised
autonomy in distributed ISR environments. The proposed framework is particularly suited for early-warning
surveillance, corridor monitoring, and infrastructure-protection missions where persistent observation,
interpretability, and protection of non-combatants remain primary operational objectives.

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Global electrification has been realized through lithium-ion battery system by extending its application into largescale devices and energy storage systems. Besides, economic regulations, such as those related to climate change and carbon neutralization, have accelerated the dissemination of battery chemistry for substitution of fossil fuels. As the battery application is widely expanded into large-scale system, additional requirements such as highenergy-density and long-term cycle stability have emerged, leading to the exploration of advanced battery materials and systems beyond conventional configuration. Thus, high-Ni cathode has attracted attention owing to higher specific capacity and unexpected issues arising from structural imperfection have been recently addressed through structural carving of materials. However, to deeply investigate battery systems using high-Ni cathodes, the perspective should be extended beyond the material to the electrode level. In this paper, emerging issues and systematic strategies for the advanced high-Ni cathode at the electrode level are reviewed to provide insight into compatible electrode/material design and highlight practical development toward high-energy-density batteries.

An amplifier is an electronic circuit that takes a weak electrical signal as input and produces a stronger version of the same signal as output. The shape of the signal stays the same-only its size (amplitude) increases. Amplifiers are everywhere. Every time you speak into a microphone, listen to music through speakers, or use a mobile phone, an amplifier is working inside the device. 1.1 The Core Idea An amplifier does NOT create power from nothing. It takes energy from a power supply and uses it to make the output signal bigger. A small input signal controls how much energy flows from the supply to the output. Simple Analogy: Think of a garden tap. A small hand movement (small input signal) controls how much water (power) flows out. The water comes from the mains supply-not from your hand. The amplifier works the same way. 1.2 Basic Facts Property Value / Description Circuit symbol Triangle (→) with input on left, output on right Main function Increase the amplitude of an electrical signal Key quantity Gain-the ratio of output to input Power source Yes-DC supply (battery or regulated power supply) Unit of gain No unit (plain ratio) or decibels (dB) Common IC example LM741, LM358 (Operational Amplifier-Op-Amp)

This paper presents a brief review of our recent work investigating a novel bottom-up approach to realize silicon based nanoelectronics. We discuss fabrication technique, electronic properties and device applications of silicon nanodots as a building block for nanoscale silicon devices.

Gait analysis is important in understanding human movement and diagnosing various mobility-related disorders. A crucial step in this procedure is the recognition of the different phases of human gait. An innovative, costeffective prototype of shoe insoles with sensors is presented, designed to capture data which are used for gait phase recognition with the aid of artificial intelligence. Each insole is embedded with capacitive sensors to record measurements and is accompanied by an inertial measurement unit (IMU) that monitors foot motion during walking. Using these prototypes, we collected data from multiple volunteers, while they performed simple walking exercises. The collected data, having undergone preprocessing, were used to train a long short-term memory (LSTM)-based neural network that recognizes the different gait phases during walking. The resulting model can segment a gait session into distinct phases with high accuracy, effectively demonstrating the capability of the prototype pair of insoles to be used as an inexpensive way to record data that can be used for gait analysis. The presented method has potential applications in rehabilitation and the early detection of mobility impairments. The most important benefit of the developed system is that it constitutes an affordable alternative to commercial solutions for patients who require medical care through telemedicine.

We describe here a novel approach to the subject of thermoelectric devices. The current best thermoelectrics are based on heavily doped semiconductors or semimetal alloys. We show that utilization of electric field effect or ferroelectric field effect, not only provides a new route to this problem, bypassing the drawbacks of conventional doping, but also offers significantly improved thermoelectric characteristics. We present here model calculation of the thermoelectric figure of merit in thin films of Bi and PbTe, and also discuss several realistic device designs.

A resonant tunneling diode, GaAs/In x Ga 1-x As/Al y Ga 1-y As/GaAs/Al 0.3 Ga 0.7 As/GaAs was studied under laser field. The effect of the pre-well potential In x Ga 1-x As on the current voltage characteristics was examined depending on the indium concentration. It has been observed that the current-voltage characteristic exhibits a critical value if the depth of the pre-well increased by increasing indium concentration. The electrons are accelerated for shallow pre-wells before that critical value and decelerated for deeper pre-wells than that of the critical value potential. In addition, the current is decreased increasing the width of the GaAs central well. The performance of the devices can be changed by applying a laser field when the geometric parameters are adjusted in resonant tunneling diodes.

This paper presents a molecular mechanics study using a molecular dynamics software (NAMD) coupled to virtual reality (VR) techniques for intuitive bio-nanorobotic prototyping. Using simulated bio-nano environments in VR, the operator can design and characterize through physical simulation and 3D visualization the behavior of protein-based components and structures. The main novelty of the proposed simulations is based on the characterization of stiffness performances of passive joints-based proteins (a-helix deca-alanine, repressor of primer protein and immunoglobulin protein) and active joints-based viral protein motor (VPL) in their native environment. Their use as elementary bio-nanorobotic components are also simulated and the results discussed.

This paper presents a molecular mechanics study using a molecular dynamics software (NAMD) coupled to virtual reality (VR) techniques for intuitive bio-nanorobotic prototyping. Using simulated bio-nano environments in VR, the operator can design and characterize through physical simulation and 3D visualization the behavior of protein-based components and structures. The main novelty of the proposed simulations is based on the characterization of stiffness performances of passive joints-based proteins (a-helix deca-alanine, repressor of primer protein and immunoglobulin protein) and active joints-based viral protein motor (VPL) in their native environment. Their use as elementary bio-nanorobotic components are also simulated and the results discussed.

Designs issues of a tunable matching network and a tunable phase shifter based on LTCC ferroelectric technology are discussed. Two devices are designed for operation in K frequency band. Test structure measurements are presented along with extracted parameters of used ferroelectrics (dielectric permittivity and tunability). Simulated and experimental performances are presented.

Traduzir é atravessar camadas invisíveis entre linguagem e significado.
Este trabalho, realizado por Gabriel Jacob Carneiro, nasce do compromisso de preservar não apenas palavras, mas ideias — mantendo viva a essência do texto original enquanto o reinscreve em língua portuguesa, sob uma perspectiva acadêmica e investigativa.

Esta tradução foi elaborada com o propósito de tornar acessível, em língua portuguesa, um conteúdo originalmente concebido em outro contexto linguístico e cultural. Mais do que uma transposição literal de palavras, o trabalho busca preservar a integridade conceitual, a nuance semântica e a intenção original do autor, respeitando a complexidade do texto de origem.

In recent fabrication technologies, buffered clock distribution networks have become increasingly popular due to increasing on-chip wiring delays. Traditionally, clock distribution networks has been optimized to minimize end-to-end skew of the distribution network. However, since most ICs have an on-chip PLL, we argue that the design goal of minimizing end-to-end jitter is more relevant. In this paper, we present a dynamic programming based approach to synthesize a minimum cost buffered H-tree clock distribution network. Our cost functions are a weighted sum of power and jitter, and a weighted sum of power and end-to-end delay of the distribution network. Our approach is based on precharacterizing the delay, jitter and power of buffered segments of different lengths, topologies, buffer sizes and wire-codes. Using this information, a dynamic programming (DP) engine automatically generates the optimal H-tree that minimizes the appropriate cost function. Compared to a manually constructed buffered H-tree network, our approaches are able to reduce both jitter (by as much as 28%, and power by as much as 46%. When optimizing for minimum jitter, the DP engine generates a H-tree with lower jitter than when optimizing for minimum delay, thereby validating our approach, and proving its usefulness.

A new and simple method to extract the effective channel length L eff of metal-oxide superconductor field effect transistor (MOSFET)s is presented. The method, which is developed based on an auxiliary integral function, has the advantage of determining the value of L eff not ...