Chrissavgi Dre

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Papers by Chrissavgi Dre

Lower MAC Software Implementations for the IEEE 802.16 Standard

IEICE Transactions on Communications, 2006

SUMMARY In this paper the development of the control plane for the frame decoding functionality o... more

Recovery Technique For Implementing DSP Algorithms,”

In this IC&D report, we provide two research works entitled:

format_quoteThe method's implementation involved various benchmark circuits, demonstrating notably low power estimations at 20 MHz and 5V.format_quote

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The low power baseband processing parts of a novel dual mode DECT/GSM terminal

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

In order to support a dual mode DECT/GSM terminal architecture, with low power characteristics an... more In order to support a dual mode DECT/GSM terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture the basic parts of such a terminal were designed and implemented. These parts include a baseband processor and a modem. The baseband processor is designed to support dual mode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm that supports direct conversion terminals. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the terminal are also presented.

The VLSI implementation of a baseband receiver for DECT-based portable applications

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

<title>Efficient address vector quantization based image coding scheme</title>

Advanced Image and Video Communications and Storage Technologies, 1995

ABSTRACT

Chinese Remainder Theorem-based Algorithm for Convolution

info:eu-repo/semantics/publishe

Low-power system-on-chip architecture for wireless LANs

IEE Proceedings - Computers and Digital Techniques, 2004

Low power design of a multi-mode transceiver

by Chrissavgi Dre and Dimitrios Soudris

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

Recent advances in electronic technology integration coupled with increasing needs for more servi... more Recent advances in electronic technology integration coupled with increasing needs for more services in portable communications favors the development of high performance dual-mode terminals. We present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and

Alternative architectures for the 2-D DCT algorithm

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Recently, a new fast algoritliin lias been proposed for the computation of the 2-0 N x N-point Di... more Recently, a new fast algoritliin lias been proposed for the computation of the 2-0 N x N-point Discrete Cosine Transform, where N is decoinposed into two mutually prime numbers NI and N2, [4]. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a inetliodology for systematic niappiiig of this algoritliin onto hardware is presented. The proposed methodology reveals the existence of a few connected coinpoiieiits iii the signal-flow graph (SFG) of the algoritliin aiid leads to architectures that can be systeinatically derived aiid exhibit varying throughput and hardware coinplexity. prime iiunibers N1 aiid N2 of which N1 is odd, while Nz is even. The index mappings that are used in the time and frequency domain are for ni,mi,ki> li E [O,Ni-11, where u i , b i , c i , d i are integer constants. Then, the sequence e(n1, n2, ml, mz) is transformed into the sequence f(n1, n2, m l , mz) by the set of equations AV2 f(.11(n2 +~)~~) m l , (m d 9) = 31n1,2N~-%-1,m1,2m2) Recently, a fast algorit,lun for tlie conipntatiori of the 2-D N x N-point D C T based on P F D lias been proposed [4]. This algorithm is of iiiterest wlieii .V is an even number but not a power of 2. Tlie 2-0 DCT is indirectly calculated using a N I x N: ! x K1 x Nz-poiiit DFT with an additional post-processing stage, oiily in two diinensioiis. The 40 D F T is realized throiigli a 2-0 D F T applied on another 2-0 D F T and Gert,iier's algorit,lini is used for tlie computation of tlie two 2-0 DFTs [GI. The

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Image coding using vector quantization of wavelet coefficients

Microprocessing and Microprogramming, 1994

Abstract In this paper, we introduce a new image compression scheme that it involves three steps:... more Abstract In this paper, we introduce a new image compression scheme that it involves three steps: First a multiresolution decomposition of the images is performed using the Wavelet Transform (WT). A thresholding algorithm is then used for the wavelet coefficients. Finally, the coefficients derived from the second step are vector quantized using a multiresoltuion codebook. The LGB algorithm is used for the Vector Quantization (VQ). Our experimental results showed that the Lena image can be coded by a two-level system at the rate of 0.24 bpp having a PSNR of 30.40 db.

Compressed maximum descent algorithm for codebook generation

Visual Communications and Image Processing '94, 1994

A vital step in building a vector quantizer is to generate an optimal codebook. Among the algorit... more A vital step in building a vector quantizer is to generate an optimal codebook. Among the algorithms presented in the literature, the Maximum Descent (MD) algorithm appears to be a promising alternative codevector generation technique to the generalized Lloyd (LBG) algorithm, when dealing with vector quantization of images. In this paper, a novel vector quantization codebook generation approach is presented. The algorithm uses an MD codebook as an initial codebook and a compression of this codebook is then achieved based on a simple feature clustering technique. According to this technique, we attempt to arrange the codevectors of the MD codebook in a way that prefixed number of clusters results. The centroids of the resulted clusters form a reduced MD codebook. Using this new technique we can produce codebooks with about 0.2 - 0.6 db improvement in peak-signal to noise ratio and a reduction of 10% - 20% in the codebook size compared to the LBG algorithm.

Coding wavelet coefficients of images

Proceedings of Third International Conference on Electronics, Circuits, and Systems

ABSTRACT In this paper, we introduce a new image compression scheme that involves three steps: fi... more ABSTRACT In this paper, we introduce a new image compression scheme that involves three steps: first a multiresolution decomposition of the images is performed using the Wavelet Transform (WT). A thresholding algorithm is then used for the wavelet coefficients. Finally, the coefficients derived are vector quantized using the LGB or the Compressed Maximum Descent (CMD) algorithm

On the computation of the prime factor DST

Signal Processing, 1995

In this paper a new algorithm based on prime factor decomposition for computing the discrete sine... more In this paper a new algorithm based on prime factor decomposition for computing the discrete sine transform (DST) is presented. The proposed 1-D N-point DST algorithm is indirectly computed by using the DFT. The DST of odd length can be implemented on the existing VLSI architectures of the DFT, while the DST of even length can be implemented on slightly modified DFT architectures. A comparison of the algorithm with other fast ones points out its computational efficiency, which is mainly based on the advantages of the prime factor decomposition and the proper choice of the index mappings.

The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal

Microelectronics Journal, 2004

In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteri... more In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture, the critical parts of such a terminal were designed and implemented using three different chips. These parts include a baseband processor, a modem and suitable analogue parts. The baseband processor was designed to support multimode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm supports a direct conversion terminal. The analogue circuitry includes analogue filters and Digital-to-Analog and Analog-to-Digital converters. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the multimode terminal are presented.

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Multi-stage hierarchical address vector quantization for image coding

International Journal of Electronics, 1995

A new vector quantization (VQ) scheme for encoding images is presented. The proposed scheme is ca... more A new vector quantization (VQ) scheme for encoding images is presented. The proposed scheme is called multi-stage hierarchical address vector quantization and it combines the concepts of multi-stage VQ (MSVQ), hierarchical VQ (HVQ) and address VQ (AVQ). Its encoder consists of several stages where the HVQ or AVQ is applied while the larger image blocks are divided into smaller sub-blocks.

Prime-factor DCT algorithms

IEEE Transactions on Signal Processing, 1995

In this correspondence, new algorithms are presented for computing the 1-D and 2-D discrete cosin... more In this correspondence, new algorithms are presented for computing the 1-D and 2-D discrete cosine transform (DCT) of even length by using the discrete Fourier transform (DFT). A comparison of the proposed algorithms to other fast ones points out their computational efficiency, which is mainly based on the advantages of prime-factor decomposition and a proper choice of index mappings.

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A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip

Lecture Notes in Computer Science, 2002

ABSTRACT In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LA... more ABSTRACT In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LANs is described. The reconfigurable System-on-Chip will realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The initial version of the system will include Mobile Terminal functionality. Future firmware versions will upgrade system’s functionality to allow its operation as Access Point. Functionality for operation in outdoor environments in wireless point-to-point links will be also targeted by future firmware upgrades. A system’s prototype is currently under development on the ARM integrator platform.

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