J. Jaehnig

A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

by Robert B Staszewski, Oren E Eliezer, J. Jaehnig, Mitch Entezari, T. Mayhugh, and Irene Deng

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of fir... more

Monolithic transformers in a five metal CMOS process

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002

Figure 6. On-chip transformer showing the inner terminals connected to the ground with underbridg... more

A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

by Chih-ming Hung, John Wallberg, Sudheer Vemulapalli, Mitch Entezari, J. Jaehnig, Khurram Waheed, T. Almholt, and S. Bhatara

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of fir... more

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

by Irene Deng and J. Jaehnig

IEEE Journal of Solid-State Circuits, 2006

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full inte... more We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of 110 dBm at 60 mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.

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