T. Mayhugh

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Papers by T. Mayhugh

Experimental Characterization of the Timing Properties of a Detector-Preamplifier System for Charged Particle Detectors Using a Laser Pulser

IEEE Transactions on Nuclear Science, 1977

The timing resolution performance of a commercially available preamplifier for use with charged p... more The timing resolution performance of a commercially available preamplifier for use with charged particle detectors has been measured. The excitation source was a laser diode pulser with a characteristic wavelength of 904 nm and a 1.8 ns pulse width FWHM. A wide variety of detectors ranging in capacitance from 27 pF to 750 pF were used in this study. The changes in timing resolution resulting from changes in the laser light intensity and changes in detector capacitance are described.

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An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers

IEEE Transactions on Circuits and Systems I: Regular Papers

A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of fir... more

A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS

2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009

In this paper we present a quad-band single-chip GSM/GPRS radio in 90nm digital CMOS process base... more In this paper we present a quad-band single-chip GSM/GPRS radio in 90nm digital CMOS process based on the Digital RF Processor (DRP T M) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly in an RF DAC. The receiver is based on direct RF sampling and discrete-time analog signal processing. A dedicated internal microprocessor manages the digital RF controls to provide best achievable RF performances. The transceiver exceeds all 3GPP specifications demonstrating a receive NF of 1.8 dB and a margin of 8dB on TX spectral mask at 400 KHz offset in GSM850/900 bands. The transceiver is best-in-class in area and occupies only 3.8 mm 2 of silicon area.

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A direct-conversion receiver for the 3G WCDMA standard

IEEE Journal of Solid-State Circuits, 2003

A highly integrated direct-conversion receiver that satisfies requirements of the third-generatio... more A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.

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The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

IEEE Journal of Solid-State Circuits, 2006

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full inte... more We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of 110 dBm at 60 mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates. Index Terms-All-digital phase-locked loop (ADPLL), built-in self-test (BIST), cellular, GPRS, GSM, low-area, low-cost, mobile phones, multi-tap direct sampling mixer (MTDSM), radio frequency (RF), sigma-delta, single-chip, system-on-chip (SoC), transceiver. I. INTRODUCTION L OW-COST wireless handsets are expected to find widespread use in the next few years in Asia and Africa. Investment in cellular infrastructure is now the preferred choice in developing and underdeveloped nations for improving the communication infrastructure and consequently, improving the standard of living of their people. Cost reduction is traditionally achieved by developing highly integrated solutions in addition to reducing the cost of individual components that make up the solution. A wide spectrum of choices exist ranging from highly integrated system in a package (SIP) to highly integrated system on a chip (SoC). The entire phone solution includes SAW filters, RF switches, power amplifiers, RF transceivers for several indoor and cellular standards, power management ICs, audio and video codecs, baseband processors, application processors, FLASH memory and several peripherals. Considering the diverse technologies needed to construct a mobile phone, the best solution appears to be a combination of SoC and SIP technologies. Recent research attempts to address various lowcost integration options [1]-[3] for wireless transceivers. An interesting side effect of this interest is that it paves the way Manuscript

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Constant-g/sub m/ rail-to-rail CMOS op-amp input stage with overlapped transition regions

IEEE Journal of Solid-State Circuits, 1999

Conventional techniques to achieve a constant-g m rail-to-rail complementary N-P differential inp... more Conventional techniques to achieve a constant-g m rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. An economical but efficient design technique to overcome these problems is proposed. The proposed technique strategically overlaps the transition regions of the tail currents for the n-and p-pairs to achieve constant overall transconductance. Experimental results demonstrate that gm variation can be restricted to within 64% with improved CMRR and frequency response.

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A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Analog Integrated Circuits and Signal Processing, 2011

Pulse Density Modulation-(PDM-) based class-D amplifiers can reduce nonlinearity and tonal conten... more Pulse Density Modulation-(PDM-) based class-D amplifiers can reduce nonlinearity and tonal content due to carrier signal in Pulse Width Modulation-(PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear-loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator-(ICO-) based frequency discriminator. By using the ICO as a phase integrator, a thirdorder noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.

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An Analog Integrated Circuit Design Laboratory

Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03, 2003

DOI to the publisher's website. • The final author version and the galley proof are versions of t... more DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

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A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process

This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillato... more This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm2 chip is implemented in 90 nm CMOS, operates over a 0.7 to 2.4 V power supply range and consumes 1.7 mW at 1 V and 520 MHz.

A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

by Robert B Staszewski, Oren E Eliezer, J. Jaehnig, Mitch Entezari, T. Mayhugh, and Irene Deng

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of fir... more

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