An Analog Integrated Circuit Design Laboratory

An analog integrated circuit design laboratory Citation for published version (APA): Mondragon-Torres, A. F., Mayhugh, J., Pineda de Gyvez, J., Silva-Martinez, J., & Sanchez-Sinencio, E. (2003). An analog integrated circuit design laboratory. In Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education, 2003, 1-2 June 2003, Anaheim, California (pp. 91-92). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/MSE.2003.1205269 DOI: 10.1109/MSE.2003.1205269 Document status and date: Published: 01/01/2003 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. 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If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 05. Jun. 2020  AN ANALOG INTEGRATED CIRCUIT DESIGN LABORATORY Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martinez and Edgar Sánchez-Sinencio Department of Electrical Engineering, Texas A&M University, College Station, Texas, 77840 [email protected] ABSTRACT The innovation in the implementation of this lab We present the structure of an analog integrated circuit consists of the creation, adaptation and integration of the design laboratory to instruct at both, senior different teaching materials available such as: undergraduate and entry graduate levels. The teaching Laboratory manual [1]; web page [2] with step by step material includes: a laboratory manual with analog instructions, examples and up to date information; use circuit design theory, pre-laboratory exercises and of industry grade design tools; and use of non-circuit circuit design specifications; a reference web page with related programs for automation and analysis. step by step instructions and examples; the use of 2. COURSE DESCRIPTION mathematical tools for automation and analysis; and The laboratory is based on a bottom-up design state of the art CAD design tools in use by industry. methodology. Each session is based on simple Upon completion of the course, the students have skills configurations, characterized by circuit design, layout, for an entry level analog designer position. simulation and measurement. By the end of the course, 1. INTRODUCTION the student has the ability to integrate these building There is a demand to prepare students in analog blocks to form complex systems such as continuous and microelectronics, and to be familiar with industry grade discrete time filters. The laboratory meets once a week IC design tools. The EE Department at Texas A&M and is divided in two sessions: One for simulation and University has developed a course in analog circuit one for physical measurement (MEA). design that covers the basic knowledge required for an 2.1. Simulation entry level analog designer position. At the beginning of the simulation session the This paper presents the organization of the student turns in the pre-laboratory exercises. The design laboratory section of the Analog VLSI Circuit Design is captured into Composer using the hand calculated (ELEN-474) class. The laboratory is a key part of the values. The simulations are performed using Analog course that fills the gap between theory and practice and Artist and Spectre. After the specifications are met, the its objectives are: circuit layout is designed using Virtuoso. The layout a) To understand the theory by designing circuits as procedure is: required in the pre-laboratory exercises. a) Generate a floor plan by identifying which b) To simulate and compare the design against the transistors should be matched and which would hand calculations. require special attention for proper layout. c) To produce a layout and compare it against the b) Execute the DRC to verify that the design complies schematic. with the design rules. d) To run a parasitic extracted simulation in order to c) Extract the layout to identify the devices generated verify performance matches against specifications. and also the non-desired parasitic devices. e) To run statistical analysis in order to predict the d) Run LVS tool to verify the correspondence between behavior of the circuit under parameter variations. the layout and the schematic. e) Generate an analog extracted cellview to perform The tools used in this laboratory are those available parasitic extracted simulations. with the Cadence Design Systems: schematic capture (CAP), circuit simulation (SIM), circuit layout (LAY), 2.2. Measurement design rule check (DRC), layout versus schematic check A set of ICs with equivalent circuits to those designed and simulated, are available for physical (LVS), circuit extraction (EXT), parasitic simulation measurement. As part of their pre-laboratory exercises, (PSM) and statistical simulation (SSM). In addition, the student proposes an experimental testbench setup to some mathematical tools are used as an aid to automate the design process, and also as a graphical user interface characterize and measure the circuit. After the students (GUI) for circuit analysis. obtain their experimental results, it is verified that the results are coherent with simulations. Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE  3. LABORATORY ORGANIZATION browsing on his/her own workstation as the TA explains 1. Introduction: Review of the Cadence design system the different steps required to complete the design. As and of the UNIX. Basics of CAP and dc SIM. the students work through their design, they can use the 2. Layout Design: LAY techniques: unit size web site to verify that the procedure is correct. transistors; common centroid and interdigitized 4.3. Mathematical Tools structures; and dummy transistors. Two mathematical programming tools have been 3. MOS Device Characterization: KP, VT, λ and γ are used to help automate the design procedure and to aid in extracted through SIM and MEA. The parametric the analysis of the design equations. These tools are (PAR) analysis is introduced. Matlab and Maple. A very useful application of the 4. Current Mirrors: Simple, cascode, feedback and mathematical tools is for the automatic generation of low-voltage. Design constraints: Zin, Zout, parameter files; e.g. the design equations are entered compliance, accuracy and complexity. Analyses: into Matlab, the output would be a text file which can be dc, ac and PAR. Run LVS. ac analysis is included into a Spice text simulation file. This introduced. procedure allows to run the mathematical tools and 5. Inverting Amplifiers: Current Mirror Load, Digital reflect the new design specifications in the simulation. CMOS, PMOS with self biased load and self biased 4.4. CAD Design Tools CMOS. Design constraints: GBW, PM and AV0. Texas A&M University is part of the Cadence The effects of power supply, source resistance and Design Systems North American University Software load capacitance are investigated. Analyses: dc and Program. The basic Cadence components used in this ac. PSM is introduced. course are the following: 6. Differential Amplifiers: Simple and cascode current a) Composer (schematic capture). mirrors. Design constraints: ADM, ACM, CMRR, b) Virtuoso (layout generation). CMR and SR. Analyses: dc, ac and transient c) Analog Artist (simulation front-end). (TRAN). TRAN analysis is introduced. d) Spectre HDL (circuit simulation). 7. Operational Transconductance Amplifiers (OTA): e) Diva tools (DRC, LVS, ERC, extraction). Symmetrical OTA. Design constraints: GM and SR. f) Hierarchy Editor (parasitic simulation) Analyses: dc, ac and TRAN. The static power (PW) g) Artist statistics (Monte Carlo Simulation and dissipation is measured and reported. statistical analysis tools) 8. Operational amplifiers (OP): Three stage OP. Cadence Design Systems tools have become the Design constraints: ADM, ACM, CMRR, PSRR, de facto industry standard. Texas A&M University has GBW, PM, Zout, SR and PW. Monte-Carlo analysis formulated the course according to the industry is introduced, the ac response is used to explore the requirements. effect of random variations on parameters. 9. Analog System: Continuous low pass filter. 5. CONCLUSIONS Macromodelling is introduced. A laboratory structure for an analog integrated 10. Switched Capacitor Integrators: Use of transmission circuit design course has been presented. The different gates, capacitors and OP. tools available, allow the students to concentrate more The grading policy applies 50% to the laboratory on the design issues rather than on software problems. reports, 40% to the pre-laboratory exercises and 10% to The laboratory manual sets the guidelines, complements the theory, develops a design procedure and sets the random assigned five minutes quizzes. specifications for each design. By using the web page, 4. TEACHING MATERIAL the student can go through the design steps and verify 4.1. Laboratory Manual that the results are correct. The use of mathematical The laboratory manual is the foundation of this analysis tools helps the student to automate some tasks laboratory, it contains the guidelines and the required that are otherwise repetitive. Moreover, the use of a theory to perform each design. The structure of each graphical interface allows the student to take design laboratory session is as follows: Objectives, decisions. The best layouts are fabricated using the Introduction, Design Description, Simulation and MOSIS service. The fabricated circuits are to be Layout procedure, Test Procedure, Pre-Laboratory, measured by the students of the forthcoming semester. Laboratory week 1, Laboratory week 2 and References. REFERENCES 4.2. Web Page [1] T. Mayhugh Jr and A. Mondragon-Torres, “Laboratory A WWW site has been created to complement the Manual for ELEN 474: VLSI Circuit Design”, Dept. of EE, laboratory lectures [2]. This resource has proved to be a Texas A&M University, Version 4.0, Sept. 1998. [2] http://amesp02.tamu.edu/~afmondra/elen474/ very useful tool. During the laboratory session, the student can follow the explanation given by the TA by Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE