Integrated Circuits for Analog Signal Processing

Esteban Tlelo‐Cuautle

doi:10.1007/978-1-4614-1383-7

Integrated circuits for analog signal process

daf dafd

https://doi.org/10.1007/978-1-4614-1383-7

visibility

…

description

327 pages

Abstract
AI

The book presents a comprehensive exploration of analog integrated circuits, focusing on analysis, design, and optimization of active devices. It covers essential topics such as bipolar and CMOS implementations, current feedback operational amplifiers, active filter design, and the application of nanometer technology in various systems, including biomedical sensors and wireless communications. The content serves as a crucial resource for students and professionals in the field, offering guidance on the usage of advanced circuit design methodologies and the challenges posed by nanometer-scale technologies.

Figures (235)

Fig. 1.1 (a) Operational amplifier, (b) operational transconductance amplifier, and (c) negative- type second generation current conveyor modeled by using nullors

Fig. 1.5 (a) Pathological-equivalent of the CFOA including dominant parasitics [1], and (b) Nullor-equivalent of the multiple-outputs current mirror including input impedance and indepen- dent gain and output impedances [5]

Fig. 1.7 Three stages uncompensated low voltage amplifier Fig. 1.8 Nullor equivalent of Fig. 1.7

Fig. 1.9 Comparison between HSPICE and the derived symbolic expression [7 The symbolic behavioral modeling of sinusoidal oscillators is quite useful for design purposes. Lets us consider the oscillator composed of OTRAs, as shown in Fig. 1.10. The system of equations by applying symbolic nodal analysis is derived in [23], where the characteristic equation is approached by (1.6), and the condition and frequency of oscillation are given by (1.7). By choosing Ry = Rp = 2kQ, R3 = R4 = 10kQ, the value of the frequencies of oscillation are shown in Fig. 1.11 as: f; =2.65 MHz (Dashed-line) with C; = Cp = 24 pF, fo = 6.29 MHz with C; = Cy = 6.46 pF (Dotted-line), and f; = 12 MHz (Solid line) with C; = C) = 0.1 pF.

Fig. 1.11 Time responses of the OTRA-based sinusoidal oscillator

Fig. 1.13 Addition of a norator P; at: (a) node 1, (b) node 2, and (c) between nodes | and 2 of the nullator O,

Fig. 1.12 Nullator-equivalent circuits to describe a VF

Fig. 1.16 Synthesis of the VFs from Fig. 1.14c, d

By combining the three VFs depicted in Fig. 1.17 with a simple CM, nine CFOAs arise. The VFs are labeled with capital letters A, B and C.

Fig. 1.18 Two VMs synthesized from the VFs in Fig. 1.17

Fig. 1.19 (a) Modeling a CM; (b) and (c) extra circuits for Jour; (d) codification of chromosome: 611669; (e) generic model of the CM 611669 [12]

Fig. 1.20 Combinations among two unity-gain cells [12]

Fig. 1.21 CFOAs synthesized by combining the VFs in Fig. 1.17 with a simple CM

1.4.1 Non-Dominated Sorting Genetic Algorithm IT (NSGAIT)

4.2 Multi-Objective Evolutionary Algorithm Based on Decomposition

Algorithm 3 Build spread of N weight vectors for m objectives

Table 1.5 Optimized performances for the CFOAs shown in Fig. 1.21

Fig. 2.2 Nullor models of active devices: (a) Ideal transistor (BJT). (b) Ideal op-amf

Fig. 2.5 Nullor model of other active building blocks. (a) Nullor model of an OTA. (b) Nullor model of a VF. (c) Nullor model of a CF

Fig. 2.6 OFA-based circuits (adapted from [17] © 1993 Springer). (a) V to I converter = GV (b) Floating gyrator (I; = G2 V2, bk = —G,V,) Fig. 2.7 A FTFN implementation using CCIIO. (a) FTFN. (b) A FTFN using two three-terminal nullors. (¢) FTFN using two CCIIO. (d) FTEN using two CFOAs

Fig. 2.8 An OMA©-based FTEN realization (adapted from [22] © 1994 IEEE)

Fig. 2.12 Conversion of GlC-based grounded impedance into FTFN-based floating impedance (a) Antoniou’s GIC-based grounded impedance (adapted from [26] © 1969 IEE). (b) The nullor model of the circuit of (a). (c) A floating version of the GIC resulting from the application of Theorem 2.1 [7]. (d) An FTFN-based floating generalized impedance as per the method first introduced in 1987 in [7, 13]. (e) An alternative generalized floating impedance using FTFNs (adapted from [30] © 1997 © 2000 Springer). (f) Another FTFN based generalized floating impedance simulation (adapted from [31] © 2001 Springer)

Fig. 2.14 (a—c) Method of transformation of a lossless grounded inductor into a FI using an FTFN or OFA [7, 13]. (d-f) Three other equivalent FIs having same value of realized inductance under the same condition of realization

Fig. 2.15 Conversion of an op-amp based single resistance controllable GI into FTFN-based FI of the same form: (a) Floating series RL, (b) floating parallel RL

Fig. 2.17 (a) A nullor model of the SRCO of Fig. 2.16. (b) An alternative nullor model of the same circuit

‘b” the configuration can realize fully differential CM summer. We now show that, is widely understood, nullors are indeed useful in realizing and unifying circuit structures using all such different kinds of active elements which can be modeled in erms of nullors. In the present case, the nullor-based configuration of Fig. 2.20 leads o a number of different practical implementations, three of which using CCII-, CCCII-+ and differential output OTA (DOTA) are shown in Fig. 2.21. It is worthwhile to mention that in all cases. the internal hardware of the to a number of different practical implementations, three of which using CCII-, CCCII+ and differential output OTA (DOTA) are shown in Fig. 2.21. It is worthwhile to mention that in all cases, the internal hardware of the employed building blocks can be easily modified to facilitate multiple and com- plementary outputs which should be useful in interconnecting two or more of such configurations as well as to provide feedback paths and summations as needed for either biquad realization or higher order filter designs. Alternatively, differential summer can also be realized by the nullor-based structure of Fig.2.21d and an exemplary configuration of a fully differential CM universal filter obtained in this manner is shown in Fig. 2.22 which realizes LP, BP, HP outputs where from HP and LP outputs can be combined to realize a band stop filter while HP and BP (inverting) can be combined to realize an all pass filter without requiring any component- matching conditions other than the equality of capacitors (which is prevalent in almost all earlier fully differential filter structures as well). A notable property of the circuit of Fig. 2.22 is that bandwidth and pole frequency can be orthogonally tuned by R; and R2 respectively: the gain is fixed at unity in all the cases. It has been shown elsewhere [54] that this approach can also be extended to the design of higher order filter.

The three transfer functions realized by the circuit of Fig. 2.22 are given by

Fig. 2.24 The synthesis of noninverting VCCS and its FET and CCII— realizations (adapted from [56] © 2005 Springer)

Fig. 2.26 Synthesis of an immittance inverter using nullors, MOSFET and CCIIs (In the CCIIs circuits, all three CCIIs could also be taken as CCII+ (adapted partly from [56] © 2005 Springer) Fig. 2.25 Synthesis of inverting VCCS using nullor MOSFET and CCs (adapted partly from [56] © 2005 Springer)

Fig. 3.1 Current feedback operational amplifier (a) the internal constituents, (b) bipolar imple- mentation of AD844 type CFOA (adapted from [9])

Fig. 3.3. Realization of non-inverting and inverting amplifiers using a CFOA

Fig. 3.4 SRCOs employing CFOAs (a) A single-CFOA-SRCO proposed by Senani and Singh (adapted from [12] © 1996 IET). (b) A dual-mode SRCO using both grounded capacitors proposed by Gupta and Senani (adapted from [14] © 1998 IET). (c) A fully uncoupled oscillator-cum- multifunction filter proposed by Bhaskar (adapted from [15] © 2003 Schiele and Schén)

Fig. 3.5 Generalized floating impedance converters/inverters using CFOAs proposed by Senani (adapted from [7] © 1998 Schiele and Schén)

Fig. 3.7 A multiple-input single output type universal biquad proposed by Nikoloudis and Psychalinos (adapted from [13] © 2010 Springer) Furthermore, the grounded forms of all the above-mentioned floating impedances can be obtained by grounding either port-1! or port-2. However, in the circuit of Fig. 3.6, with port-2 grounded, CFOA2 becomes redundant (y-terminal of CFOA3 and R; can be connected to ground directly) and as a consequence, the circuit can be simplified to have only three CFOAs while still being capable of realizing a grounded impedance:

Lastly, it must be mentioned that no such mixed-mode universal biquad configura- tion is possible or known with traditional VOAs. 6.5 Analog Divider Using CFOAs and MOSFETs

3.6.7 Design of Precision Rectifier Using CFOAs

3.6.8 Realization of Relaxation Oscillator/Waveform Generator A triangular/square wave generator can be made from a single CFOA as shown in Fig. 3.12 [27]. In this circuit, the CFOA behaves as a Schmitt trigger with the input— output characteristic shown in Fig. 3.12b where the threshold voltages are given by

It is worthwhile to point out that, apart from being employed as four terminal build- ing blocks in their own right, CFOAs have also been employed to realize other build- ing blocks in the analog circuits literature, for instance see [28-31]. Some important realizations have been summarized here in Fig. 3.13a—h, where input marked as “++” represents y-input and the one marked as “—” represents x-input of the CFOA.

Fig. 3.14 CFOA using forward and reverse bootstrapping proposed by Hayatleh-Tammam, Hart and Lidge (adapted from [33] © 2007 Taylor & Francis) Although there have been hundreds of publications on improving the design of current conveyors, surprisingly, in spite of the wide spread applications of CFOAs as exemplified here and in the references cited therein, there have been comparatively a very much smaller number of efforts [32-36] on improving the design of bipolar or CMOS CFOAs. In [32] Tammam, Hayatleh and Lidgey have presented a new CFOA architecture with significantly improved CMRR and gain accuracy. In [33] Hayatleh, Tammam, Hart and Lidgey have introduced a new CFOA architecture using forward and reverse bootstrapping (reproduced here in Fig. 3.14). This circuit is shown to offer increase of CMRR by about 46 dB with a reduction of input- referred-offset-voltage by a factor of two. References [34-36] have dealt with the design of improved CFOAs for CMOS technology. Out of these [35] deals with fully differential CFOA design reproduced here in Fig.3.15. A typical CMOS CFOA architecture from [36] provides improved performance in terms of low output resistance, high current drive and high slew rate capability as compared to a number of earlier designs. The continued efforts on improving the design of bipolar and CMOS CFOAs include a systematic synthesis of CFOAs advanced by Torres-Papaqui and Tlelo-Cuautle through manipulation of voltage followers and current followers [37]. It is hoped that continued work in this direction may result in better CFOAs in both bipolar and CMOS technologies in near future to facilitate the realization of numerous applications of CFOAs more efficiently and fruitfully.

Fig. 3.15 Schematic of the fully differential current feedback operational amplifier proposed by Soliman and Awad (adapted from [35] © Springer 2005)

Fig. 3.17 CMOS implementation of the DDCCFA (adapted from [40] © 2005 IET) Fig. 3.16 Conversion of CFOA-based SRCO into DVCFA-based GC-SRCO as proposed by Gunnes and Toker (adapted from [39] © 2002 Elsevier)

Fig. 4.1 (a) Nullator. (b) Norator. (c) Voltage mirror. (d) Current mirror circuits [13]. Despite the ability of nullor elements to describe many active building blocks, they fail to represent devices like the CCII+. Other passive elements like resistors are combined with nullators and norators in order to obtain the nullor representation of the CCII+ [6]. In order to avoid the use of passive elements in the nullor representation of any building block, additional pathological elements called mirror elements describing the voltage and current reversing actions are introduced in [11]. The voltage mirror (VM) shown in Fig. 4.1c, is a lossless two-port network element used to represent an ideal voltage reversing action and it is described by:

Fig. 4.2 (a) Class I three node generalized configuration. (b) Class II four-node configuration. (c) Class II four-node configuration. (d) Class IV five nodes generalized configuration

Table 4.1 Summary of the state matrix equation of the four classes of oscillators

Fig. 4.3 (a) Pathological realization of class I-type A oscillator. (b) Pathological realization of class I-type B oscillator

Fig. 4.4 (a) Pathological realization | of class II-type A oscillator. (b) CCU— and CCII+ oscillator circuit realizing Fig.4.4a [1, 16]. (c) Pathological realization 1 of class Il-type C oscillator. (d) CCH— and ICCII-— oscillator circuit realizing Fig. 4.4c [1]

By successive expansions the following NAM is obtained:

The above equation results in the class [V-type A pathological realization 1 shown in Fig. 4.7a. The corresponding realization using three CCIH— is shown in Fig. 4.7b. It should be noted that this new oscillator circuit can also be obtained from the unity gain band-pass filter introduced in [25] by connecting the band-pass output to the input port through a voltage follower to provide isolation to band-pass output port. Following similar steps as in the previous section a second pathological realiza- tion is obtained and is shown in Fig. 4.8a and the corresponding current convevor

Apply NAM expansion to (4.22) the following Y matrix is obtained:

Fig. 4.12 (a) Class [V-type B topology II pathological realization. (b) Two CCII one ICCH realization of Fig. 4.12a. (c) Class IV-type B topology II pathological realization 2

Fig. 5.5 The “switched” circuit obtained from Table 5.9 Fig. 5.4 Screenshot of the transfer function corresponding to Table5.9 obtained using [11]. (a) The product matrix coefficients. (b) The numerator coefficients. (c) The denominator coeffi- cients

Fig. 5.7 Screenshot of the transfer function corresponding to Table 5.10 obtained using [11]. (a) The numerator coefficients. (b) The denominator coefficients. (c) The product matrix coeffi- cients

Fig. 5.9 The “switched” circuit (according to Table 5.12) Fig. 5.8 Screenshot of the transfer function corresponding to Table 5.12 obtained using [11]. (a) The numerator coefficients. (b) The denominator coefficients. (c) The product matrix coeffi- cients

Fig. 5.11 The equivalent current conveyor based filter

Fig. 5.10 The nullor based circuit that is equivalent to the “switched” circuit shown in Fig. 5.10

Fig. 6.1 Block level partitioning of a modern wireless device

Fig. 6.2 A typical wireless radio using direct conversion architecture

Fig. 6.4 Effect of filtering and AGC on dynamic range requirements from Antenna to ADC

Fig. 6.5 Baseband input spectrum with digital adjacent channels

Fig. 6.6 Output power density and definitions of integrated power in the desired channel, residual N-+1 adjacent channel, and residual power in all undesired channels Table 6.1 Parameters used eee TOE) Oem eR cere

Fig. 6.8 Analog adjacent channels with single analog carrier per channel 6.2.2.2 Residual Undesired Power from Analog Adjacent Channels

Fig. 6.9 Residual dynamic range for the analog adjacent channel

Fig. 6.10 Estimated ADC Power consumption (for 4 MHz signal bandwidth) based on the data in [11]

Table 6.2 Pole-zero placement for baseband inverse chebyshev approximation

Fig. 6.11 Analog baseband architecture 8'" order Low Pass Inverse Chebyshev Approximation (3/4 MHz bandwidth setting)

where Tee is the input referred noise density of the amplifier. The first term repre- sents the noise contribution from R; and R4; the second term represents the noise contribution from R3 = mR; and the third term represents the noise contribution from the amplifier. Parameters w, and Q- are output spot noise spectral density for the filter is

Fig. 6.13 Variation of integrated noise for a given total capacitance budget with varying resistor ‘atio

Fig. 6.14 Switched-capacitor biquad implementation (single-ended structure shown)

Fig. 6.15 Chip Micrograph of the UHF receiver To measure the ResidualDR, input power spread over two channels (generatec using two signal generators and a power combiner) is injected into the filter: A digital channel is generated using 64-QAM modulation employing Root-Nyquis' (RNYQ) pulse shape with appropriately scaled symbol rate to generate a flat PSD through-out the channel, while an analog channel is generated using a single carrier. The output power levels between the desired and the undesired channels is suitably adjusted to vary the ACyp values to obtain a wide range of measurements. Filtered PSD is measured at both the continuous- and discrete-time outputs. Figure 6.17 shows the measured input and filtered outputs with digitally modulated desired

Fig. 6.16 Measured baseband transfer function (a) continuous-time section (b) continuous- and discrete-time sections together

“By definition, equivalent integrated power of the (NV + 1) channel is (AC +3)gpg higher than the integrated power of the desired channel due to 2X integrating bandwidth of (N + 1) channel

Fig. 6.17 Measured filtered output PSD with combined input of two 64-QAM digital modulated channels (desired and N+1 adjacent) with ACyg = 30 dB Table 6.3 Measured ResidualDR with near (N + 1) and far (N + 3) blockers

Table 6.4 Experimental results with comparison to previous work

Fig. 6.18 Measured linearity performance using two-tone measurement results for the system En ee Re SE TNT EE The power consumption and the area metrics indicated for this work in Table 6.4 do not include the frequency synthesizer, and quadrature generator. The RF front end and baseband blocks consume 58 and 52mW from a 1.8V_ supply respectively. The digital clock tree to drive the SC filter switches consumes 10mW from a 2.5 V digital supply. Compared to the previously published UHF receiver solutions, this work implemented in CMOS process offers competitive performance.

Fig. 7.1 Multi-standard LNA: (a) Based on switchable resonant tank [11] and (b) With an external switchable capacitor

with ggsnj being the small signal drain-source conductance of M,; c is the correlation factor, which has a value of —0.3957 and —0.5j for long and short channel transistors respectively [17]; o is a technology parameter used to model the gate noise; and y is a technology parameter ranging from 2 / 3 for long-channel transistors to 2—3 for short-channel transistors [19]. Se; | a er a oo | ef |e: es, i Ce a. 7 fs. 2s Si i

Table 7.1 Design requirements for the inductively degenerated common- source two-stage LNA

4INZAS LU HAVE INTIN 1LUdUs [ILUTJI]. Note that a cascode stage could be used to increase the voltage gain compared vith the single stage with inductively source degeneration. However, cascode stages imit the resonant frequency tuning in terms of voltage gain. Such a trade-off is llustrated in Fig. 7.7, where an inductively source degeneration (ISD) and a cascode vith an inductively source degeneration (CISD) LNAs are compared respectively, onsidering a variation of g,,.,1;. Note that a lower tuning range is obtained by the “ISD topology. For that reason, a simple input stage was considered in this design.

Fig. 7.7 Dependency of the voltage gain in CISD and ISD LNAs due to gin) variation The real part of Zpcsa, given by (2manFLs/CgsnnF), must be set equal to the RF source resistance, Rpp, in the band of interest—1.85—2.48 GHz in this design. In this prototype, as the LNA is fully integrated as a stand-alone circuit, a termination of 50Q is needed not only at the input terminal but also at the output one, as will be shown in the next section. AM. 8 ee: meanrlenmeaeam nl en FRA. Sea anktvie<csead Tex: zrawann, the ewccemmnnmns

Noise factor, F, can be easily obtained by replacing (7.31) and (7.32) in th following expression [43]:

Fig. 7.12 LNA layout implemented in 90-nm CMOS technology

Fig. 7.13 Cross-section of the physical structure for: (a) Inductors and (b) Varactors

metal-metal capacitors. MOS varactors shown in Fig. 7.13b are formed by source- drain connection in a MOS transistor. All PADs are Electrostatic Discharged (ESD) protected. The die area, including PADs, is 1.8mm?, with the core occupying 1.0mm’. As usual, a significant portion of this area corresponds to integrated inductors. However, in this circuit, and contrary to most reported multi-standard LNAs, the number of inductors is not increased as compared to the mono-standard case, with the subsequent area saving.

Fig. 7.15 Simulation of NF and S-parameters: (a) NF (b) S21 (c) Sy; and (d) S22

Fig. 7.16 (a) Chip microphotograph and (b) Test PCB 7.3.7 Experimental Results

Table 7.4 Comparison with the state-of-the-art reconfigurable CMOS LNAs

Fig. 8.2. The static latch: cross-coupled inverters (a), the characteristic (b), small-signal equivalent circuit (c), voltage-time dependence (d)

Fig. 8.3 Offset and hysteresis of a comparator, which is affected by noise

Fig. 8.4 Occurrence of bit errors due to the influence of noise [12]

Fig. 8.5 Cross section of a typical deep-sub-micron (DSM) CMOS process The delay time of a clocked regenerative comparator is the minimum time uration from beginning of the comparison phase (reset is released when the ppropriate clock edge reaches typically 50% of Vpp) till a valid logical voltage evel is available at the output. Another definition is the minimum time duration rom beginning of the comparison phase (reset is released when the appropriate lock edge reaches typically 50% of Vpp) till one output node reaches the half upply voltage Vop/2. A further important parameter to characterize a clocked regenerative comparator

Fig. 8.6 Two comparators, which are often described in literature: latch-type voltage sense amplifier [17, 18] (a), double-tail latch-type voltage sense amplifier [19] (b)

Fig. 8.9 Block diagram of the test chip containing the comparator to be measured Fig. 8.8 Transient simulation of the comparator at a supply voltage of Vcomp = 0.5 V and 500 MHz clock frequency: TBIAS = 0.4 V (a) CINP —CINN = £25mV (b) CINP—CINN = +100mV

Fig. 8.10 Schematic of the adapter and block diagram of the transfer stage

Fig. 8.11 Layout plot and microphotograph of the test chip (1.38 x 1.39 mm?) with the comparator

Fig. 8.12 BER measurements: On the right side the measured BER versus the bias level at CINP is shown and on the J/eft side BER measurements versus the amplitude at the optimal operating point at different parameters are shown

Fig. 8.13 Measured transient behavior at 6 GHz

Fig. 8.14 Circuit of the comparator with the modified latch

Fig. 8.16 Block diagram of the test chip including the comparator

Fig. 8.17 BER measurements: On the /eft side the measured BER versus the bias level at CINP is shown and on the right side BER measurements versus the amplitude nearby the optimal operating point at different parameters are shown

Fig. 9.1 An overview of wireless body area network (WBAN) based patient monitoring system

Table 9.1 Top ten targets for wireless medicine 3 Applications of Biomedical Sensors

Fig. 9.3. Location of smart sensor within the eye [24]

manner, but only in the reverse direction, providing a feedback system within the eye. Figure 9.4 depicts the processing steps from external image reception to transmission to artificial retina prosthesis. A camera mounted on an eyeglass frame feeds its output to a DSP unit for data reduction and processing. The camera is combined with a laser pointer for automatic focusing. The DSP unit transmits the processed data via wireless transceiver system to the implanted chip in the eye for subsequent decoding. Figure 9.4 shows a wireless transceiver setup inside the human body, but not within retina.

Fig. 9.5 Components of a watchlike glucose monitor being developed by Cygnus Inc [23] the donated organs go unused as there is a very short window of time in which to transplant the organ before it becomes no longer viable. A better understanding of the condition of the organ could lengthen this window. Moreover, organ rejection after transplant is also a serious issue. Continuous monitoring of the patient after the transplant for symptoms of rejection is crucial. Biosensors can be employed for the monitoring of the condition of the donated organs as well as the symptoms of the rejection of the transplanted organs.

Fig. 9.6 Relationship between g,, and the drain current in different regions of operation [43] affect the internal components of the circuit. Another advantage of biasing the input pair transistors in W.I. is the reduction of the total noise of the system. In low frequency circuit design flicker-noise has a huge impact on circuit quality. In these circuits the flicker noise can be derived from the equation below [44]:

In analog/RF circuit the power consumption is proportional to the supply voltage and thus reducing the power supply can reduce the power consumption of the circuit. Lower supply voltage also reduces the electric field and improves the long term device reliability. However, lower supply voltage limits the dynamic range in analog circuit and offers reduced voltage headroom for the cascode structures. Therefore it is necessary to develop new techniques to obtain the same performance while using a nominal power supply voltage.

Fig. 9.10 Typical configurations of a current mirror with (a) gate-driven NMOS and (b) bulk- driven NMOS reducing the Vin below V,o. Figure 9.8 shows a basic configuration of a conventional gate-driven NMOS transistor (a) and bulk-driven NMOStransistor (b).The cross section of an N-channel MOSFET (P-substrate technology) is shown in Fig. 9.9. Unlike the conventional gate-driven MOSFETs, the bulk-driven ones operate very similar to JFETs [47]. Besides, the channel width is constant as long as the gate bias does not change. Therefore, the bulk-driven MOSFETs can operate as a depletion- mode device

Fig. 9.12 (a) Conventional NMOS cascode structure, (b) improved NMOS cascode with high output voltage swing indicating the aspect ratios of the MOSFETs. An additional current branch is needed in (b) to properly set the bias

Self-cascode technique shown in Fig.9.13a is developed to maintain a good output swing without requiring any additional biasing there by making this scheme a potentially good candidate for low voltage design. In this configuration, usually M2 has an aspect ratio of m times of that of MI ie., (W/L). = m (W/L), (usually for optimal operation, m is set much larger than 1). Under this scenario. these two transistors can be considered as a composite transistor M3 as shown in Fig.9.13b. This new transistor has much larger effective channel length while having a much lower effective output conductance (which results in much higher output resistance) [50]. Then, the effective transconductance of M3 can be expressed as:

Fig. 9.14 A self-cascode differential VCO for high frequency application [51]

Fig. 9.15 A typical floating gate N-MOSFET (a) layout, (b) schematic symbol, and (c) equivalent circuit with parasitic capacitance noted [58]

Fig. 9.16 Typical configurations of (a) current mirror, (b) differential pair with two-input gate- floating N-MOSFETs

An example of current signal processing using a three-electrode potentiostat is shown in Fig.9.18 [61]. This potentiostat consists of three electrodes: working electrode (WE), counter electrode (CE) and reference electrode (RE). To measure the physical parameters such as glucose, lactate, CO and pH, a constant difference potential should be provided across RE and WE. Based on the concentration of the analyte solution, the applied voltage across these electrodes can initiate chemical reaction which generates electrons that can be collected in CE. The collected current from this electrode needs to be processed using a signal processing unit. A current mirror is used to generate a copy of the current collected by CE. The mirrared cinrrent gqeneratec 49 waAltagea acrncee the reacictar R which ic nrannartinnal tn

Fig. 9.21 Typical power-conditioning module for systems with inductive link power The circuit consists of: (1) a bandgap voltage reference, (2) an error amplifier, (3) a pass element, and (4) a voltage divider. The bandgap outputs a very stable DC voltage, Vier, Which is immune to supply and temperature variation, but it cannot directly drive the load. The error amplifier Al is used to monitor the changes in the output voltage and to generate a drive voltage for the pass element to adjust the current with a negative feedback scheme to stabilize the output voltage. A conventional operational amplifier can be employed as the error amplifier. The pass element typically employs a MOSFET or a composite structure to provide the output stage for the load. Usually the transistor size is large to handle the required output current. Besides, it is also very important in terms of frequency compensation for the entire negative feedback loop. A voltage divider can be designed to obtain the desired output voltage. From the schematic, one can easily derive the output voltage expression:

10.2 Analog and Semi-digital Sensor Conditioning Circuits The available types of sensor readouts can be broadly classified into analog and semi-digital. Traditionally, the digitized outputs were obtained by employing analog sensor readout signals followed by analog-to-digital converters (ADC), as shown in Fig. 10.2. This topology, which uses an ADC, not only increases the complexity and power consumption but also introduces extra noise. In order to address these issues, semi-digital solutions such as pulse-frequency modulation (PFM) [3] or pulse-width modulation (PWM) [4] have been investigated. These kind of readouts represent analog quantities using only digitized signal levels. This is achieved by encoding the information in the time or frequency domain, rather than the analog voltage or current domain as in analog readouts. This topology is shown in Fig. 10.3. Its rail- to-rail voltage swing also provide the advantage of robustness against environment noise. This alternative method eliminates the traditional ADC and reduces the power consumption significantly. In addition, the dynamic range in semi-digital readouts

Fig. 10.4 The block diagram of resistive and capacitive sensor readout configurations

Assuming the input impedance of the comparators is large and the input clock transits quickly, a simple capacitance charging and discharging model can be utilized to analyze the behavior of the circuit during the low and high portion of the input clock. The ideal response of the circuit without a reset block is shown in Fig. 10.5. Neglecting the delay of the comparators, which does not impact the circuit response assuming both comparators have identical delay, we observe that the waveform on O1 is equal to V1 and depending on the excitation signal transition, node V2 either charges or discharges with an RC time constant. In this design, the switching threshold of the comparator is set to 0.5Vpp. The outputs of the

Fig. 10.8 Capacitance dynamic range with different reference resistors

Fig. 10.9 Resistance dynamic range with different reference resistors

Fig. 10.11 Conceptual diagram of the additive noise voltage Fig. 10.10 Conceptual diagram of signal up-conversion operation

VECAUSE OL UIE Teil SCHSIUVILY LO LUO THOS’, In the following noise analysis, we assume that the additive noise is a stationary white Gaussian random variable with standard deviation oy. If we denote the noise AS Uy, then it can be expressed as u, ~ N(0, 07). Thus, the output pulse width 7,,, can be expressed as discrete time random processes that depend on noise uy. By using (10.17) and (10.19), assuming y = In(0.5Vpp — uy), the variance of jitter, oF, san be derived according to the variance of noise voltage, o2, as:

Fig. 10.13 Effect of jitter at different stages. (a) Clock signal after the comparator. (b) Signal at the RC charging node. (c) Signal after the comparator. (d) Output signal of the phase detector (XOR) Fig. 10.12 Conceptual diagram of the noise sources in readout system

Fig. 10.14 Frequency spectrum measurement Fig. 10.15 RMS jitter on rising and falling edges of the PWM output signal versus sensing capacitance

implantable and mobile applications [19-21]. A low-complexity up-conversion process is utilized in order to address flicker noise. Sensor signal is up-converted utilizing AC excitation before it is contaminated by flicker noise. In addition, the example makes an effective use of the pulse period to provide an improvement to

Table 10.1 Performance comparison ~ Commercial universal transducer interface for resistive bridges 25-Q-10-kQ with maximum imbalance +4% or +0.25% ’ The maximum resistance and capacitance are calculated using (10.3) and the measured output pulse widths, likewise the minimum resistance and capacitanc are calculated using (10.3) and the measured jitters

Setting u = 4*/dp and w = 4»/dp and interchanging the order of derivatives, we obtain Y: RNa+! _, RMa exists so that yo = Y(Xo0,o). In general, this is possible for any (x*,y*,t*) such that g,(x*,y*,f*) is invertible, thus allowing to obtain the sensitivity of y with respect to a parameter p from the sensitivity of x with respect to the same parameter. In fact, assuming that (x,(t),ys(t)) is the solution of (11.1) for t € [f, t]. the sensitivity of this solution with respect to a system parameter p € R can be computed from (11.1) as

h(x,t) is adopted to verify whether or not a generic point x(t) belongs to either . R, or Ro. More specifically

Fig. 11.2 Two different examples of two-dimensional “jumping” trajectories. In Fig. 11.2a both the differential variables x and the algebraic ones y are continuous since g undergoes no switch in correspondence with Asw(x,y,t1). On the contrary, in Fig. 11.2b, y- # yt since the algebraic constraint changes across hsw (x, y,t1)

Fig. 11.3. The generic architecture of an AMS circuit. The time variable ¢ is assumed, at least in principle, to be available at both sides of the circuit. In particular, in the digital part, both a clock signal tg and the continuous variable ¢ are available. Clock-time can trigger sequential events and the continuous variable can be used to store the value of ¢ at specific events if one is interested, for instance, in producing delayed digital outputs

Fig. 11.6 The schematic of the analog to digital converter

Fig. 11.7 The modulus of the spectra computed by the DSH based PAC analysis related to the analog conversion of one bit of the ADC (across the C2 capacitor) in Fig. 11.7a and to S&H (across the C, capacitor) in Fig. 11.7b. x-axis: frequency of the small signal applied to In; y-axis: magnitude of the components of the spectra in dB

Fig. 11.8 The power spectral density of total noise at the Qut node. The only considered sources of noise are the R1 and R2 resistors

Fig. 11.9 The schematic of the CLASS-D audio amplifier

controlled switches Mp and Mn. The models of these switches are such that Mn closes (its on resistance becomes equal to Ron) when the driving signal is larger than a given threshold while Mp closes when the driving signal is less than this threshold. The sawtooth waveform at node Pwm has a period of | us. The pulsed width modulated large signal (and power) is filtered by the LC filter composed of Lo and Co. The values of these elements have been chosen considering the impedance of the load (loudspeaker). The value of Rb has been chosen equal to 10Ra in order to have an input/output gain of the CLASS-D amplifier equal to +20dB. The amplifier has been driven at the In node by the Vin = 2sin(2710°r)

Fig. 11.11 CLASS-D amplifier: the modulus of the input/output transfer function in Fig. 11.1la and its phase in Fig. 11.11b

Fig. 12.1 Integrated spiral inductor: (a) Planar inductor pi-model, (b) Single metal layer inductor metal width variation Aw

Fig. 12.3 Process variables impact on inductor quality factor and inductance

Fig. 12.5 Effect of discretizing a continuous search space

design is 7%, the highest quality factor corresponds to an inductance deviation of only 0.4%. Higher values for Q are achieved only for a deviation larger than the 7% limit.

Fig. 12.7 Best design results obtained by the group of four swarms

global best solution its velocity approaches zero, and the particle will, eventually, stop moving. As a result, the particle will converge to the best position found so far, without granting that the true global optimum has been reached. In fact it may not even correspond to a local optimum. XETW. ....... gh ..f... ... .1..J4. sli s2zihe. 2k. * LI CONHALA 1L......] ..1......,’*al.... *. .tu1.. 1.

To deal with the dual-objective problem two different swarms are used. One of them aims to minimize the inductance deviation. The goal of the second swarm is to maximize the quality factor, constrained to a 5% maximum inductance deviation. Each swarm is composed of two particles and runs for four iterations. The algorithm parameters are & = 0.75 and cy = cz = 0.3. The local optima found by the two swarms are merged in Fig. 12.9. Table 12.4

Fig. 12.10 (a) Local optima. (b) Worst-case robustness results for the local optima

Fig. 12.11 Location on the local optima plane (a) of the worst-case non-dominated solutions (b)

Fig. 13.1 Topologies of translinear circuits: (a) alternating, (b) balanced, and (c) electronically simulated I Maes Ser Se ee ee a a See ee ee Re Beene eee Three basic configurations for forming TL loops can be implemented: (1) alter- nating cell (elements with different type of transistor are interconnected one to one in the TL), (2) balanced cell or stacked cell (elements with similar type of transistor are interconnected first, after the rest of transistors of the other type are joined to the TL) or (3) electronically simulated o tunable cell (elements are operated by adjusting the gate voltages making possible to cancel the possible circuit nonlinearity caused by the input voltages). These topologies are shown in Fig. 13.1 for n-channel MOS transistors, using a TL of four transistors for the case of Fig. 13.la, and Fig. 13. 1b. For the case of Fig. 13.1c; a floating gate realization is shown, since with these devices the extra circuitry to force the gate voltages is notably reduced.

where j is the number of translinear elements, and S = W/L. TL loops in strong inversion are used to form translinear loops or translinear circuits in RMS-DC converters [3, 17], chaotic analog noise generators [5], a differentiator circuit [14], a flipped voltage followers (geometric-mean circuits and squarer/divider circuits) [16], square-root domain filters [18, 21-23], log domain filters [24, 25, 27, 28, 32, 40], integrators [26], oscillators [29], square-root circuits [33], squarer/dividers [33], and multiplier/divider circuits [33,39]. Most of above references uses four transistors single loops for the cell implementation operating in Class-A, however in [3] multicoupled cells are proposed operating in Class- AB. These last procedure has no be generalized, and can be a challenge for a new research.

Fig. 13.3. Translinear circuits based on FGMOS transistors

The capacitor current is equal to the current generated by the divider, then Equations (13.18) and (13.20) can be related by means of the chain rule as follows:

Integrated Circuits for Analog Signal Processing Esteban Tlelo-Cuautle Editor Integrated Circuits for Analog Signal Processing 123 Editor Esteban Tlelo-Cuautle INAOE Luis Enrique Erro No. 1. Tonantzintla Mexico ISBN 978-1-4614-1382-0 ISBN 978-1-4614-1383-7 (eBook) DOI 10.1007/978-1-4614-1383-7 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2012938259 © Springer Science+Business Media New York 2013 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Preface Analog integrated circuits encounter applications in signal amplification, filtering, data acquisition systems, sensor conditioning, biomedical implants, actuator con- ditioning, oscillators, mixers, and so on. Those applications are possible, thanks to the availability of a huge plethora of active devices/elements, and thanks to the appropriate exploitation of their electrical characteristics. For instance, active devices can be classified according to the kind of signal (voltage/current) and port characteristics. Some examples are: voltage operational amplifier, current opera- tional amplifier, operational transconductance amplifier, operational transresistance amplifier, current conveyor, current differencing transconductance amplifier, and so on. In this manner, this book collects recent theories and design methods and applications of active devices/elements (working in voltage-, current-, and/or mixed- mode) and summarizes challenges imposed by the nanometer technology. The book consists of 13 chapters focused on: analysis, design, and optimization of active devices; nullors, their bipolar and CMOS implementations and applications in analog circuit synthesis and design; current feedback op-amps, their variants, in- tegratable implementations and applications in analog signal processing; generation of grounded capacitors minimumcomponent oscillators; active filter design using a two-graph based transformation technique; analog baseband filter design considera- tions for wireless receivers; flexible nanometer CMOS low-noise amplifiers for the next-generation software-defined-radio, mobile systems; clocked nanometer CMOS comparators; low-power electronics for biomedical sensors; sensor conditioning circuits; steady-state simulation of mixed analog/digital circuits; variability-aware optimization of RF integrated inductors in nanometer-scale technologies; and a survey on the static and dynamic translinear paradigm. The topics covered in this book are intended for people in academy and industry, as well as a key guidance for students and practitioners in the very wide field of analog integrated circuits. v Contents 1 Analysis, Design and Optimization of Active Devices . . . . . . . . . . . . . . . . . . 1 I. Guerra-G´omez, E. Tlelo-Cuautle, M.A. Duarte-Villase˜nor, and C. S´anchez-L´opez 2 Nullors, Their Bipolar and CMOS Implementations and Applications in Analog Circuit Synthesis and Design . . . . . . . . . . . . . 31 Raj Senani, A.K. Singh, Pragati Kumar, and R.K. Sharma 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations and Their Variants . . . . . . . . . . . . . . . . . . 61 R. Senani, D.R. Bhaskar, S.S. Gupta, and V.K. Singh 4 Generation of Grounded Capacitors Minimum Component Oscillators .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 85 Ahmed M. Soliman 5 Active Filter Design Using a Two-Graph Based Transformation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 107 Mourad Fakhfakh and Marian Pierzchała 6 Analog Baseband Filter Design Considerations for Wireless Receivers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 121 Jose Silva-Martinez and Raghavendra Kulkarni 7 Flexible Nanometer CMOS Low-Noise Amplifiers for the Next-Generation Software-Defined-Radio Mobile Systems . . . 145 Edwin C. Becerra-Alvarez, F. Sandoval-Ibarra, and J.M. de la Rosa 8 Clocked Nanometer CMOS Comparators .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 171 Bernhard Goll and Horst Zimmermann vii viii Contents 9 Low-Power Electronics for Biomedical Sensors . . . . .. . . . . . . . . . . . . . . . . . . . 193 Syed Kamrul Islam, Fahmida Shaheen Tulip, Kai Zhu, and Melika Roknsharifi 10 Sensor Conditioning Circuits. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 223 Julia Hsin-Lin Lu and Byunghoo Jung 11 Steady State Simulation of Mixed Analog/Digital Circuits . . . . . . . . . . . . 243 Federico Bizzarri, Angelo Brambilla, Giambattista Gruosso, and Giancarlo Storti Gajani 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale Technologies . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 271 Fernando Coito, Helena Fino, and Pedro Pereira 13 A Survey on the Static and Dynamic Translinear Paradigm . . . . . . . . . . 289 Rafael Vargas-Bernal and Carlos A. De La Cruz Blas Index . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 307 Contributors Edwin C. Becerra-Alvarez CUCEI, University of Guadalajara, Guadalajara, M´exico D. R. Bhaskar Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, India Federico Bizzarri Dipartimento di Elettronica e Informazione, Politecnico di Milano, pza. Leonardo da Vinci, Milano, Italy Angelo Brambilla Dipartimento di Elettronica e Informazione, Politecnico di Milano, pza. Leonardo da Vinci, Milano, Italy Fernando Coito DEE, Faculdade de Ciˆencias e Tecnologia, UNL, Caparica, Portugal Carlos A. De La Cruz Blas Departamento de Ingenier´ıa El´ectrica y Electr´onica, Universidad P´ublica de Navarra, Espa˜na, CP, Spain Jos´e M. de la Rosa IMSE-CNM, CSIC/University of Seville, Seville, Spain ˜ Miguel Aurelio Duarte Villasenor INAOE, Tonantzintla, Puebla, M´exico Mourad Fakhfakh University of Sfax, Sfax, Tunisia Helena Fino DEE, Faculdade de Ciˆencias e Tecnologia, UNL, Caparica, Portugal Giancarlo Storti Gajani Dipartimento di Elettronica e Informazione, Politecnico di Milano, pza. Leonardo da Vinci, Milano, Italy Bernhard Goll Vienna University of Technology, EMCE, Vienna, Austria Giambattista Gruosso Dipartimento di Elettronica e Informazione, Politecnico di Milano, pza. Leonardo da Vinci, Milano, Italy Ivick Guerra-G´omez INAOE, Tonantzintla, Puebla, Mexico S. S. Gupta Department of Industrial policy and promotion, Ministry of Commerce and Industry, New Delhi, Government of India ix x Contributors Julia Hsin-Lin Lu Purdue University, West Lafayette, IN, USA Byunghoo Jung Purdue University, West Lafayette, IN, USA Syed Kamrul Islam The University of Tennessee, Knoxville, TN, USA Raghavendra Kulkarni Texas A&M University, College Station, TX, USA Pragati Kumar Department of Electrical Engineering, Delhi Technological University, New Delhi, India Pedro Pereira DEE, Faculdade de Ciˆencias e Tecnologia, UNL, Caparica, Portugal Marian Pierzchala Wroclaw University of Technology, Wroclaw, Poland Melika Roknsharifi The University of Tennessee, Knoxville, TN, USA Carlos S´anchez-L´opez Universidad Aut´onoma de Tlaxcala, Tlaxcala, M´exico Federico Sandoval-Ibarra Cinvestav-Unidad Guadalajara, Guadalajara, M´exico Raj Senani Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India Fahmida Shaheen Tulip The University of Tennessee, Knoxville, TN, USA R. K. Sharma Department of Electronics and Communication Engineering, Ambedakar Institute of Technology, New Delhi, India Jose Silva-Martinez Texas A&M University, College Station, TX, USA A. K. Singh Department of Electronics and Communication Engineering, ITS Engineering College, Greater Noida, India V. K. Singh Department of Electronics Engineering, Institute of Engineering & Technology, Lucknow, UP, India A.M. Soliman Department of Electronics and Communication Engineering, Cairo University, Giza, Egypt Esteban Tlelo-Cuautle INAOE, Tonantzintla, Puebla, M´exico Rafael Vargas-Bernal Departamento de Ingenier´ıa en Materiales, Instituto Tecnol´ogico Superior de Irapuato, Guanajuato, M´exico Kai Zhu The University of Tennessee, Knoxville, TN, USA Horst Zimmermann Vienna University of Technology, EMCE, Vienna, Austria Chapter 1 Analysis, Design and Optimization of Active Devices ˜ I. Guerra-G´omez, E. Tlelo-Cuautle, M.A. Duarte-Villasenor, and C. S´anchez-L´opez 1.1 Introduction This chapter describes three computational techniques for the design automation of analog integrated circuits (ICs): Symbolic nodal analysis using the nullor concept and pathological elements, systematic design of active devices from a binary genetic encoding approach, and circuit biasing and sizing by applying evolutionary algorithms. Symbolic analysis techniques are very useful in generating analytical expressions of analog ICs. Their main characteristics can be identified by the kind of models they use. For instance, in the case of symbolic nodal analysis techniques, the use of active devices models based on pathological elements has demonstrated advantages in the formulation of small and sparse matrices [1]. In fact, using the pathological elements accompanied of passive circuit elements, e.g. resistances, one can model the behavior of almost all active devices, as already shown in [1–3]. It is also possible to include parasitic circuit elements into the models [4], and performances characteristics such as input and output impedances and gain [5]. In performing symbolic analysis one is interested in generating exact or approx- imated symbolic expressions [6]. However, using detailed models of active devices, the generated expressions can be too large, while by using compact models the expression may be very compact or reduced. In both cases, the generated symbolic expression approximates the exact response with some error tolerance [7, 8]. To generate compact expressions, a big circuit can be partitioned so that some blocks I. Guerra-G´omez () • E. Tlelo-Cuautle • M.A. Duarte-Villase˜nor INAOE, Tonantzintla, M´exico e-mail: [email protected]; [email protected]; [email protected] C. S´anchez-L´opez Universidad Aut´onoma de Tlaxcala, Tlaxcala, M´exico, e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 1 DOI 10.1007/978-1-4614-1383-7 1, © Springer Science+Business Media New York 2013 2 I. Guerra-G´omez et al. can be replaced by their dominant characteristics, and the symbolic analysis is accelerated by applying determinant decision diagrams (DDD) [9], and parallel DDD-based analysis [10]. For instance, in [5] is presented the symbolic nodal analysis of ICs containing current mirrors (CMs). The nullor-equivalent of the CM is very useful in formulating a reduced system of equations, as shown in the following section by performing symbolic nodal analysis of an all-pole third-order low-pass filter implemented with dual-output CMs [11]. Symbolic nodal analysis can also be applied in the synthesis of analog ICs through deriving performance-analytical- expressions of the active devices [6]. Recently, a binary genetic encoding (BGE) representation for the automatic synthesis of mixed-mode circuit topologies was introduced in [12]. The chromoso- mal representation of the four unity-gain cells was generated from nullator/norator descriptions, and the binary strings are represented by hexadecimal numbers in order to have a unique meaning when they are decoded to create transistor-based circuits. In Sect. 1.3, a summary on the synthesis of the voltage and current followers, and voltage and current mirros, is presented. The synthesis of more complex active devices is also described by combining and/or superimposing unity-gain cells. This kind of synthesis methodology is part of evolutionary electronics, because this research area involves applications of evolutionary computation in the domain of electronics. On this direction, analog design is much amenable for evolutionary techniques, because contrasting with the digital design, there is no solid set of design rules or procedures to automate circuit synthesis. For instance, analog synthesis begins by selecting a specific topology and its design is performed by finding parameter values (e.g. transistor lengths and widths). Furthermore, to have an idea among all the currently available design methodologies, a classification of design strategies developed by researchers in recent history over more than 20 years is presented in [13]. That way, yet there is a founded interest in the development of automatic techniques capable to find new circuit topologies and optimum component values. In general, the design of analog ICs requires the use of different kinds of active devices, as the ones summarized in [1,4,14]. Moreover, to improve the performances of those analog ICs, optimized active devices are required. In this manner, Sect. 1.4 summarizes the application of three evolutionary algorithms to compute the biases and sizes of analog ICs. That way, several active devices are optimized taking into account design constraints, and linking HSPICETM like circuit simulator to evaluate electrical characteristics. 1.2 Symbolic Nodal Analysis This section summarizes several models of active devices using the nullor concept and pathological elements [1, 4, 5]. Those models are used to derive symbolic expressions of analog ICs. 1 Analysis, Design and Optimization of Active Devices 3 Fig. 1.1 (a) Operational amplifier, (b) operational transconductance amplifier, and (c) negative- type second generation current conveyor modeled by using nullors 1.2.1 Modeling Active Devices Using Nullors and Pathological Elements The symbolic behavioral model generation of analog ICs can be found in [1, 4–6], where it is demonstrated that when using nullors and/or pathological elements, one not only can describe the dominant behavior of analog ICs, but also one can add or remove parasitic elements to generate models at different abstraction levels. The transfer relationships of the models are expressed by two kinds of signals: voltage and current. When the signals are voltages, the circuit works in voltage-mode, when they are currents, it works in current-mode, and when they are both voltage and current signals, it works in mixed-mode. Therefore, in general four transfer relationships are obtained. One mixed-mode active device was introduced in 1968 [15], it was named first- generation current conveyor (CCI). Nowadays, the current conveyor has evolved into three generations [4], basically composed of unity-gain cells [12], to drive voltages and currents. The models of several active devices by using controlled- sources are given in [14]. Those models have the drawback of generating systems of equations bigger than by using nullors or pathological elements [1]. For instance, Fig. 1.1 shows the ideal models of the operational amplifier (opamp), operational transconductance amplifier (OTA) and negative-type second generation current conveyor (CCII− [4]). These nullor equivalents are quite useful to derive simplified symbolic expressions. Lets us consider the active RC filter shown by Fig. 1.2. The modified nodal analysis (MNA) [6], generates one equation for each node plus one equation for each opamp, leading to a system of order 15. On the other hand, the symbolic nodal analysis using nullors generates a system equal to the number of nodes minus the number of nullors, leading to a system of order 6, as shown by (1.1). The symbolic transfer function is obtained by applying the symbolic technique presented in [1], and it is given by (1.2) [6]. 4 I. Guerra-G´omez et al. Fig. 1.2 RC filter Fig. 1.3 OTA-C filter ⎡ ⎤ ⎡ ⎤⎡ ⎤ vin 1 0 0 0 0 0 v1,2 ⎢ 0 ⎥ ⎢ −G1 −G5 − sC1 0 −G6 0 0 ⎥ ⎥ ⎢ v4 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎢ 0 ⎥ ⎢ 0 −G4 −G7 0 0 0 ⎥ ⎢ v6 ⎥ ⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥“⎢ (1.1) ⎢ 0 ⎥ ⎢ 0 0 −G8 −sC2 0 0 ⎥ ⎢ v8 ⎥ ⎥⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎣ 0 ⎦ ⎣ 0 0 0 −G9 G9 + G10 0 ⎦ ⎣ v9,10 ⎦ 0 −G2 −G3 0 0 G2 + G3 + G11 −G11 v11 −(G9 + G10)C1G2C2G7s2 + ((G1G3 − G2G5)(G9 + G10)) vout C2G7s − G4G8(G9G1(G2 + G3 + G11) + G2G6(G9 + G10)) “ . (1.2) vin G11(G9 + G10)(G6G8G4 + sC2G7G5 + s2C2G7C1) The OTA-C filters [16], can also be modeled using nullors. Lets us consider the one shown by Fig. 1.3, the system is given in [6], and the expression by (1.3). s2C1C2vC + sC1gm4vB + gm2gm5vA v4 “ . (1.3) s2C1C2 + sC1gm3 + gm2gm1 1 Analysis, Design and Optimization of Active Devices 5 Fig. 1.4 (a) CFOA description, and its (b) nullor-equivalent including Rx [4] Fig. 1.5 (a) Pathological-equivalent of the CFOA including dominant parasitics [1], and (b) Nullor-equivalent of the multiple-outputs current mirror including input impedance and indepen- dent gain and output impedances [5] The current-feedback opamp (CFOA) is another active device quite useful in linear and nonlinear applications [17–20]. It has four ports as shown in Fig. 1.4a, and basically, it can be designed by cascading a positive-type second generation current conveyor (CCII+) with a voltage follower (VF) [12]. That way, its nullor- equivalent is shown in Fig. 1.4b [4]. Besides, by using the pathological CM element [21], a compact model can be derived, as shown in Fig. 1.5a [1], where the dominant parasitics are included. In a similar manner, other kinds of active devices, such as the current differencing buffered amplifier (CDBA) [22], operational transresistance amplifier (OTRA) [23], current operational amplifier (COA) [24], and the ones summarized in [14], can be modeled by using nullors and pathological elements, as already shown in [1, 4]. 1.2.2 Current-Mode Filter Based on Current Mirror Arrays The CM can be modeled as shown in Fig. 1.5b, including multiple-outputs, input impedance and independent gain and output impedance at each output current- path. To highlight its usefulness, lets us consider the active filter shown in Fig. 1.6. 6 I. Guerra-G´omez et al. Fig. 1.6 All-pole low-pass filter implemented with dual-output CMs [11] This filter can easily be simulated using hardware description languages [25], but it is necessary to generate the symbolic behavioral model including the gains of each CM (CM1-CM6). By applying symbolic nodal analysis [1], the admittance matrix is computed by (1.4). ⎡ ⎤ g1 + gi1 + go2a ⎢ +go3a + sC1 gi3 A3 a 0 0 gi2 A2 a 0 0 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎢ go2b + gi3 + sC2 ⎥ ⎥ ⎢ ⎢ 0 +go4a + go5a gi5 A5 a 0 gi2 A2 b gi4 A4 a 0 ⎥ ⎥ g3 + go6a + sC3 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎢ 0 0 +gi5 + go4b 0 0 gi4 A4 b gi6 A6 a ⎥ ⎥ gL ⎢ ⎥ ⎥. ⎢ ⎥ +go6b ⎢ ⎢ 0 0 0 0 0 gi6 A6 b ⎥ ⎢ ⎥ ⎢ ⎢ go1 ⎥ ⎥ gi1 A1 0 0 0 +gi2 0 0 ⎥ ⎢ ⎥ ⎢ ⎢ ⎥ ⎢ ⎢ go3b ⎥ ⎥ ⎢ ⎢ 0 gi3 A3 b 0 0 0 +gi4 0 ⎥ ⎥ ⎢ ⎥ ⎣ go5b ⎦ 0 0 gi5 A5 b 0 0 0 +gi6 (1.4) When the output impedances of the CMs are ideal and the gains unitary, the symbolic expression becomes, iout g6 “ 2 i 5 . (1.5) iin C2 gi C3 g1 + C2 gi g3C1 s + gi C3 + gi 5C1 + C2 gi 3 g3 g1 s 3 3 +gi 5 g1 + gi 5 g3 + C2 gi 3C3C1 s3 1 Analysis, Design and Optimization of Active Devices 7 Fig. 1.7 Three stages uncompensated low voltage amplifier Fig. 1.8 Nullor equivalent of Fig. 1.7 1.2.3 Symbolic Behavioral Modeling of Amplifiers and Oscillators Lets us consider the three stages uncompensated low-voltage amplifier shown in Fig. 1.7. Its nullor equivalent is given in Fig. 1.8. The nodal admittance matrix has an order 7×7 [7]. The exact symbolic transfer function is given in [26], which is too large, so that a further step should be performed to simplify large symbolic expressions [6]. If the low voltage amplifier is designed with standard CMOS IC technology, its gain performance comparison with respect to its behavioral model is shown in Fig. 1.9. The noise analysis of CMOS amplifiers using nullor-equivalents and DDDs is presented in [8]. 8 I. Guerra-G´omez et al. Fig. 1.9 Comparison between HSPICE and the derived symbolic expression [7] Fig. 1.10 (a) OTRAs-based oscillator, and (b) its nullor-equivalent [23] The symbolic behavioral modeling of sinusoidal oscillators is quite useful for design purposes. Lets us consider the oscillator composed of OTRAs, as shown in Fig. 1.10. The system of equations by applying symbolic nodal analysis is derived in [23], where the characteristic equation is approached by (1.6), and the condition and frequency of oscillation are given by (1.7). By choosing R1 “ R2 “ 2 kΩ , R3 “ R4 “ 10 kΩ , the value of the frequencies of oscillation are shown in Fig. 1.11 as: f1 “2.65 MHz (Dashed-line) with C1 “ C2 “ 24 pF, f2 “ 6.29 MHz with C1 “ C2 “ 6.46 pF (Dotted-line), and f3 “ 12 MHz (Solid line) with C1 “ C2 “ 0.1 pF. 1 Analysis, Design and Optimization of Active Devices 9 Fig. 1.11 Time responses of the OTRA-based sinusoidal oscillator The parasitic capacitances are approximated to Cm1 “ Cm2 “ 6.46 pF. From Fig. 1.11 one can observe that the maximum frequency of oscillation ( f3 “ 12 MHz) is limited by Cm1,2 “ CZ2 . 2 1 1 1 1 s + − s+ . (1.6) C2 + Cm2 Rs R4 R1 R2 (C1 + Cm1 )(C2 + Cm2 ) 1 C.O. : R3 “ R4 , ωo “ a . (1.7) R1 R2 (C1 + Cm1 )(C2 + Cm2 ) 1.3 Systematic Design of Active Devices In the field of analog CAD, recent developments on the computational synthesis of analog ICs are given in [13]. Another recent technique is given in [12], where the VF is evolved to a voltage mirror (VM), and the dual topology of the VF leads us to design a current follower (CF). These are three unity-gain cells, and the fourth one is the CM. In summary, the computational synthesis of the VF includes [27]: generation of the small-signal circuitry, addition of the bias circuitry, replacement of nullator- norator pairs by transistors, and replacement of current biases by CMs. That is, since 10 I. Guerra-G´omez et al. a b c Fig. 1.12 Nullator-equivalent circuits to describe a VF Fig. 1.13 Addition of a norator P1 at: (a) node 1, (b) node 2, and (c) between nodes 1 and 2 of the nullator O1 the voltage across a nullator is zero [1], the VF is modeled as shown by Fig. 1.12. A norator is joined to each nullator to form nullator-norator joined-pairs, as shown by Fig. 1.13. The combinations for the descriptions in Fig. 1.12 are given in [12]. The bias circuitry is generated by addition of DC voltage and current bias levels to each nullator-norator joined-pair. That way, global DC voltage sources (VDD and VSS) are added, and ideal DC current sources are added to each norator Pi , as shown by Fig. 1.14. Besides, several bias sources can be eliminated as shown in [12, 27]. Each nullator-norator joined-pair (Oi -Pi ) is replaced by a MOSFET, where the joined terminals are associated to the source, and the other terminals of the nullator and norator, are associated to the gate and drain, as shown by Fig. 1.15. The kind of MOSFET, i.e. channel N or P, is determined by the direction of the current biases from VDD to VSS. In the same manner, an ideal current source is replaced by either a CMOS current mirror or a single MOSFET, as shown by Fig. 1.15. For instance, the biased circuits shown by Fig. 1.14c, d, are synthesized in Fig. 1.16 [27]. One can note that the VF topology in Fig. 1.16e is the flipped VF [28]. Figure 1.17 shows three well-known CMOS VFs. They can be evolved to design VMs, as the ones shown in Fig. 1.18, where the VF topologies for Fig. 1.17a, b are embedded into topologies Fig. 1.18a, b, respectively [12]. 1.3.1 Computational Synthesis of CMs The synthesis of a CM begins by using four nullators (O) and four norators (P), as shown by Fig. 1.19a. Each gate (G1, G2, G3, G4) in Fig. 1.19a can be connected 1 Analysis, Design and Optimization of Active Devices 11 a b c VDD VDD VDD Ibias1 Ibias1 Ibias1 O1 O1 1 2 3 1 2 P1 P1 P1 O1 1 2 3 3 Ibias2 Ibias2 Ibias2 VSS VSS VSS d e f VDD VDD VDD Ibias1 Ibias1 Ibias1 P1 P1 3 P1 1 2 1 2 O1 1 2 O1 O1 Ibias2 Ibias2 Ibias2 VSS VSS VSS Fig. 1.14 Addition of current biases to Fig. 1.13 D D D D G,D G S G S S S Fig. 1.15 Synthesis of the nullor by a MOSFET, and of a current source by a CM to nodes: A, B, C, D, VBIAS , Vdd or to an extra node (NG1, NG2, NG3, NG4) who is also used to add level shifters. The chromosomal representation consists of three genes [12]: genBias, genIO, and genLS. Lets us consider the chromosome 611669. Its BGE is shown in Fig. 1.19d. Figure 1.19e shows its generic description. Six synthesized CMs are shown in Table 1.1. 12 I. Guerra-G´omez et al. a b c VDD VDD VDD Ibias1 Ibias1 2 3 1 1 M1 1 M1 M1 2 2 3 Ibias2 Ibias2 Ibias2 VSS VSS VSS d e f VDD VDD VDD Mcm1 Mbias1 Mcm1 Mbias1 4 2 4 3 1 Iref Iref M1 1 1 M1 M1 2 2 3 5 3 Iref Mcm2 Mbias2 Mbias2 Mcm2 Mbias2 VSS VSS VSS Fig. 1.16 Synthesis of the VFs from Fig. 1.14c, d 1.3.2 Computational Synthesis of Mixed-Mode Active Devices The four unity-gain cells find applications in filter and oscillator design [29–31]. Furthermore, the interconnection or superimposing of two or more of them [12], leads us to create known or new active devices. For instance, several combinations among two unity-gain cells are shown in Fig. 1.20. From Fig. 1.20, the negative and positive types second generation current convey- ors (CCII−/+) [4], are generated by Figs. 1.20e, f, and their inverting realizations (ICCII−/+) by Fig. 1.20g, h. Other topologies like the OTRA, CBDA and inverting current conveyors can be synthesized by augmenting the interconnection strategies from [12]. For example, the superimposing of Fig. 1.20f, k generates the CFOA, i.e., it is the connection of three blocks VF-CM-VF, or equivalently, the CCII+ in cascade connection with a VF [4]. 1 Analysis, Design and Optimization of Active Devices 13 Vdd Vdd a b MA2 MA1 MA2 MA3 MA1 MA3 Iref Iref M1 M1 M2 Vin M2 Vout Vin Vout M3 M4 M3 M4 MB1 MB2 MB3 MB4 MB1 MB2 MB3 MB4 Vss Vss c Vdd MA1 MA2 MA3 Iref M2 Vin M3 Vout M1 M4 MB2 MB4 MB1 MB2 Vss Fig. 1.17 Three VFs already synthesized in [27] By combining the three VFs depicted in Fig. 1.17 with a simple CM, nine CFOAs arise. The VFs are labeled with capital letters A, B and C. 1.4 Circuit Optimization The biasing and sizing of analog ICs is a challenge in the development of electronic design automation tools [26]. Multi-objective evolutionary algorithms have demonstrated their usefulness in generating suitable/feasible solutions [32–34]. In this manner, we summarize three evolutionary algorithms for the multi-objective optimization of the nine CFOA-topologies synthesized in Fig. 1.21. A multi-objective optimization problem (MOP) can formally be defined as the problem of finding the vector: x “ [x1 , x2 , . . . , xn ]T , satisfying k inequality constraints: gi (x) < 0; for i “ 1, 2, . . . k 14 I. Guerra-G´omez et al. a Vdd MA1 MA2 MA MC MA3 Iref M2 M4 Vout M1 M3 Vin MB MB1 MB2 MB3 MB4 Vss b Vdd MC MA1 MA2 MA3 MA Iref M1 M2 Vout M3 M4 Vin MB MB1 MB2 MB3 MB4 Vss Fig. 1.18 Two VMs synthesized from the VFs in Fig. 1.17 the p equality constraints h j (x) “ 0; for j “ 1, 2, . . . p and minimizing the vector function f : Rn → Rm f(x) “ [ f1 (x), f2 (x), . . . , fm (x)]T . 1 Analysis, Design and Optimization of Active Devices 15 Fig. 1.19 (a) Modeling a CM; (b) and (c) extra circuits for IOUT ; (d) codification of chromosome: 611669; (e) generic model of the CM 611669 [12] The goal is focused on determining from the set S, all vectors (points) satisfying the constraints that yield the optimum values for all the m objective functions simultaneously. The constraints define the feasible region S, and any point x in the feasible region is called a feasible point. Pareto dominance: A vector u ∈ Rm is said to dominate a vector v ∈ Rm , u ≺ v, if and only if u is partially less than v, i.e., ∀i ∈ {1, . . . m}, ui ≤ vi ∧ ∃i ∈ {1, . . . m}: ui < vi , (assuming minimization). One solution dominates another one when it is strictly better in at least one objective, and not worse in any of them. Formal definition of Pareto optimality: A solution xu ∈ S (where S is the feasible region) is said to be Pareto optimal if and only if there is no xv ∈ S for which v “ f(xv ) ∈ Rm dominates u “ f(xu ) ∈ Rm , where m is the number of objectives. This definition says that xu is Pareto optimal if there exists no feasible vector xv which would decrease some objective without causing a simultaneous increase in at least one another objective (assuming minimization). This definition does 16 I. Guerra-G´omez et al. Table 1.1 Six synthesized CMs CM chromosome 611669 1269180 43072028 69593766 90642412 116098801 Gain 1.001 1.000 1.002 0.997 1.002 0.999 BW MHz 195 196 36.6 106 546 86 Rin KΩ 4.88 8.16 5.91 74 1.03 0.029 Rout KΩ 67000 4e7 12.3 7.37 7.45 920 Offset nA 8 0.02 0 (in 60 µA) 652 7840 15 SettlingT ns 2.03 1.85 3.14 1.26 0.39 – Slew Rate A/ms 6.25 6.30 2.62 12.97 19.88 – Dynamic −10 −10 45 −0.75 −10 −10 Range µA to 270 to 61 to 80 to 50 to 210 to 5,000 Fig. 1.20 Combinations among two unity-gain cells [12] 1 Analysis, Design and Optimization of Active Devices 17 a CFOAAA b CFOAAB c CFOAAC Fig. 1.21 CFOAs synthesized by combining the VFs in Fig. 1.17 with a simple CM not provide us a single solution (in decision variable space), but a set of so- lutions which form the so-called Pareto Optimal Set or Pareto Front. All the vectors that correspond to the solutions included in the Pareto Front are non- dominated. 18 I. Guerra-G´omez et al. d CFOABA e CFOABB f CFOABC Fig. 1.21 (continued) 1 Analysis, Design and Optimization of Active Devices 19 g CFOACA h CFOACB i CFOACC Fig. 1.21 (continued) 20 I. Guerra-G´omez et al. Algorithm 1 NSGA-II Algorithm 1: P0 “ random, Q0 “ random 2: t“0 3: Pt+1 “ 0/ and i “ 1 4: repeat 5: Rt “ Pt ∪ Qt 6: F= fast-non-dominated-sort(Rt ) 7: crowding-distance-assignment(Fi ) 8: repeat 9: Pt+1 “ Pt+1 ∪ Fi 10: i “ i+1 11: until |Pt+1 | + |Fi | ≤ N 12: Sort(Fi ,≺n ) 13: Pt+1 “ Pt+1 ∪ Fi [1 : (N − |Pt+1|)] 14: Qt+1 “ make-new-pop(Pt+1 ) 15: until stop criteria 1.4.1 Non-Dominated Sorting Genetic Algorithm II (NSGAII) This is an improved version of the (NSGA) by including elitism and was named as NSGA-II [35]. The NSGA-II procedure is summarized in Algorithm 1, and it approximates the Pareto Front of a MOP by sorting and ranking all solutions in order to choose the better solutions to make a new offspring. This means, by ranking all the population in different Pareto subfronts that it will be possible to know which solutions show better performance. In this algorithm is contemplated a way to choose the best solution between two solutions in the same subfront preserving diversity, in this form it is possible to select the best part of a population without losing diversity. NSGA-II is based on two main procedures: Fast Nondominated Sort and Crowding Distance Assignment. These two procedures ensure elitism and it is possible to add constraints to ensure that the solutions are feasible [34, 35]. At the begining it is necessary to randomly initialize the parameters and start by generating two populations (Po and Qo ) each one of size N, from random values into a feasible region. The NSGA-II procedure in each generation consists of rebuilding the current population (Rt ) from the two original populations (Pt and Qt ) then the new size of current population will be 2N. Now, through a nondominated sorting all solutions in Rt are ranked, and classified in a family of subfronts, as shows Fig. 1.22. In the next step is necessary to create from the current population Rt (previously ranked and ordered by subfront number) a new offspring (Pt+1 ), the objective will be to choose from a population of size 2N, the N solutions which belong to the first subfronts. In this manner, the last subfront could be greater than is necessary, then it is used a measure (idistance ) that allows to identify the better solutions and preserving elitism by selecting the solutions that are far the rest, this is possible simply by modifying a little bit the concept of Pareto dominance by including constraints in the dominance concept. 1 Analysis, Design and Optimization of Active Devices 21 1.4 Pareto Front 1.2 F1 F2 F3 1 F4 0.8 f2 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 f1 Fig. 1.22 Fast Non-dominated sorting 1.4.2 Multi-Objective Evolutionary Algorithm Based on Decomposition The basic idea of MOEA/D is the decomposition of a multiobjective problem in scalar optimization subproblems by a weights vector [36]. This vector associates a weight (λ ) for each subproblem which is considered as a single individual in the population which is going to try to improve by itself and to its nearby (neighbors ). After the initialization of the parameters the first step in MOEA/D is related to define the N spread weights vector over the objectives space (to each individual corresponds one λi ). One way can be by using a parameter H in a sequence as described by (1.8): 0 1 H , ,..., . (1.8) H H H Therefore, for m “ 2 , N “ H + 1 , with m > 2 the number of such vectors is defined by the combination in (1.9): m−1 N “ CH+m−1 (1.9) In Algorithms 2 and 3 are the pseudocode to generate these vectors, for three and m objectives, respectively. It is necessary to chose a value for H, so that the population size depends on this number. 22 I. Guerra-G´omez et al. Algorithm 2 Build spread of N weight vectors (m “ 3) 1: i “ 1, set H 2: for µ1 “ 0 to 1, step H1 do 3: for µ2 “ 0 to 1, step H1 do 4: if 1 − (µ1 + µ2 ) ≥ 0then λi “ {µ1 µ2 . . . 1 − (µ1 + µ2 ) } 5: 6: i “ i+1 7: end if 8: end for 9: end for Algorithm 3 Build spread of N weight vectors for m objectives 1: i “ 1, set H 2: for µ1 “ 0 to 1, step H1 do 3: for µ2 “ 0 to 1, step H1 do . .. 4: 5: for µm−1 “ 0 to 1, step H1 do 6: if 1 − (µ1 + µ2 + . . . µm−1 ) ≥ 0 then λi “ {µ1 µ 2 . . . 1 − (µ1 + µ2 + . . . µm−1 ) } 7: 8: i “ i+1 9: end if 10: end for . 11: .. 12: end for 13: end for Algorithm 4 MOEA/D Algorithm 1: build an uniform spread of N weight vectors (λ ) 2: B(i) “ {i1 , i2 , . . ., iT } 3: t “ 1 , POP=random() , set E “ 0/ , T 4: repeat 5: for i “ 1, 2, . . ., N do 6: randomly select parents from B(i) 7: generate new individual y 8: for each ℓ ∈ B(i) do 9: if g(y | λℓ , Z∗ ) ≤ g(xℓ | λℓ , Z∗ ) then 10: xℓ “ y 11: Fℓ “ F(y) 12: end if 13: end for 14: end for 15: remove from EP all vectors dominated by F(y) 16: until stop criteria A number (T ) of neighborhoods is defined for each λi . The Euclidean distance between each λi is calculated. Finally, for each λi there are (T ) neighborhoods nearby, saved in B. Algorithm 4 shows the steps performed by MOEA/D [36]. In each generation there is a population of N points x1 , x2 , . . . , xN ∈ X where xi “ (x1i , x2i . . . xni ) is the current solution to the ith subproblem and there are F1 , F2 , . . . , FN , where Fi “ F(xi ) : Rn → R. 1 Analysis, Design and Optimization of Active Devices 23 Algorithm 5 Pseudocode for MO-PSO 1: Initialize NoLoops, bound limits, population (N) and velocities 2: Evaluate population 3: Update Pbest 4: Select non-dominated particles 5: Select Gbest randomly among non-dominated particles 6: for i= 1 to NoLoops do 7: for j=1 to N do 8: Update particle velocity 9: Update particle position 10: Ensuring new position is into bound limits 11: end for 12: Evaluate population 13: Update Pbest 14: Select non-dominated particles and save them in REP 15: Select Gbest randomly among non-dominated particles 16: end for In the procedure, a new individual y is generated and compared with all its neighborhood by applying a decomposition approach (g[xi | λi , Z∗ ]), e.g. the Tchebycheff Approach, and each neighbor worse than this new individual will be replaced by it in an external population (EP), which is used to store non-dominated solutions. In the Tchebycheff Approach, the scalar optimization problem is described by (1.10), where Z∗ “ {z∗1 , z∗2 , . . . , z∗m }T are the best current objective functions found. g(xi | λi , Z∗ ) “ max{λi | f j (xi ) − z∗j |} 1≤i≤N . (1.10) 1≤ j≤m 1.4.3 Multi-Objective Particle Swarm Optimization In the Multi-Objective Particle Swarm Optimization Algorithm (MO-PSO) [32], there are N particles denoted by xi , where i “ 1, 2, . . . , N, and are represented by their positions in the search space. Each particle xi “ (x1i , x2i . . . xni ) represents a position in the space and depends on its previous local best position (Pbest ) and global best position (Gbest ). Equation (1.11) is used to compute the speed of each particle, where Vi is the current velocity of the particle ith, kw is the inertia weight which takes typical values lower than 1; Pbesti is the best position of particle ith, Pi is the position of the current particle and Gbest is a global best selected among the global best solutions. The new position of each particle is computed by (1.12). Vi “ kwVi + R1(Pbesti − Pi) + R2(Gbest − Pi ). (1.11) Pi “ Pi + Vi . (1.12) In Algorithm 5 our proposed MO-PSO is described. It takes care of the new position to avoid going beyond the bound limits. Step 1 is the initialization 24 I. Guerra-G´omez et al. procedure to set the bound limits, and the particles are initialized randomly within those bound limits. The velocities are initialized with zero values. In step 2, the population is evaluated to update the best position (Pbest ) at step 3, for each particle. Afterwards, the non-dominated particles are gathered to select randomly a global best (Gbest ) into that repository (steps 4 and 5). Then, the velocity and position of each particle is updated, and avoiding going beyond the bound limits (steps 7–11). Once all the particles are updated, an evaluation process updates the best position for each particle, the non-dominated particles are selected and saved in a repository (REP). Among the solutions contained in REP, one of them is selected randomly to be the global best for the next loop (steps 12–15). This process continues until a determined number of loops. 1.4.4 Optimization of Active Devices by Evolutionary Algorithms This section shows the application of NSGA-II, MOEA/D and MO-PSO, in the optimization of the nine CFOAs shown in Fig. 1.21. Those algorithms were programmed with a PERL script, and the circuit simulations are made with HSPICE. The goal is to find the optimal width (Wi ) and length (L) of each MOSFET. The simulation results are collected by using the HSPICE .MEASURE instruction, that is capable to save electronic measurements in the output listing. The CFOAs are biased with VDD “ 1.5 V and VSS “ −1.5 V. The electrical measurements were executed with a load capacitor of 1 pF and the HSPICE simulations were performed with a LEVEL 49 standard CMOS Technology of 0.18 µm. As already shown in [32–34], the optimization problem is expressed as: minimize f(x) “ [ f1 (x), f2 (x), . . . , f11 (x)]T subject to hk (x) ≥ 0 , k “ 1 . . . p, (1.13) where x ∈ X. f(x) is the vector formed by eleven objectives: • f1 (x) “ Power consumption • f2 (x) “ |1 - Voltage gain from Y port to X port| (GAINX ) • f3 (x) “ −1∗ Voltage band width from Y port to X port (BWX ) • f4 (x) “ −1∗ Input resistance on Y port (ZY ) • f5 (x) “ Output resistance on X port (ZX ) • f6 (x) “ | 1 - Current gain from X port to Z port| (GAINZ ) • f7 (x) “ −1∗ Current band width from X port to Z port (BWZ ) • f8 (x) “ −1∗ Output resistance on Z port (ZZ ) • f9 (x) “ |1 - Voltage gain from Z port to W port| (GAINW ) • f10 (x) “ −1 * Voltage band width from Z port to W port (BWW ) • f11 (x) “ Output resistance on W port (ZW ) 1 Analysis, Design and Optimization of Active Devices 25 Table 1.2 CFOAAA ENCODING gene Design variable Encoding Decision space x1 L All transistors 0.18 µm ≤ L ≤ 0.9 µm x2 W1 MREF, MB1-MB4, M1, M2 0.18 µm ≤ W1 ≤ 200 µm x3 W2 MA1-MA4, M3, M4 0.18 µm ≤ W2 ≤ 200 µm x4 W3 MB5, MB6, M5, M6 0.18 µm ≤ W3 ≤ 200 µm x5 W4 MA5, MA6, M7 , M8 0.18 µm ≤ W4 ≤ 200 µm x6 I IBIAS 10 µA ≤ I ≤ 400 µA Table 1.3 CFOABC ENCODING gene Design variable Encoding Decision space x1 L1 MREF, MA1-MA4, MB1-MB4, M1-M4 0.18 µm ≤ L1 ≤ 0.9 µm x2 L2 MA5, MA6, MB5, MB6, M6-M8 0.18 µm ≤ L2 ≤ 0.9µ m x3 W1 MREF, MB1, MB2, M3, M4 0.18 µm ≤ W1 ≤ 200 µm x4 W2 MA1, MA2, M1, M2 0.18 µm ≤ W2 ≤ 200 µm x5 W3 MB3, MB4 0.18 µm ≤ W3 ≤ 200 µm x6 W4 MA3, MA4 0.18 µm ≤ W4 ≤ 200 µm x7 W5 MB5, MB6 0.18 µm ≤ W5 ≤ 200 µm x8 W6 MA5, MA6 0.18 µm ≤ W6 ≤ 200 µm x9 W7 M5 0.18 µm ≤ W7 ≤ 200 µm x10 W8 M6 0.18 µm ≤ W8 ≤ 200 µm x11 W9 M7 0.18 µm ≤ W9 ≤ 200 µm x12 W10 M8 0.18 µm ≤ W10 ≤ 200 µm x13 I IBIAS 10 µA ≤ I ≤ 400 µA Table 1.4 CFOACC encoding gene Design variable Encoding Decision space x1 L1 MREF, MA1-MA4, MB1-MB4, M1-M4 0.18 µm ≤ L1 ≤ 0.9 µm x2 L2 MA5, MA6, MB5, MB6, M6-M8 0.18 µm ≤ L2 ≤ 0.9 µm x3 W1 MREF, MB1-MB4 0.18 µm ≤ W1 ≤ 200 µm x4 W2 MA1-MA4 0.18 µm ≤ W2 ≤ 200 µm x5 W3 M3 0.18 µm ≤ W3 ≤ 200 µm x6 W4 M1 0.18 µm ≤ W4 ≤ 200 µm x7 W5 M2 0.18 µm ≤ W5 ≤ 200 µm x8 W6 M4 0.18 µm ≤ W6 ≤ 200 µm x9 W7 MB5, MB6 0.18 µm ≤ W7 ≤ 200 µm x10 W8 MA5, MA6 0.18 µm ≤ W8 ≤ 200 µm x11 W9 M6 0.18 µm ≤ W9 ≤ 200 µm x12 W10 M5 0.18 µm ≤ W10 ≤ 200 µm x13 W11 M7 0.18 µm ≤ W11 ≤ 200 µm x14 W12 M8 0.18 µm ≤ W12 ≤ 200 µm x15 I IBIAS 10 µA ≤ I ≤ 400 µA 26 Table 1.5 Optimized performances for the CFOAs shown in Fig. 1.21 Objective POWER GAINX BWX ZY ZX GAINZ BWZ ZZ GAINW BWW ZW Units Watts | VVYX | Hz Ω Ω | VVXZ | Hz Ω | VVYX | Hz Ω CFOAAA NSGA-II 1.61E-4 0.9883 5.54E7 20612 1737 0.9825 5.26E7 391360 0.9849 1.82E6 83091 MOEA/D 1.58E-4 0.9881 6.48E7 32139 1976 0.9711 9.29E7 442150 0.9811 1.30E6 120800 MOPSO 3.77E-4 0.9883 8.79E7 7227 902.6 0.9864 6.28E7 11138 0.9881 4.77E7 2853 CFOAAB NSGA-II 3.32E-4 0.9851 1.34E8 16870 904.8 0.9943 1.93E8 173730 0.9779 1.42E6 100800 MOEA/D 1.59E-4 0.9881 6.30E7 33626 1921 0.9706 8.42E7 466010 0.9783 7.85E5 185980 MOPSO 3.91E-4 0.9869 1.02E8 10257 922.3 0.9823 9.42E7 15928 0.9749 2.53E7 6699 CFOAAC NSGA-II 2.70E-4 0.9871 6.54E7 7357 2042 0.9942 6.84E7 134620 0.9778 4.39E7 3968 MOEA/D 3.13E-4 0.9882 6.26E7 95688 1835 0.9801 6.92E7 132850 0.9754 4.39E7 2456 MOPSO 1.13E-3 0.9835 1.40E8 45082 738.7 0.9752 6.98E7 2344 0.9878 1.25E8 645.2 CFOABA NSGA-II 3.35E-4 0.987 2.69E7 106960 4071 0.9907 5.68E7 5700 0.9848 7.60E7 2173 MOEA/D 4.73E-4 0.9873 2.70E7 142350 4350 0.9829 6.01E7 4444 0.9871 1.17E8 643.2 MOPSO 1.50E-3 0.9865 7.01E7 20337 1259 0.9912 8.25E7 975 0.9856 1.94E8 275.9 CFOABB NSGA-II 6.84E-3 0.9734 7.51E7 269280 1994 0.9735 2.27E8 1007 0.9457 7.89E8 176.6 MOEA/D 4.85E-4 0.9851 2.46E7 756260 6110 0.9829 5.73E7 60735 0.974 1.98E7 9002 I. Guerra-G´omez et al. MOPSO 6.75E-3 0.9821 1.53E8 27306 821.4 0.9912 1.29E8 709.3 0.9403 3.65E8 337.5 CFOABC NSGA-II 8.76E-4 0.986 1.70E7 382410 7816 0.9948 4.08E7 2470 0.9807 1.95E8 313.9 MOEA/D 1.43E-3 0.9857 9.01E7 55392 1471 0.975 7.24E7 100230 0.9839 3.32E7 3423 MOPSO 6.89E-3 0.9828 1.13E8 51479 1054 0.9801 1.32E8 1431 0.9786 4.62E8 148.6 1 Analysis, Design and Optimization of Active Devices CFOACA NSGA-II 3.34E-4 0.9823 6.59E7 172600 1953 0.9898 6.35E7 298510 0.9859 9.25E5 162920 MOEA/D 2.84E-4 0.9825 2.72E7 1012100 5376 0.9924 2.97E7 558540 0.9833 3.52E6 42719 MOPSO 1.13E-3 0.9835 1.40E8 45082 738.7 0.9752 6.98E7 2344 0.9878 1.25E8 645.2 CFOACB NSGA-II 6.93E-4 0.9838 1.25E8 92861 736.9 0.9789 8.85E7 141830 0.9747 4.87E6 32926 MOEA/D 4.53E-4 0.9847 5.55E7 277830 2480 0.9801 7.00E7 422190 0.9774 2.08E6 68170 MOPSO 1.77E-3 0.9829 1.85E8 35788 545.5 0.9837 1.10E8 2723 0.9769 7.75E7 1360 CFOACC NSGA-II 7.45E-4 0.9835 1.20E8 119030 844.4 0.9885 1.08E8 129250 0.9844 2.34E7 6985 MOEA/D 7.26E-4 0.9858 7.88E7 81182 1552 0.9911 6.97E7 305020 0.9773 3.72E7 5151 MOPSO 2.00E-3 0.9843 1.54E8 21114 698.3 0.9822 7.14E7 28261 0.9763 1.12E8 1463 27 28 I. Guerra-G´omez et al. where X : Rn | 0.18 µm ≤ Li ≤ 0.9 µm, 0.18 µm ≤ W j ≤ 200 µm, 10 µm ≤ IBIAS ≤ 400 µA, is the decision space for the n variables. Finally, hk (x), k “ 1 . . . p are performance constraints, in our experiments we include the saturation condition in all transistors as constraints. All CFOAs are encoded with Li and Wi , where i represents a specific transistor or transistors sharing the same L or W. All L and W values are rounded to multiples of the minimum allowed by the technology process. The variables encoding for some CFOAs from Fig. 1.21 are listed in Tables 1.2–1.4. Table 1.5 shows the optimization results of the nine CFOAs. The three evolutionary algorithms are listed along with the best feasible solutions for the 11 objective functions. From this table, one can select the desired topology accomplishing target specifications [37]. 1.5 Conclusions This chapter summarized recent developments on the analysis and design of active devices by using the nullor concept and pathological elements. Those active devices find applications in the area of analog signal processing, as shown in the following chapters. The optimization of active devices was discussed by presenting the application of three evolutionary algorithms, which provide similar results, but their computational capabilities still being for future research. Acknowledgment This work is supported by CONACyT/MEXICO under project 131839-Y. References 1. S´anchez-L´opez C, Fern´andez FV, Tlelo-Cuautle E, Tan SX-D (2011) Pathological element- based active device models and their application to symbolic analysis. IEEE Trans Circuits Syst I Regul pap 58(6):1382–1395 2. Wang HY, Huang WC, Chiang NH (2010) Symbolic nodal analysis of circuits using patholog- ical elements. IEEE Trans Circuits Syst II Express Briefs 57(11):874–877 3. Saad RA, Soliman AM (2008) Use of mirror elements in the active device synthesis by admit- tance matrix expansion. IEEE Trans Circuits Syst I Fundam Theory Appl 55(9):2726–2735 4. Tlelo-Cuautle E, S´anchez-L´opez C, Moro-Frias D (2010) Symbolic analysis of (MO)(I)CCI(II)(III)-based analog circuits. Int J Circuit Theory Appl 38(6):649–659 5. Tlelo-Cuautle E, S´anchez-L´opez C, Martinez-Romero E, Tan SX-D (2010) Symbolic analysis of analog circuits containing voltage mirrors and current mirrors. Analog Integr Circuits Signal Process 65(1):89–95 6. Fakhfakh M, Tlelo-Cuautle E, Fern´andez FV (2012) Design of Analog Circuits through Symbolic Analysis. Bentham Sciences Publishers Ltd., United Arab Emirates 7. Tlelo-Cuautle E, Martinez-Romero E, S´anchez-L´opez C, Tan SX-D (2010) Symbolic be- havioral modeling of low voltage amplifiers. IEEE international confernce on electrical engineering, computing science and automatic control (CCE), M´exico, pp 510–514 1 Analysis, Design and Optimization of Active Devices 29 8. Rodriguez-Chavez S, Tlelo-Cuautle E, Palma-Rodriguez AA, Tan SX-D (2012) Symbolic DDD-based tool for the computation of noise in CMOS analog circuits. International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico 9. Shi G (2011) A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits. Analog Integr Circuits Signal Process. doi: 10.1007/s10470-011-9773-8 10. Tan SX-D, Liu X-X, Molinar E, Tlelo-Cuautle E (2012) Parallel symbolic analysis of large analog circuits on GPU platforms. In: VLSI Design, InTech Publisher. Available via InTech– Open Science 11. Souliotis G, Haritantis I (2008) Current-mode filters based on current mirror arrays. Int J Circuit Theory Appl 36:173–183 12. Duarte-Villase˜nor MA, Tlelo-Cuautle E, Gerardo de la Fraga L (2011) Binary genetic encoding for the synthesis of mixed-mode circuit topologies. Circuits Syst Signal Process. doi:10.1007/s00034-011-9353-2 13. Martens E, Gielen G (2008) Classification of analog synthesis tools based on their architecture selection mechanisms. Integr VLSI J 41:238–252 14. Biolek D, Senani R, Biolkova V, Kolka Z (2008) Active elements for analog signal processing: classification, review, and new proposals. Radioengineering 17(4):15–32 15. Sedra A, Smith KC (1968) The current conveyor: a new circuit building block. Proc IEEE 56:1368–1369 16. Mobarak M, Onabajo M, Silva-Martinez J, et al (2010) Attenuation-predistortion linearization of CMOS OTAs with digital correction of process variations in OTA-C filter applications. IEEE J Solid State Circuits 45(2):351–367 17. Abhirup L, Maneesha G (2011) Realizations of grounded negative capacitance using CFOAs. Circuits Syst Signal Process 30(1):143–155 18. Gupta SS, Bhaskar DR, Senani R, et al (2011) Synthesis of linear VCOs: the state-variable approach. J Circuits Syst Comput 20(4):587–606 19. Soliman AM (2011) Generation of CFOA, CCII and DVCC based oscillators from passive RLC filter. J Circuits Syst Comput 20(4):621–639 20. Trejo-Guerra R, Tlelo-Cuautle E, S´anchez-L´opez C, Mu˜noz-Pacheco JM, Cruz-Hern´andez C (2010) Realization of multiscroll chaotic attractors by using current-feedback operational amplifiers. Revista Mexicana de Fisica 56(4):268–274 21. Saad RA, Soliman AM (2010) A new approach for using the pathological mirror elements in the ideal representation of active devices. Int J Circuit Theory Appl 38(2):148–178 22. Biolek D, Bajer J, Biolkova V, et al (2011) Z copy-controlled gain-current differencing buffered amplifier and its applications. Int J Circuit Theory Appl 39(3):257–274 23. S´anchez-L´opez C, Martinez-Romero E, Tlelo-Cuautle E (2011) symbolic analysis of OTRAs- Based circuits. J Appl Res Technol 9(1):69–80 24. S´anchez-L´opez C, Fern´andez FV, Tlelo-Cuautle E (2010) Generalized admittance matrix models of OTRAs and COAs. Microelectronics J 41(8):502–505 25. Tlelo-Cuautle E, Duarte-Villase˜nor MA, Garcia-Ortega JM, S´anchez-L´opez C (2007) Design- ing SRCOs by combining SPICE and Verilog-A. Int J Electronics 94(4):373–379 26. Tlelo-Cuautle E (2011) Advances in analog circuits. InTech Publisher. Online Available http://www.intechweb.org/books/show/title/advances-in-analog-circuits 27. Tlelo-Cuautle E, Torres-Mu˜noz D, Torres-Papaqui L (2005) On the computational synthesis of CMOS voltage followers. IEICE Trans Fundam Electronics Commun Comput Sci E88- A(12):3479–3484 28. Carvajal RG, Ramirez-Angulo J, L´opez-Martin A, Torralba A, Gal´an J, Carlosena A, Mu˜noz F (2005) The flipped voltage follower: a useful cell for low-voltage low-power circuit design. IEEE Trans Circuits Syst II 52(7):1276-1291 29. Gupta SS, Senani R (2006) New voltage-model/current-mode universal biquad filter using unity-gain cells. Int J Electronics 93(11):769–775 30. S´anchez-L´opez C, Castro-Hernandez A, Perez-Trejo A (2008) Experimental verification of the Chua’s circuit designed with UGCs. IEICE Electron Express 5(17):657–661 30 I. Guerra-G´omez et al. 31. Trejo-Guerra R, Tlelo-Cuautle E, Jim´enez-Fuentes JM, Mu˜noz-Pacheco JM, S´anchez-L´opez C (2011) Multiscroll floating gate based integrated chaotic oscillator. Int J Circuit Theory Appl. doi:10.1002/cta.821 32. Tlelo-Cuautle E, Guerra-G´omez I, Reyes-Garcia CA, Duarte-Villase˜nor MA (2010) Synthesis of analog circuits by genetic algorithms and their optimization by particle swarm optimization. In: Chiong R (ed) Intelligent systems for automated learning and adaptation: emerging trends and applications. Information Science Reference: IGI Global, pp 173–192 33. Tlelo-Cuautle E, Guerra-G´omez I, Duarte-Villase˜nor MA, de la Fraga LG, Flores-Becerra G, Reyes-Salgado G, Reyes-Garcia CA, Rodriguez-G´omez G (2010) Applications of evolutionary algorithms in the design automation of analog integrated circuits. J Appl Sci 10(17):1859–1872 34. Tlelo-Cuautle E, Guerra-G´omez I, de la Fraga LG, Flores-Becerra G, Polanco-Martag´on S, Fakhfakh M, Reyes-Garcia CA, Rodriguez-G´omez G, Reyes-Salgado G (2011) Evolutionary algorithms in the optimal sizing of analog circuits. In: Koeppen M, Schaefer G, Abraham A (eds.) Intelligent computational optimization in engineering: techniques & applications, vol 366. Springer, Hershey, PA, pp 109–138 35. Deb K, Pratap A, Agarwal S, Meyarivan T (2002) A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans Evol Comput 6(2):182–197 36. Zhang QF, Li H (2007) MOEA/D: a multiobjective evolutionary algorithm based on decompo- sition. IEEE Trans Evol Comput 11(6):712–731 37. Polanco-Martag´on S, Reyes-Salgado G, Flores-Becerra G, Guerra-G´omez I, Tlelo-Cuautle E, de la Fraga LG, Duarte-Villase˜nor MA (2012) Selection of MOSFET sizes by fuzzy sets intersection in the feasible solutions space. J Appl Res Technol 10(2) In press Chapter 2 Nullors, Their Bipolar and CMOS Implementations and Applications in Analog Circuit Synthesis and Design Raj Senani, A.K. Singh, Pragati Kumar, and R.K. Sharma 2.1 Introduction Analog circuits using the traditional voltage mode (VM) op-amps suffer from the well-known drawbacks resulting from the limited slew rate, gain- bandwidth conflict and requirements of passive component-matching in the realization of several functions (such as controlled current sources, non-inverting integrators/differentiators and variable gain differential/instrumentation amplifiers, to name a few). The requirement of component-matching quite often leads to increased sensitivities and may even cause instability in several cases. During the past four decades, a number of research groups around the world have toiled with the idea of searching for a universal analog building block overcoming the aforementioned limitations. Of various building blocks proposed so far, nullors have been regarded to be universal building blocks since the four controlled sources and all existing analog circuit building blocks can be represented using only nullors R. Senani () Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India e-mail: [email protected] A.K. Singh Department of Electronics and Communication Engineering, ITS Engineering College, Greater Noida, India e-mail: [email protected] P. Kumar Department of Electrical Engineering, Delhi Technological University, New Delhi, India e-mail: pragati [email protected] R.K. Sharma Department of Electronics and Communication Engineering, Ambedakar Institute of Technology, New Delhi, India e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 31 DOI 10.1007/978-1-4614-1383-7 2, © Springer Science+Business Media New York 2013 32 R. Senani et al. a b c Nullator I, V both arbitrary Nullor Norator ⎡V1 ⎤ ⎡ 0 0 ⎤ ⎡ V 2 ⎤ ⎢ ⎥=⎢ ⎥⎢ ⎥ ⎣ I 1 ⎦ ⎣0 0 ⎦ ⎣ − I 2 ⎦ ‘Null’ transmission matrix Fig. 2.1 Symbols and definitions of nullator, norator and nullor and resistors. The floating nullor is a special form of nullor in which ground is external to the four terminals forming the two-port (with nullator comprising the input port and norator comprising the output port). Although the origin of the concept of nullor itself was advanced as early as 1961–1964, by Carlin and Youla [1, 2] till about 1984 or so, theses elements were largely regarded as theoretical concepts useful only in generating equivalent networks of BJT and Op-Amp based circuits such as gyrators and impedance converters/inverters. However, over the years, nullors have attracted a lot of attention in literature and there have been a large number of publications dealing with applications and implementations of nullors, for instance, see [3] and the references cited therein. It was shown by a number of researchers (such as Nordholt [4], Stevenson [5], Huijsing [6] and Senani [7] (who coined the term “four-terminal floating-nullor” (FTFN) to represent a fully floating nullor) that fully floating versions of Op-Amps [termed as operational floating amplifier (OFA)] and FTFNs are more versatile and flexible building blocks than the traditional op-amps in several applications. Thus, the “OFA” and “FTFN” got going and soon attracted the attention of circuit designers as attractive building blocks for a number of voltage- mode and current-mode signal processing applications. In most of the investigations, the FTFNs have been realized by a composite connection of two CCIIs as suggested by Senani in [7]. The current feedback op-amp AD844 from Analog Devices, which embodies a CCII+ followed by an on-chip buffer, became a preferred choice for implementing FTFNs using the quoted formulation (shown explicitly in Fig. 2.7d in this chapter). However, it is the CMOS implementability of the concept of FTFN which has brought it to the forefront of analog design in more recent years. A number of CMOS implementations of the FTFNs are now known, for instance, see [8–11] and references cited therein. In this chapter, we deal with the nullors, particularly the floating ones namely, the FTFNs or OFAs, their hardware implementations and applications in circuit synthesis and design. The symbolic notation and characterizing equations for nullator, norator and nullor have been depicted in Fig. 2.1. 2 Nullors, Their Bipolar and CMOS Implementations... 33 2.2 Nullor Representation of Various Analog Circuit Building Blocks Since the evolution of nullors, the utility of nullor representation of ideal transistors (both BJT, FET) and the ideal Op-Amps was soon understood [12]. Subsequently, nullors have also been used to model other active building blocks which came into existence later on. Thus, it is well known that an ideal BJT as well as an ideal FET/MOSFET is a three-terminal nullor (see Fig. 2.2a); an ideal op-amp is also a three-terminal nullor with its input terminals representing a nullator and the output terminal with respect to the ground representing the norator; see Fig. 2.2b. A CCII− is equivalent to a three-terminal nullor (Fig. 2.3). This equivalence and the basic properties of nullators and norators and different ways of combining these have been used by Senani [13] and Higashimura and Fukui [14, 15] to synthesize a number of interesting CCII−based inductance simulation circuits. In principle, since all the four controlled sources (namely, the voltage- controlled/current-controlled voltage/current sources) can be represented by nullators, norators and resistors, a CCII+ can also be represented by nullors but requires two resistors in addition (see Fig. 2.4). A nullor representation of an operational transconductance amplifier (OTA), voltage follower (VF) and current follower (CF) are shown in Fig. 2.5. a c b c b 1 1 3 3 2 b e e 2 Fig. 2.2 Nullor models of active devices: (a) Ideal transistor (BJT). (b) Ideal op-amp y z y CCII- z x x Fig. 2.3 Nullor model of CCII− iy = 0,vx = vy, iz = ix y y CCII+ z x z R R x Fig. 2.4 Nullor model iy = 0, vx = vy, iz = ix of CCII+ 34 R. Senani et al. a V1 Gm i0 V1 V2 Gm i0 = Gm (V1−V2 ) V2 i0 b c Iin VF Iin CF I0 1 1 Vin V0 Vin V0 = Vin ; Iin =0 I0 = ; =0 Iin Vin Fig. 2.5 Nullor model of other active building blocks. (a) Nullor model of an OTA. (b) Nullor model of a VF. (c) Nullor model of a CF Since nullors can be used to represent a variety of active elements, they provide a unified framework not only for analysis, synthesis and design of active networks but also for inter-relating the realizations using different active elements. This fact will be unfolded in subsequent sections of this chapter. However, before proceeding further, we briefly look into the advent of OFAs and FTFNs. 2.3 The Advent of OFA and FTFN Nordholt in 1982 [4], presented a method of extending op-amp capabilities using current source power supplies. This “extended op-amp” represented a four-port active element which was loosely equivalent to a floating nullor. Another op-amp-based floating nullor was employed by Stevenson in 1984 in realizing two-way circuits with inverse transmission properties in [5]. This floating nullor circuit was derived from a three-terminal nullor realized with two op-amps, proposed earlier by Cox, Su and Woodland in 1971 [16]. Huijsing in [6, 17], introduced the concept of an OFA which is same as a floating nullor (Fig. 2.6). It was demonstrated that an OFA is particularly useful in realizing current amplifiers, gyrators and instrumentation amplifier with a minimum possible number of external passive components in contrast to conventional op-amp-based circuits for the same functions and hence, an OFA can be regarded to be a versatile building block.1 1 For a differential difference version of an OFA, see [18]. 2 Nullors, Their Bipolar and CMOS Implementations... 35 a b I2 + - OFA1 OFA3 I1 + - + - + + floating floating OFA - port1 G1 G2 port2 + V2 - V1 + + G1 OFA2 OFA4 + - - - - Fig. 2.6 OFA-based circuits (adapted from [17] c 1993 Springer). (a) V to I converter I1 = G1 V1 . (b) Floating gyrator (I1 = G2 V2 , I2 “ −G1 V1 ) b CCII- a y z X W X x W x Y y z Z Y Z CCII- c d X y X y CCII- z W w z x x W x Z CCII- z Z x z Y y w Y y Fig. 2.7 A FTFN implementation using CCIIΘ. (a) FTFN. (b) A FTFN using two three-terminal nullors. (c) FTFN using two CCIIΘ. (d) FTFN using two CFOAs It was shown by Senani in [7, 13] that FTFNs provide a novel solution to the problem of RC active synthesis of floating impedances. A discrete implementation of the FTFN using only an op-amp, OTA and a resistance was proposed in [7]. It was also suggested in [7] that a composite connection of two CCII− can be used to realize an FTFN (see Fig. 2.7a–c of this chapter). This follows from the fact that the representation of FTFN of Fig. 2.7a is equivalent to the combination of two 3- terminal nullors as shown in Fig. 2.7b where each 3-terminal nullor is equivalent to a 36 R. Senani et al. +V +V 1 + 3 4 2 - -V -V c 1994 IEEE) Fig. 2.8 An OMAΘ-based FTFN realization (adapted from [22] CCII−, thus, finally, leading to the implementation of Fig. 2.7c. In fact, two CCII+ or two current feedback op-amps (CFOA) such as AD844, which contains a CCII+ and a VF, can also be used to realize an FTFN using the same configuration. In the recent years, the CFOA-based implementation of Fig. 2.7d has been quite frequently used by various circuit designers to implement an FTFN.2 Another implementation, which has also been employed in several instances, is the one based upon the concept of an operational mirrored amplifier (OMA) [20, 21], and is shown here in Fig. 2.8 which employs an OFA configuration particularly referred as OMAΘ. The outputs (3) and (4) are, however, dissimilar, the former being a voltage output (with ideally zero output impedance) and the later being a current output having ideally infinite output impedance). 2.4 CMOS and Bipolar Implementations of FTFN Though a bipolar three-terminal nullor in integratable form was presented as early as in 1977 by Huijsing and Dekorte in [23], the renewed interest in the applications of nullors grew after workable discrete implementations of the floating nullor (FTFN) using the off-the-shelf components as detailed in the previous section started becoming available. Subsequently, during the late nineties, a number of researchers 2 Itwas suggested in [19] that the OTA Max 435 could also be used as an FTFN although to the best knowledge of the authors the same does not appear to have been employed as an FTFN experimentally anywhere in the open literature so far. 2 Nullors, Their Bipolar and CMOS Implementations... 37 +V M5a Vb2 Vb4 Vb3 x y w z Vb1 Vb5 -V c 2000, Taylor and Fig. 2.9 CMOS FTFN proposed by Cam and Kuntman (adapted from [10] Francis) worked out a number of CMOS implementations of the FTFN. Because of space limitations, it is difficult to describe all bipolar/CMOS OFAs/FTFNs reported so far, the discussion would be limited to a few representative implementations only. In 1999, Cam and Kuntman presented a CMOS implementation of two circuits that realize FTFNs [8]. Both these implementations were based on CMOS CCII− architecture. In yet another proposition in 2000, Cam, Toker and Kuntman [9] presented a CMOS implementation of FTFN based on translinear cells. Though not mentioned there explicitly, this implementation is in fact, an interconnection of two translinear CCII+- conforming to the scheme of Fig. 2.7b. Cam and Kuntman in [10] proposed another CMOS realization of the FTFN which combines the advantages of a cascade of common-source and common-gate amplifiers and a floating current source. This circuit was shown to exhibit wideband operation (unity gain bandwidth in excess of 250 MHz) with a wide dynamic range. Fig. 2.9 shows the circuit proposed in [10]. Tansritat, Unhavanich, Dumawipata and Surakompontorn [24] presented a bipolar implementation of an FTFN with variable current gain which they termed as a tunable FTFN. This implementation is a modification of the basic supply current sensing method for the realization of FTFN. Jiraseri-amornkun, Chipipop and Surakompontorn [25] presented another bipolar implementation of an FTFN with multiple complementary outputs. This implementation is based on a transconductor and an improved translinear cell wherein a number of CMs have been used to replicate the output currents (see Fig. 2.10). 38 R. Senani et al. +V Z- W Z+ X Y IB2 IB1 IB3 -V c Fig. 2.10 Bipolar implementation of the multiple output floating nullor (adapted from [25] 2001, IEEE) +V Vbia s1 Vbias2 Vbias1 Vbias2 Vbias3 Vbias3 Iwp Izn Izp Iwn Vwp Vzn Vzp Vwn Vyp Vxn Vyn Vxp Vbias4 Vbias4 Ibias -V c 2002, IEEE) Fig. 2.11 CMOS fully-balanced FTFN (adapted from [11] In 2002, Al-Zaher and Ismail in [11] presented the notion of a fully-balanced3 FTFN and its CMOS implementation. They modified the design of the Op-Amp used in supply current sensing mode, by providing two input differential stages. Provision of two balanced outputs was made instead of a single output from the op-amp. These outputs are finally mirrored to the output port of the FTFN. This circuit is shown in Fig. 2.11 and is characterized by the following equations: Ixp “ Ixn “ Iyp “ Iyn “ 0; Vdx “ Vxp − Vxn “ Vdy “ Vyp − Vyn ; Idz “ Izp − Izn “ −Idw “ −(Iwp − Iwn ). 3 Foranother extension of FTFN or OFA termed as “Differential difference operational floating amplifier”, the reader is referred to [18]. 2 Nullors, Their Bipolar and CMOS Implementations... 39 From survey of literature and the exemplary implementations outlined here, the opinion of the authors is that any “perfect” bipolar/CMOS implementation of the FTFN has yet not been achieved. In the subsequent sections, we will show important applications of nullors/FTFNs in the areas of floating impedance simulation, generation of equivalent oscillators and universal biquad filter realization which may serve as a motivation for developing a fully integrable bipolar/CMOS FTFN as an off-the-shelf IC. 2.5 Novel Applications of FTFN in Impedance Synthesis Simulated inductors have important applications in the design of both filters and oscillators. The Antoniou’s generalized impedance converter (GIC) [26] based grounded lossless inductance simulation circuit has been the most well-recognized and widely-acceptable solution in many applications. Before the advent of FTFN, the problem of synthesizing floating inductors/impedances (FI) was regarded to be relatively more difficult than that of realizing grounded inductors/impedances. All available circuits/techniques called for either the use of two identical op-amp RC sub-circuits thereby leading to the requirement of double the number of op-amps and RC elements as in [7, 13, 27] or required a large number of resistors with matching constraints and/or cancellation conditions when only two op-amps were employed (as in the circuits of The-Yanagisawa [28]). A potential application of FTFNs has been in the area of floating impedance simulation where the resulting circuits offer significant advantages as compared to the previously known op-amp RC based FI circuits. In the following, we highlight a number of techniques of realizing floating impedances of various kinds using the concept of nullors/FTFNs known so far. 2.5.1 Realizing Floating Generalized Impedance Converters/Inverters The method to be presented here is based upon the following theorem presented in [7] and similar ideas contained in [13]: Theorem 2.1. Suppose that a 1-port active network N, containing grounded and floating, two terminal passive elements, nullators and norators realizes a grounded driving point impedance (GDPI) Y11 (s) “ y(s). If a 2-port network N* be formulated from N by disconnecting from ground all grounded passive elements and terminals (of grounded nullators and norators) and joining them together to form port 2, then N ∗ will have short circuit admittance matrix [Y]N∗ “ [Y](with i1 “ −i2 “ y(s)[v1 − v2]). For a formal proof of the above theorem, the reader is referred to [7]. 40 R. Senani et al. a b - + Z3 Z4 Z1 Z2 Z1 Z2 Z5 Z3 Z4 + - Z5 c d Z W FTFN Z3 Z4 Y X Z3 Z4 Z1 Z2 Z5 Z1 Z2 Z5 X Y FTFN W Z W Z e FTFN f Y X Z3 Z4 V1 Y4 Y5 Y1 Y2 Z1 Z2 Z5 I X Y y z y z FTFN FTFN-I FTFN-II x w x w Y3 W Z I V2 Fig. 2.12 Conversion of GIC-based grounded impedance into FTFN-based floating impedance (a) Antoniou’s GIC-based grounded impedance (adapted from [26] c 1969 IEE). (b) The nullor model of the circuit of (a). (c) A floating version of the GIC resulting from the application of Theorem 2.1 [7]. (d) An FTFN-based floating generalized impedance as per the method first introduced in 1987 in [7, 13]. (e) An alternative generalized floating impedance using FTFNs (adapted from [30] c 1997 c 2000 Springer). (f) Another FTFN based generalized floating impedance simulation (adapted from [31] c 2001 Springer) Consider now the Antoniou’s GIC shown in Fig. 2.12a. Figure 2.12b shows the nullor model for the same. In Fig. 2.12c, the two-port obtained by ungrounding both the norators as well as the impedance Z5 have been shown. Thus, from Theorem 2.1 it follows that the circuit of Fig. 2.12c would realize the same impedance in floating form as the grounded impedance realized by the GIC-based circuit of Fig. 2.12a, i.e. Z1 Z3 Z5 Z(s) “ Z2 Z4 2 Nullors, Their Bipolar and CMOS Implementations... 41 An FTFN implementation of the circuit of Fig. 2.12a is shown in Fig. 2.12d. It is, thus, seen that not only one does not require four op-amps and double the number of passive elements (including two capacitors) as required in the known methods of obtaining GIC-based floating impedance (for instance, see [29]) but one does not require any component matching conditions either which are required in the two-GIC-based (hence, four op-amp- based) approach. Note that for inductance simulation, Z2 or Z4 is chosen as a capacitor with all other impedances being resistors. An alternative floating structure of GIC-based generalized floating impedance proposed by Cabeza and Carlosena 1997, [30] is shown here in Fig. 2.12e which also realizes a floating impedance of the same value. Yet another circuit having the same characterization was proposed by Cam, Ozoguz and Kuntman in 2001 [31] as shown here in Fig. 2.12f. 2.5.2 Generation of CCIIΘ -based Floating Generalized Impedance Converters/Inverters Consider now the nullor model for generalized impedance converter/inverter shown in Fig. 2.13a taken from one of the models of reference [32]. By a routine analysis, the admittance looking into terminals 1 and 2 is found to be y1 y3 y5 y0 “ y2 y4 It is immediately clear from this nullor circuit, by appropriately defining the second port, a number of two port immittance inverter/converter circuits can be generated. Since none of the terminals or impedances is connected to ground, Theorem 2.1 applies. Since each pair of nullator, norator has common terminal, both the nullors are realizable with a CCII−. It may appear that a total number of six different floating generalized impedance converter/inverter should be derivable from the model of Fig. 2.13a however, after discarding the redundant cases; it is found that only three distinctly different configurations [27] are possible which are shown here in Fig. 2.13b. It may be pointed out that all the three configurations of Fig. 2.12d–f as well as those of Fig. 2.13b can be used to realize a number of useful floating impedances. In this context, it may be noted that the three most common elements, from the point of view of various active network applications, are the synthetic floating L, floating FDNR (Z(s) “ 1/Ds2 ) and floating FDNC (Z(s) “ Ms2 ) elements. With the proposed GPIC/GPII configurations, these are realizable more efficiently than the CC- based simulations previously known. 42 R. Senani et al. a Y1 Y3 Y4 Y2 Y5 Y0 b y y CCII-z CCII- z x x Y1 Y2 Y4 Y1 Y2 Y3 Y4 YL Y3 YL 1 y 2 1 y 2 z CCII- z CCII- x x x CCII-z y Y1 Y2 Y3 Y4 YL 1 x 2 z CCII- y c Fig. 2.13 (a) A nullor model of generalized impedance converter/inverter (adapted from [32] 1970 IEEE). (b) Three CCIIΘ-based floating generalized impedance converter/inverter derived c 1986 IEEE) from nullor model of (a) (adapted from [27] (a) Synthetic floating inductance (FI)-choosing Z3 as a capacitor and remaining impedances as resistors, the simulated L is given by C3 R1 R4 RL L1−2 “ (2.1) R2 (b) Floating FDNR- choosing Z1 and ZL as capacitors, the circuit simulates a floating FDNR having value C1CL R2 R3 D1−2 “ (2.2) R4 (c) Floating FDNC– choosing Z2 and Z3 as capacitors, the circuit simulates a floating FDNC having value M1−2 “ R1 R4 RL C2 C3 (2.3) 2 Nullors, Their Bipolar and CMOS Implementations... 43 It is worthwhile to point out that the previously published CC-networks simulating floating ideal L or D elements [33–38] use three to four CCs. Also, the ideal floating L (and also the corresponding D element), outlined by Paul and Patranabis [39] as an application example of their proposed floating NIC too employs four CCs. In comparison, the use of the proposed networks of Fig. 2.13b makes it possible to realize these elements with only two FTFNs or two CCs, while providing the merits of lack of any component-matching requirement, low sensitivities to element value changes and single-resistance-tunability of the realized immittances. For the CC-based realization of lossy FIs using nullors see [40]. 2.5.3 Generation of Lossless Floating Inductance Circuits Using a Single FTFN To the best knowledge of the authors, only four single op-amp lossless grounded inductance circuits appear to have been known in the earlier literature till date which were proposed by Orchard-Willson 1974, [41], Schmitt-Lee 1975, [42], Ramsey 1978, [43] and Horn-Moschytz 1979, [44]. Here, we demonstrate how all these four circuits can be transformed as per the techniques of [7, 13] into as many as sixteen4 lossless FI circuits using Theorem 2.1 in conjunction with Theorem 2.2 (to be outlined subsequently). Consider the grounded inductance simulation circuit of Horn-Moschytz [44] which realizes an inductance value R5 −1 R2 R2 R1 + R6 R1 R6 L “ CR3 R6 1 + 1+ provided “ + 1+ R1 R4 R4 R5 R3 R5 (2.4) The process of deriving an FTFN/OFA based FI circuit corresponding to this circuit is shown in Fig. 2.14a to c is self-explanatory. It is, however, interesting to note that from the FI circuit of Fig. 2.14c, three additional FI circuits can be derived as follows: (1) An equivalent of the circuit of Fig. 2.14c can be generated invoking the following theorem: Theorem 2.2. If a 2-port active-RC network N1 containing floating two terminal passive elements, floating nullators and floating norators has short circuit admit- tance matrix 1 −1 [Y1 ] “ y(s) (2.5) −1 1 4 In [13] 32 equivalent FI realizations were stipulated using a two-op-amp FTFN available then. 44 R. Senani et al. a b c d e f Fig. 2.14 (a–c) Method of transformation of a lossless grounded inductor into a FI using an FTFN or OFA [7, 13]. (d–f) Three other equivalent FIs having same value of realized inductance under the same condition of realization then if it is transformed into another network N2 by interchanging all nullators and norators, the transformed network has the same Y-matrix. By applying Theorem 2.2 to the FI circuits of Fig. 2.14c, the resulting second equivalent FI turns out to be as shown in Fig. 2.14d. (2) Owing to simulating a lossless inductance employing a single floating capacitor, the two port network of Fig. 2.14c can be looked upon as a floating gyrator with terminals 1 and 2 constituting the input port and terminals 3 and 4 (between which the capacitor is connected) constituting the output port. Thus, gyrator action is available even if the input and the output ports are transposed i.e. the capacitor is connected between terminals 1 and 2 and the floating impedance is looked between 3 and 4. This results in the third equivalent FI shown in Fig. 2.14e. (3) Finally, the fourth and the last additional equivalent FI is obtained by swapping the nullator and norator in the circuit of Fig. 2.14f in accordance with Theo- rem 2.2. Lastly, it must be pointed out that twelve additional lossless FI circuits, each employing only a single FTFN, are similarly realizable starting from the lossless grounded inductance circuits of Orchard-Wilson [41], Schmidt-Lee [42] and Ram- sey [43] by following the above outlined procedure. It may be mentioned that the basic ideas outlined above had been elaborated by Senani in [7] and [13]. 2 Nullors, Their Bipolar and CMOS Implementations... 45 a b R2 R3 R1 R3 R4 R1 R3 R4 C R2 R1 R4 C x w R2 C y z R2 R2 2 R1 1 1 2 x w R3 R1 NFTFN C y z R3 R4 R4 C 1' 2' 1' 2' Fig. 2.15 Conversion of an op-amp based single resistance controllable GI into FTFN-based FI of the same form: (a) Floating series RL, (b) floating parallel RL 2.5.4 Single-Resistance-Tunable Lossy Floating Inductance Simulation Using Only a Single FTFN The technique explained in Sect. 2.5.1 above opens the way for evolving a large number of floating impedance circuits starting from various known grounded GDPI circuits. Figure 2.15 shows the conversion of a simulated single resistance tunable grounded lossy inductance into a FI of the same value. Starting from the grounded inductance circuit of [45], its nullor model is drawn, a two port is created by ungrounding all grounded elements/terminals where from finally, a circuit simulating the same kind of impedance in floating form using FTFN is derivable (see Fig. 2.15). Thus, GDPI using an op-amp as well as the derived FI using an FTFN both simulate series RL impedance with inductance value given by R1 R2 R4 Rs “ R1 + R2 + · Ls “ CR1 R2 1 + (2.6) R3 R3 where from it is seen that LS is independently adjustable by R4 which does not appear in the expression for Rs . A single FTFN-based floating parallel RL impedance possessing single- resis- tance controllability of inductance value is similarly derivable from the tunable grounded parallel RL impedance circuits of [45] is shown in Fig. 2.15b for which equivalent resistance Rp and inductance Lp are given by R3 −1 1 1 1 R3 “ + + · L p “ (CR1 R2 ) 1 + (2.7) Rp R1 R2 R1 R2 R4 46 R. Senani et al. 2.6 Use of Nullors in Deriving Equivalent Circuits of Single-Resistance-Controlled Oscillators (SRCO) Although there have been several efforts in synthesizing oscillators using FTFNs as active elements, for instance, see [46–48] and the references cited therein, the potential of FTFNs has been particularly appealing in generating oscillator- equivalences which quite often have resulted in alternative oscillator topologies possessing properties not available in the parent circuits. In this section, we will, therefore, focus only on this particular application of FTFNs in the domain of oscillator design. A general theory of deriving equivalent forms of op-amp RC sinusoidal oscillators using the formalism of nullors was presented earlier in [22]. This theory is based upon the following theorems: Theorem 2.3. Suppose there is a sinusoidal oscillator N which employs m nullators, m norators and an arbitrary number of passive resistors and capacitors. If N is transformed into another circuit N∗ by interchanging all nullators and norators then N∗ has the same characteristic equation (CE) as that of N. Theorem 2.4. Corresponding to any RC-nullor oscillator having n nodes (excluding the ground node which is taken “external” to the circuit) and consisting of m nullors along with an arbitrary number of passive resistor and capacitors, there are 2n grounded nullor-RC equivalent oscillator circuits having the same CE since in an oscillator, because there is no external input, the ground node can be chosen arbitrarily without affecting the CE. In [22] it was shown that the classical Wein bridge oscillator has ten equivalent forms.5 This number was further increased in [51] to sixteen by considering the junction of the series RC branch as another node. It was shown in [22] that some of such additional realizations are likely to have some interesting properties not available in the original circuit. In the following, we show how applying the above theorems on an existing SRCO we can derive a number of equivalents having same characterization and that some of the derived equivalents indeed have new and interesting properties not available in the original circuit. Let us now consider the single op-amp RC SRCO of [52] reproduced here in Fig. 2.16. This oscillator is characterized by the following condition of oscillation (CO) and frequency of oscillation (FO): g f 1f 1 + R3 +R4 R4 2R5 e 2π C R 1 “ (with C1 “ C2 “ C) and f0 “ (2.8) R3 R2 R2 R3 5 It is worthwhile to point out that the theory of [22] was usefully extended to derive a class of two FTFN-based SRCOs employing a minimum possible number of resistors in [49]. Yet another two FTFN-based GC SRCO was presented in [50]. 2 Nullors, Their Bipolar and CMOS Implementations... 47 Fig. 2.16 Senani’s SRCO c 1979 (adapted from [52] R6 IEEE) C1 R2 C2 - R3 + + Vout R1 R4 R5 - a b C1 C1 R2 R2 C2 C2 2 3 2 3 R3 5 R3 1 5 1 R4 R4 R4 R5 R1 R1 4 4 Fig. 2.17 (a) A nullor model of the SRCO of Fig. 2.16. (b) An alternative nullor model of the same circuit From the above it is seen that CO is controllable independently by R5 where as FO is independently controllable by R1 . A nullor model of this SRCO, with ground node excluded, is shown in Fig. 2.17a. Figure 2.17b shows an alternative nullor model having the same CE obtained by applying Theorem 2.3. Since each model contains five nodes it follows from Theorem 2.4 that for each model, ground node can be selected in five different ways thereby leading to a total of ten equivalent SRCOs having the same CE. It may be noted that only four of these would be realizable with a normal op-amp while the remaining six require an FTFN (Fig. 2.18). Two of the new SRCOs generated by this methodology (resulting from treating node 1 as ground) employ grounded capacitors as preferred for IC implementation and are particularly note worthy since this feature was not present in the original circuit of Fig. 2.16. Also, four of the quoted ten circuits can provide explicit current outputs-again a feature which was not there in the original circuit. 48 R. Senani et al. Fig. 2.18 (a) FTFN-based a b grounded capacitor version of R5 R5 the SRCO of Fig. 2.16. (b) An alternative R2 R2 FTFN-based grounded y w z y capacitor version of the 1 1 x z w x SRCO of Fig. 2.16 C2 C4 R4 R4 C1 C1 R3 R3 R1 R1 Thus, the examples in [22, 51] and the one shown here prove the potential of FTFNs in generating new oscillator configurations possessing interesting properties, beyond their normal use as active elements in oscillator realization as demonstrated in [46–48]. 2.7 Use of FTFN in Realization of Universal Biquad, Fully Differential and Inverse Filters In the area of active filter design, the FTFNs have been shown to be very useful building blocks in realizing universal biquad filters, inverse filters and fully differential biquad filters. A brief account of some important works in this direction is provided in the following. 2.7.1 Universal Current-mode Biquad Although a number of attempts have been made by various researchers in evolving universal biquads in current mode (CM), trans-admittance mode or so the called mixed-mode using a variety of building blocks, a particularly simple CM biquad with a minimum possible number of passive elements (namely only four) along with a minimum possible number of FTFNs to provide three explicit current outputs was proposed by Cicekoglu [53] and is reproduced here in Fig. 2.19. Selecting Y1 “ 1/R1 , Y2 “ sC2 , Y3 “ 1/R3 , and Y4 “ sC4 , the circuit realizes a high pass (HP) response at i01 and a band pass (BP) response at i02 with relevant parameter given by c c 1 R3C4 ω0 “ , and Q0 “ (2.9) R1 R3C2C4 R1C2 2 Nullors, Their Bipolar and CMOS Implementations... 49 Fig. 2.19 Current-mode Y4 Y2 biquad using FTFN (adapted iin c 2001 IEEE) from [53] y w y w y w 1 i01 2 i02 3 x z x z x z Y1 Y3 Fig. 2.20 Fully-differential A CM building block (adopted Iin I'o from [54]) Z1 Z2 I'in Z1 Io B On the other hand, by selecting Y1 “ sC1 , Y2 “ 1/R2 , Y3 “ sC3 , Y4 “ 1/R4 , the same circuit realizes a low pass (LP) response at i01 and a BP response i02 with relevant parameters being given by c c 1 C1 R2 ω0 “ and Q0 “ (2.10) R2 R4C1C3 C3 R4 The advantageous features of this circuit are the availability of ideally zero input resistance, ideally infinite output resistances (both expected from an ideal CM filter) together with the use of a minimum possible number of passive elements. 2.7.2 Fully Differential CM Biquad As another example of the potential of the nullors, we next demonstrate their use in the realization of a fully differential filter. There has been lot of interest in literature in realizing fully differential filters in both VM and CM because of their capability of eliminating common-mode noise. In the following, we discuss a nullor-based approach for constructing a fully differential CM building block which can be used to realize a fully differential CM universal filter in a configuration employing two fully differential integrators and a fully differential summer with complimentary CM outputs. A fully differential CM building block is shown in Fig. 2.20 and is characterized by i0 “ −i′0 “ Z1 /Z2 (iin − i′in ). Thus, depending upon the choice (resistive/capacitive) of the impedances Z1 and Z2 , this block can realize fully differential scalar, integrator or differentiator. With both impedances as resistors and summing nodes created at nodes “a” and 50 R. Senani et al. a CCII(-) b y CCCII(+) iin z y x -io iin z C1 C1 x -i o R1 CCCII(-) CCII(-) x io x io -iin -iin C1 z C1 z y y CCII-based fully differential CM integrators CCCII- based fully differential CM integrators c d i2 i3 iin io ii C1 Gm = 1 io = i1+i2+i3 R2 -iin C1 -io −io= (i1+i2+i3) -i1 -i2 -i3 DOTA based fully differential CM integrators Summer with complementary CM outputs Fig. 2.21 Various realizations of the fully differential CM integrators (adapted from [54]) “b” the configuration can realize fully differential CM summer. We now show that, as widely understood, nullors are indeed useful in realizing and unifying circuit structures using all such different kinds of active elements which can be modeled in terms of nullors. In the present case, the nullor-based configuration of Fig. 2.20 leads to a number of different practical implementations, three of which using CCII−, CCCII+ and differential output OTA (DOTA) are shown in Fig. 2.21. It is worthwhile to mention that in all cases, the internal hardware of the employed building blocks can be easily modified to facilitate multiple and com- plementary outputs which should be useful in interconnecting two or more of such configurations as well as to provide feedback paths and summations as needed for either biquad realization or higher order filter designs. Alternatively, differential summer can also be realized by the nullor-based structure of Fig. 2.21d and an exemplary configuration of a fully differential CM universal filter obtained in this manner is shown in Fig. 2.22 which realizes LP, BP, HP outputs where from HP and LP outputs can be combined to realize a band stop filter while HP and BP (inverting) can be combined to realize an all pass filter without requiring any component- matching conditions other than the equality of capacitors (which is prevalent in almost all earlier fully differential filter structures as well). A notable property of the circuit of Fig. 2.22 is that bandwidth and pole frequency can be orthogonally tuned by R1 and R2 respectively: the gain is fixed at unity in all the cases. It has been shown elsewhere [54] that this approach can also be extended to the design of higher order filter. 2 Nullors, Their Bipolar and CMOS Implementations... 51 Iin x z- y z- z+ y z- y z- x z- IHP IBP x z+ 2C1 ILP 2C2 R1 R2 2C1 2C2 I'LP I'HP I'BP x z+ y z- x z- z+ y z- x z- y z- I'in Fig. 2.22 A fully differential CM universal filter (adapted from [54]) The three transfer functions realized by the circuit of Fig. 2.22 are given by IBP s C11R1 ILP 1 IHP s2 s 1 C1C2 RR2 “− : “ ; “ where Δ “ s2 + + Iin Δ Iin Δ Iin Δ C1 R1 C1C2 RR2 (2.11) 2.7.3 Design of CM Inverse Filter In the area of filter design another interesting application of FTFNs has been in the derivation of the so-called “inverse filters” [55]. Out of the various approaches of designing inverse filters published earlier, we present here a specific procedure of realizing a current mode FTFN-based inverse filter from a given op-amp RC-based filter based upon [55] which consists of the following steps: (1) Obtain a nullor model of the given op-amp RC filter by replacing the op-amp by nullator-norator pair, (2) swap the driving source and the norator in the above model, (3) apply RC:CR dual transformation on the model of the previous step, (4) obtain the final inverse filter by replacing the nullors with FTFNs. An exemplary inverse filter generated by using the above steps, is demonstrated in Fig. 2.23. 52 R. Senani et al. R1 R2 C1 + V0 C2 C1 R1 R2 V0 V0 R1 R2 - R + F + + C2 RF RF + Vin Vin C2 RG C2 Vin RG RG RF I0 RF x R2 I0 x z w z RG y w RG C2 L Iin C2 Iin y R1 C1 Ri C1 c 1999 IEE) Fig. 2.23 Design of an inverse filter using FTFN (adapted from [55] The final CM inverse function realized by FTFN circuit of Fig. 2.23 is ⎡ ⎤−1 I0 ⎣ k (R1 R2C1C2 ) “ ⎦ (2.12) Iin s2 + s 1 + 1 + 1−k + 1 R1C1 R2C1 R2C2 R1 R2C1C2 where k “ 1+ (RF /RG ). 2.8 Systematic Synthesis of Active RC Circuits Using Nullors Haigh and co-workers [56] have carried out pioneering work on the systematic synthesis of active RC networks using nullors. While it is difficult to summarize the entire body of their work in a chapter of limited length, we outline here an exemplary synthesis of an immittance inverter circuit which evolves in a systematic way by expansion of the relevant port admittance matrices such that the circuit topology emerges naturally from the synthesis procedure. We start from the common knowledge that an immittance inverter can be synthesized by a parallel back-to-back connection of a positive voltage controlled current source (VCCS) and a negative VCCS characterized by the two port 0 0 0 0 admittance matrices: and respectively. G1 0 −G2 0 Taking the first matrix, we move the element G1 to the main diagonal so that it can describe a grounded resistor. This is accomplished by adding a blank row 3 and column 3, then moving G1 term from column 1 to column 3 and from row 2 to row 3 and then adding a nullator between nodes 1 and 3 and a norator between nodes 2 and 3 in order to allow the G1 term to move to the 3, 3 position, as shown in the following equation: 2 Nullors, Their Bipolar and CMOS Implementations... 53 2 3 y 1 2 1 1 CCII(-) z 2 3 3 x G1 G1 G1 Fig. 2.24 The synthesis of noninverting VCCS and its FET and CCII− realizations (adapted from [56] c 2005 Springer) The circuit realizations corresponding to the last matrix of the above equation are shown in Fig. 2.24. For the negative VCCS, we note that a negative conductance can be identified with one of the two off- diagonal negative elements describing a non-grounded conductance. The description of non-grounded conductance needs two rows or two columns. Thus, we introduce two blank rows and two blank columns, thereby introducing two new nodes 3 and 4 in the matrix. Now connecting a nullator from node 3 to node 1 and a norator from node 4 to 2 will permit—G2 to move to position 4, 3. Since an indefinite admittance matrix must have sum of each row and each column equal to zero hence, row 0 and column 0 should contain terms G2 , −G2 and G2 , as shown. Now connection of a norator between nodes 3 and 0 will allow the row 0 term to be brought to row 3. Similarly, connection of nullator between nodes 4 and 0 will allow column 0 term to be brought to column 4 as shown. The final admittance matrix in 54 R. Senani et al. 1 y 1 CCII(-z) 3 x 3 4 3 1 2 G2 G2 G2 4 2 4 x CCII(-) z 2 y Fig. 2.25 Synthesis of inverting VCCS using nullor MOSFET and CCs (adapted partly from [56] c 2005 Springer) Fig. 2.26 Synthesis of an immittance inverter using nullors, MOSFET and CCIIs (In the CCIIs c 2005 Springer) circuits, all three CCIIs could also be taken as CCII+ (adapted partly from [56] the above equation shows the connections of two nullors and a floating conductance representing the inverting VCCS, the final circuit for which is shown in Fig. 2.25 along with its FET and CCII− based realizations (not included in [56]). Finally, the complete nullor representation of the immittance inverter and its FET- and CCII−based realizations are shown in Fig. 2.26. 2.9 Current Mirror and Voltage Mirror as Two New Pathological Elements While a CCII− can be represented by a three terminal nullor without requiring any resistors, however, a CCII+ cannot be realized by nullators and norators only and does require at least two resistors see Fig. 2.4. This difficulty motivated Awad and Soliman [57, 58] to propose two new pathological elements namely the CM and VM which are basically used to represent active devices with current or voltage reversing properties. A CM is a two port network element for which V1 and V2 2 Nullors, Their Bipolar and CMOS Implementations... 55 Fig. 2.27 The symbols of I1 I1 CM and VM (adapted from 1 1 [58] c 2002 Springer) V1 VM CM V2 2 2 I2 I2 a b Y Y CCII- CCII+ Ix Iz Ix Iz X Z- X Z+ c d Y Y ICCII- ICCII+ Ix Iz Ix Iz X Z- X Z+ Fig. 2.28 Realization of various building blocks using VM–CM pair. (a) CCII−. (b) CCII+. (c) ICCII−. (d) ICCII+ (adapted from [59] c 2010 John Wiley & Sons) are arbitrary and I1 “ I2 and they are also arbitrary. The VM is a lossless two- port network element characterized by V1 “ −V2 and I1 “ I2 “ 0. The symbolic notations of the CM and VM are shown in Fig. 2.27. Saad and Soliman in 2010 [59] demonstrated that CM-VM pair constitutes an universal active element since it is capable of representing an op-amp as well as all the four types of current conveyors namely CCII−, CCII+, Inverting CCII− (ICCII−) and inverting CCII+ (ICCII+) without using any resistors (see Fig. 2.28). Soliman and his co-worker have employed nullator–norator–CM–VM in the systematic synthesis of analog circuits, however, for a detailed discussion of these the reader is referred to [60] and the references cited therein. 56 R. Senani et al. 2.10 Current Trends and Directions for Future Research Although about a dozen different CMOS FTFN structures have been reported in literature, a perfect implementation of nullor which can be produced as an IC to take advantage of its universality6 is still awaited. It is also observed from a review of literature that applications of nullors have not been explored as exhaustively as these have been evolved using other devices like operational amplifiers, OTAs, current conveyors and current feedback amplifiers, etc. A good mixed mode universal filter realized with FTFNs providing most of the desirable properties is yet to be evolved and appears to be a worthwhile problem for future investigations. The more recent works on the utilization of nullors include creation of general admittance matrix stamps for the operational trans-resistance amplifier (OTRA) current output amplifier (COA) [63]. Work is also being conducted by Tlelo- Cuautle and his co-workers [64] on the pathological element based active device modeling and their applications to symbolic analysis. The concept of nullors has also been employed in developing systematic synthesis procedure for realizing CFs and VMs [65]. Thus, continued work on nullors is currently dominantly motivated by the evolution of systematic synthesis procedures using nullator–norator–CM–VM ele- ments for realizing impedance converter inverters, biquad filters and oscillators and it is expected that nullors (or FTFNs) in conjunction with CM-VM pair will continue to find more and more interesting applications in circuit synthesis and design, in days to come. References 1. Carlin HJ, Youla DC (1961) Network synthesis with negative resistor. Proceeding IRE 49:907–920 2. Carlin HJ (1964) Singular network elements. IEEE Trans Circuit Theory 11:67–72 3. Kumar P, Senani R (2002) Bibliography on nullor and their applications in circuit synthesis and design. Analog Integr Circuits Signal Process 33:65–76 4. Nordholt EH (1982) Extending op-amp capabilities by using a current-source power supply. IEEE Trans Circuits Syst 29:411–412 5. Steveanson JK (1984) Two-way circuits with inverse transmission properties. Electron Lett 20:965–967 6. Huijsing JH (1990) Operational floating amplifier. IEE Proc 137:131–136 7. Senani R (1987) A novel application of four-terminal floating nullor. IEEE Proc 75:1544–1546 8. Cam U, Kuntman H (1999) CMOS four terminal floating nullor design using a simple approach. Microelectron J 30:1187–1197 6 It is worth pointing out that it has been shown in [61] that there are nine distinctly different analog building blocks which can be said to be “universal” in a generic sense. Also, it may be noted that as pointed out in [40] and [62], the so called PFTFN or FTFN+-(based on norator +) are strictly speaking not floating nullors and hence, are not included in this chapter. 2 Nullors, Their Bipolar and CMOS Implementations... 57 9. Cam U, Toker A, Kuntman H (2000) CMOS FTFN realization based on translinear cells. Electron Lett 36:1255–1256 10. Cam U, Kuntman H (2000) A new CMOS realisation of a four terminal floating nullor (FTFN). Int J Electron 87:809–817 11. Alzaher H, Ismail M (2002) A CMOS fully balanced four terminal floating nullor. IEEE Trans CAS-I: Fundam Theory Appl 49:413–424 12. Mitra SK (1969) Analysis and synthesis of linear networks. John Wiley & Sons, Inc. New York 13. Senani R (1987) Generation of new two amplifier floating inductors. Electron Lett 23:1202–1203 14. Higashimura M, Fukui Y (1988) Novel method for realizing higher-order immittance function using current conveyors. IEEE Int Symp CAS 3:2677–2680 15. Higashimura M, Fukui Y (1988) Realisation of impedance function using current conveyors. Int J Electron 65:223–231 16. Walter N, Cox Jr, Su KL, Woodland RP (1971) A floating three terminal nullor and the universal impedance converter. IEEE Trans Circuit Theory 18:399–400 17. Huijsing JH (1993) Design and applications of the operational floating amplifier (OFA): the most universal amplifier. Analog Integr Circuits Signal Process 4:115–129 18. Mahmood SA, Soliman AM (1998) The differential difference operational floating amplifier: a new block for analog signal processing in MOS technology. IEEE Trans CAS-II: Analog Digital Signal Process 45:148–158 19. Hanspeter Schmid (2003) Comments on “A CMOS Fully Balanced Four-Terminal Floating Nullor”. IEEE Trans CAS-I: Fundam Theory Appl 50:1601 20. Higashimura M (1991) Realization of current-mode transfer function using four terminal floating nullor. Electron Lett 22:170–171 21. Normand G (1986) Floating impedance realization using a dual operational mirrored amplifier. Electron Lett 22:521–522 22. Senani R (1994) On the equivalent form of single op-amp sinusoidal RC oscillators. IEEE Trans CAS-I: Fundam Theory Appl 41:617–624 23. Huijsing JH, Dekorte J (1977) Monolithic nullor-A universal active network element. IEEE J Solid State Circuits 12:59–64 24. Tangsrirat W, Unhavanich S, Dumawipata T, Surakampotorn W (2001) FTFN with variable current gain. Electric Electron Technol 1:209–212 25. Jiraseri-amornkun A, Chipipop B, Surakampontorn W (2001) Novel translinear-based multi- output FTFN. In: Circuits and Systems, ISCAS Sydney, NSW, Australia 26. Antoniou A (1969) Realization of gyrator using operational amplifier and their use in RC- active-network synthesis. Proc IEE 116:1838–1850 27. Senani R (1986) On the realization of floating active elements. IEEE Trans CAS 33:323–324 28. The LO, Yanagisawa Y (1977) Some new lossless floating inductance circuits. Proc IEEE 66:1071–1072 29. Riordan RHS (1966) Simulated inductors using differential amplifier. Electron Lett 3:50–51 30. Cabeza R, Carlosena A (1997) Analog universal active device: theory, design, applications. Analog Integr Circuits Signal Process 12:153–168 31. Cam U, Cicekogulu O, Kuntman H (2001) Novel lossless floating imittance simulator employing only two FTFNs. Analog Integr Circuits Signal Process. 29:233–235; also see ibid Gandhi G (2002) comments on Novel lossless floating imittance simulator employing only two FTFNs. 32:191 32. Pauker VM (1970) Equivalent networks with nullors for positive immittance inverter. IEEE Trans Circuit Theory 17:642–645 33. Senani R (1980) New tunable synthetic floating inductors. Electron Lett 16:382–383 34. Pal K (1980) Novel floating inductance using current conveyor. Electron Lett 17:638–639 35. Pal K (1981) New inductance and capacitance floating scheme using current conveyor. Electron Lett 17:807–808 36. Singh V (1981) Active-RC single resistance controlled lossless floating inductance simulation using a single grounded capacitor. Electron Lett 17:920–921 58 R. Senani et al. 37. Senani R (1982) Novel lossless synthetic floating inductor employing a grounded capacitor. Electron Lett 18:413–414 38. Nandi S, Jana PB, Nandi R (1983) Floating ideal FDNR using current conveyors. Electron Lett 19:251–252 39. Paul, AN, Dey, AN, Patranabis D (1983) Floating NIC without constraint and its applications. IEEE Trans Circuits Syst 30:181–183 40. Senani R (1988) Floating immittance realization using nullor approach. Electron Lett 24:403–404 41. Orchard HJ, Willson AN (1974) New active gyrator circuit. Electron Lett 10:261–262 42. Schmidt CE, Lee MS (1975) Multipurpose simulation network with a single amplifier. Electron Lett 11:9–10 43. Ramsey WT (1978) High pass and band pass filter using a new single amplifier simulated inductor. IEE J Electron CAS 2:79–85 44. Horn P, Moschytz GS (1979) Active-RC single op-amp design of driving point impedances. IEEE Trans CAS 26:22–30 45. Senani R (1982) Author’s reply on Comments on new canonic active RC realizations of grounded and floating inductors. Proc IEEE 70:101–103 46. Abuelma’atti MT, Al-Zaher HA (1999) Current-mode sinusoidal oscillators using single FTFN. IEEE Trans CAS-II: Analog Digital Signal Process 46:69–74 47. Cam U, Toker A, Cicekoglu O, Kuntman H (2000) Current-mode high output impedance sinusoidal oscillator configuration employing single FTFN. Analog Integr Circuits Signal Process 24:231–238 48. Liu SI, Liao YH (1996) Current-mode sinusoidal oscillator using single FTFN. Int J Electron 81:171–175 49. Abuelma’atti MT, Al-Zaher HA (1998) Current-mode sinusoidal oscillator using two FTFNs. Proc Natl Sci Council ROC(A) 22:758–761 50. Bhaskar DR, Senani R (2005) New FTFN-based grounded-capacitor SRCO with explicit current-mode output and reduced number of resistors. Int J Electron Commun (AEU) 59:48–51 51. Singh V (2001) Realization of operational floating amplifier based equivalent forms of the conventional 1-op-amp-based sinusoidal oscillators. IEEE Trans CAS-I: Fundam Theory Appl 48:377–381 52. Senani R (1979) New canonic sinusoidal oscillator with independent frequency control through a single grounded resistor. Proc IEEE 67:691–692 53. Cicekoglu O (2001) Current mode biquad with a minimum no of passive elements. IEEE Trans CAS-II: Analog Digital Signal Process 48:221–222 54. Kumar P (2003–08) FTFNs and their applications in circuit synthesis and design. PhD Thesis, University of Delhi (India) (Supervised by Raj Senani) 55. Chipipop B, Surakampontorn W (1999) Realization of current mode FTFN-based inverse filter. Electron Lett 35:690–692 56. Haigh DG, Tan FO, Papavassiou C (2005) Systematic synthesis pf active-Rc circuit building blocks. Analog Integr Circuits Signal Process 43:297–315 57. Awad IA, Soliman AM (1999) Inverting second generation current conveyor: the missing building blocks, CMOS realizations and applications. Int J Electron 86:413–432 58. Awad IA, Soliman AM (2002) On the voltage mirrors and current mirrors. Analog Integr Circuits Signal Process 32:79–81 59. Soliman AM, Saad RA (2010) The voltage-mirror current mirror pair as universal element. Int J Circuits Theory Appl 38:787–795 60. Soliman AM (2011) Generation of Kerwin–Huelsman–Newcomb biquad filter circuits using nodal admittance matrix expansion. Int J Circuits Theory Appl 39:697–717 61. Shmidt H (2000) Approximating the universal active element. IEEE Trans CAS-II: Analog Digital Signal Process 47:1160–1169 62. Soliman AM (2010) On the four terminal floating nullor (FTFN) and the operational mirror amplifier (OMA). J Active Passive Electron Devices 5:209–219 2 Nullors, Their Bipolar and CMOS Implementations... 59 63. Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E (2010) Generalized admittance matrix models of OTRAs and COAs. Microelectron J 41:502–505 64. Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E (2011) Pathological element-based active device models and their application to symbolic analysis. IEEE Trans Circuits Syst 1 58:1382–1395 65. Tlelo-Cuautle E, Duarte-Villasenor MA, Guerra-Gomez I (2008) Automatic synthesis of VFs and VMs by applying genetic algorithms. Circuits Syst Signal Process 27:391–403 Chapter 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations and Their Variants R. Senani, D.R. Bhaskar, S.S. Gupta, and V.K. Singh 3.1 Introduction The current-mode techniques have given way to a number of important analog signal processing/signal generating circuits as is evident from a vast amount of literature on current-mode circuits published over the past 35 years. Due to the advances made in integrated circuit (IC) technology circuit designers have quite often exploited the potential of current-mode analog techniques for evolving elegant and efficient solutions to several circuit design problems. As a consequence, the current-mode approach has often been claimed to provide one or more of the following advantages in analog circuit design: higher frequency range of operation, lower power consumption, higher slew rates, improved linearity, better accuracy as well as reduced component-count and elimination of passive component-matching requirements. R. Senani () Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India e-mail: dr [email protected] D.R. Bhaskar Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, India e-mail: [email protected] S.S. Gupta Department of Industrial policy and promotion, Ministry of Commerce and Industry, New Delhi, Government of India e-mail: [email protected] V.K. Singh Department of Electronics Engineering, Institute of Engineering & Technology, Lucknow, UP, India e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 61 DOI 10.1007/978-1-4614-1383-7 3, © Springer Science+Business Media New York 2013 62 R. Senani et al. 3.2 The Evolution of Current Conveyors The most popular current-mode building blocks have been, undoubtedly, the current conveyors (CC) introduced by Smith and Sedra. The first generation current conveyor (CCI) was introduced in 1968 [1] and was later refined to second generation current conveyor (CCII) by Sedra and Smith in 1970 [2]. Because of the extensive work done by researchers for more than four decades on the hardware implementation and applications of CCs, coupled with the commercial availability of a number of IC CCs (such as PA630A from Phototronics Corporation of Canada, CCII01 from LTP Electronics, AD844 from Analog Devices Inc. and more recently, MAX4198 from Maxim Integrated Products), the CCs have emerged as an important class of active building blocks with properties that enable them to rival the traditional voltage mode op-amp (VOA) in a wide range of applications. 3.3 The Current Feedback Op-amp A closely related building block to CCs, which has received significant attention for over two decades now, has been the so-called “Trans-impedance op-amp”, more popularly known as the “Current Feedback Op-Amp” (CFOA) [3–7]. CFOAs fabricated in bipolar technology exhibit an almost constant bandwidth irrespective of the closed loop gain in contrast to the VOAs. The slew rate attained is also very high, typically in excess of 2,000 V/µs as opposed to merely 0.5 V/µs in case of traditional µA741 type VOA. Although the theoretical basis of many of these current feedback designs had been known earlier, attention on these building blocks has been largely due to the recent developments in complementary bipolar technology. The translinear circuit principle, first introduced by Barrie Gilbert in 1975 [8], which exploits the logarithmic relationship between the base-emitter voltage and collector current in bipolar transistor to create a variety of novel analog circuits, has been used for the evolution of CFOAs and many other high performance analog circuits. From the view point of internal architecture, a CFOA, such as the popular AD844, is essentially a translinear second generation current conveyor (CCII+) followed by a translinear voltage buffer (see Fig. 3.1 (a) for the block diagram of the internal circuit and (b) for a typical bipolar implementation). Thus, CFOA AD844 from Analog Devices is a 4-terminal building block characterized by the following terminal equations: iy “ 0, vx “ vy , iz “ ix and vw “ vz . (3.1) 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 63 a b +V y IB CCII+ 1 w y x z w iz IB x z -V Fig. 3.1 Current feedback operational amplifier (a) the internal constituents, (b) bipolar imple- mentation of AD844 type CFOA (adapted from [9]) 3.4 CFOAs Overcome Several Limitations of VOAs CFOA AD844 was introduced by Analog Devices around 1985, however, it caught the attention of circuit designers only after 1990 or so and subsequently, it was demonstrated [3–7] that it offers the following advantages in analog circuit design: (1) Using CFOAs, various functional circuits can be realized with a minimum number of passive components without any component-matching (these advantages are particularly noticeable in case of realization of impedance converters/inverters, non-inverting/inverting differential integrators/differentiators, VCCS, instrumenta- tion amplifiers, universal biquad filters and single resistor-controlled oscillators and many others). (2) CFOAs exhibit much higher slew rates (in excess of 2,000 V/µs) in contrast to VOAs (0.5 V/µs). (3) Gain and bandwidth can be set independently; amplifiers with variable gain but constant bandwidth become possible and (4) higher operational frequency range possible (as compared to conventional op-amps). 3.5 Why CFOA has a Higher Slew Rate? In a typical internally-compensated op-amp architecture [6], the input stage is composed of a differential transconductance amplifier which exhibits a tanh- characteristic between the output current and the differential input voltage Vid since it is given by Iout “ IB tanh(Vid /2VT ) resulting in saturation of the current to a maximum value of IB for larger values of Vid . Since the charging current to the compensating capacitor Cc is provided by the output current of the input transconductance stage, the slew rate which is decided by the maximum value of charging current is, therefore, limited to ±IB , the maximum slew rate is IB /CC . On the other hand, in case of a typical CFOA architecture, the input stage is a mixed translinear cell in which the characteristic between the differential input (Vy – Vx ) turns out to be a Sinh-characteristic given by Iout “ 2IB sinh{(Vy −Vx )/VT } thereby the output current goes on increasing indefinitely (theoretically up to infinity) when differential voltage input becomes large [6]. Since in the large differential input 64 R. Senani et al. case, the maximum charging current to the compensating capacitor is, in this case, theoretically infinite, this leads to a theoretically infinite slew rate. In practice, however, slew rates of the order of 2,000–4,000 V/µs are easily achievable. Although CFOAs may not be very appropriate for applications which require low input offset voltage, good CMRR, low noise and high PSRR, nevertheless, they have been proved to be quite versatile for applications which require high slew rates, low distortion or the ability to set gain and bandwidth independently. Furthermore, there are numerous applications of CFOAs which can either not be performed with VOAs or which can be carried out more efficiently with CFOAs using lesser number of external passive components, with no component-matching required and with better tunability properties etc. The major focus of this chapter will, therefore, be on presenting only such applications of CFOAs, which exhibit one or more of the above-mentioned significant advantages. 3.6 Applications of the CFOAs Numerous applications of CFOAs in the design of linear as well as nonlinear circuits have so far been evolved. Since well over one hundred publications have appeared on the applications and implementation of CFOAs during the past two decades, it is not feasible to even include references to all these works due to limitations of space. Due to this reason, we are constrained to include here only some representative application circuits and hardware implementations, which, in our opinion have some novelty and ingenuity in their architecture. Some key applications to illustrate the versatility of CFOAs now follow: 3.6.1 Design of Amplifiers With Variable-gain but Constant-bandwidth A conventional op-amp-based instrumentation amplifier requires as many as three op-amps along with seven resistors and suffer from the drawback of gain-bandwidth conflict. By contrast, with CFOAs, only two CFOAs and a bare minimum of only two resistors are enough (see Fig. 3.2). The instrumentation amplifier of Fig. 3.2 can be considered to be a CFOA- version of Wilson’s CCII-based circuit [10]. Considering the finite input resistance looking into terminal X of the CFOA as rx and taking parasitic output impedance looking into terminal Z as a resistance RP in parallel with capacitance CP , the maximum gain and 3-dB bandwidth of this circuit are found to be: V0 R2 1 1 1 “ and BW “ + (3.2) (V1 − V2 ) R1 + 2rx C p R2 R p 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 65 Fig. 3.2 An instrumentation V1 amplifier using CFOAs y w V01 (CFOA-version of Wilson’s z CCII-based circuit) x R2 R2 V01 = (V −V ) R1 R1 1 2 x w z V2 y a b Vin y Vin x w Vo R1 z w Vo x z y R1 R2 R2 c d R2 R1 R2 Vin x R1 w Vo x z V0 y Vin z w y Fig. 3.3 Realization of non-inverting and inverting amplifiers using a CFOA from where it is seen that the bandwidth of the amplifier can be fixed at a constant value by fixing R2 while the gain can be made variable by changing R1 . In Fig. 3.3, we show two different ways of realizing non-inverting amplifiers and inverting amplifiers using a single CFOA. For all the circuits, the expressions for maximum gain and 3-dB bandwidth are given by |Gain| – (1+R2 /R1 )/(1+R2 /Rp ) and BW – (1 + R2/ Rp )/Cp R2 for R1 , R2 ≫rx , from where it is seen that in all cases, the bandwidth can be fixed by R2 whereas gain can be made variable through R1 . Note that it is not possible to make either an instrumentation amplifier or inverting/noninverting amplifier using VOAs with the decoupling of gain and bandwidth, which is achievable by the CFOA circuits presented above. 66 R. Senani et al. 3.6.2 Single Resistance Controlled Oscillators (SRCO) Interest in realizing sinusoidal oscillators using CFOAs grew when it was demonstrated by Martinez, Celma and Sabadell [11] that using a CFOA, rather than a VOA, in the classical Wien bridge oscillator configuration results in an oscillator which offers important advantages such as: (1) more accurate adjustment of oscillation frequency, (2) much wider frequency span of frequency of operation, (3) higher frequency and larger amplitudes because of much higher slew rates than VOAs and (4) lower sensitivity of the frequency to the bandwidth variation of the active element thereby resulting in higher frequency stability. This stimulated considerable interest among the researchers to extend the realization of oscillators to the more popular and important class of single resistance controlled oscillators (SRCO) with the hope that such oscillators when realized with CFOAs will, therefore, offer significant advantages over their VOA-based counterparts as well as with the hope that the 4-terminal CFOA-based new SRCOs may possess additional interesting features not available in 3-terminal VOA-based SRCOs known earlier. Consequently, there has been a widespread interest on CFOA-based SRCOs and a large number of structures using one, two or three CFOAs are now known, however, here we present only three examples which prove the above mentioned contentions to be true. Consider first a single CFOA-based SRCO proposed by Senani and Singh (from [12]; Fig. 3.7 therein) which is reproduced here in Fig. 3.4a. For the oscillator of Fig. 3.4a, the condition of oscillation (CO) and frequency of oscillation (FO) are given by d R3 C0 R3 1 1 1 “ + ; ω0 “ + (3.3) R4 C1 R0 R2 R0 R3C0C1 Thus, this circuit has the feature of providing independent control of FO by the resistor R2 and independent control of CO by R4 while using only a bare minimum of three resistors and two capacitors. This is significant, as any SRCO using a single VOA is not known to be realizable with only three resistors and two capacitors. Second example is that of realizing SRCOs employing grounded capacitors as preferred for integrated circuit implementation. Many such SRCOs have been discovered including a number of systematic methods for realizing them for instance; see [16–18]. Here we present a specific circuit proposed by Gupta and Senani [14] which is shown here in Fig. 3.4b and for the oscillator of Fig. 3.4b, CO and FO are given by c 1 R1 “ R3 f or C1 “ C2 (adjustable by R1 ); ω0 “ (adjustable by R2 ) C1C2 R2 R3 (3.4) To the best knowledge of the authors, this is the first two CFOA-GC SRCO, which provides explicit voltage mode output as well as explicit current mode output. It may be pointed out that no such SRCO with only VOAs is feasible. 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 67 a b C2 C1 a y x y z w Vo V1 w 1 R2 2 w z y x P x z Io a' R1 R2 C1 R3 R3 R4 C0 R0 c R4 R1 x w y y z w x x z zw C2 R2 y C1 R3 Fig. 3.4 SRCOs employing CFOAs (a) A single-CFOA-SRCO proposed by Senani and Singh (adapted from [12] c 1996 IET). (b) A dual-mode SRCO using both grounded capacitors proposed by Gupta and Senani (adapted from [14] c 1998 IET). (c) A fully uncoupled oscillator-cum- multifunction filter proposed by Bhaskar (adapted from [15] c 2003 Schiele and Sch¨on) As the last example, we present a three-CFOA oscillator which, apart from employing two grounded capacitors, provides fully uncoupled controls for CO and FO. (Note that CO and FO may be called fully uncoupled only when they are decided by two completely different sets of components, i.e. none of the components involved in CO are also involved in FO and vice versa.) In the oscillator of Fig. 3.4c, CO and FO are given b R1 “ R2 ; (adjustable by either or both of R1 , R2 ) c 1 ω0 “ (adjustable by either or both of R3 , R4 ) (3.5) C1C2 R3 R4 It is worth mentioning that no such fully-uncoupled-oscillator is known to be realizable using VOAs in the earlier literature. Furthermore, with feedback link broken at point “P”, and considering the input to resistor R2 , the three filter responses namely V01 , V02 and V03 are BPF, LPF and BRF respectively (for details the reader is referred to [15]). Thus, these three examples confirm the contention that using CFOAs such SRCO structures are possible the type of which cannot be realized by VOAs. 68 R. Senani et al. 3.6.3 Floating Impedance Simulation Using CFOAs It is well known that using VOAs it is impossible to simulate a floating inductance (FI) (lossless or lossy) without requiring any component matching conditions. Furthermore, for lossless FI simulation one normally requires two to four VOAs. By contrast, the first author of this chapter had demonstrated in 1979 onwards that using current conveyors it does become possible to simulate lossy floating inductance [19, 20] and as well as lossless [21] impedances respectively using no more than two current conveyors without requiring any component matching conditions. Since a CFOA contains a CCII+ followed by a voltage follower it looks intuitively possible to be able to accomplish the same properties and features using CFOAs also. In this section, a few representative configurations which can realize lossless FIs and FDNRs as well as generalized positive/negative impedance convertors/invertors (GPIC/GPII) employing CFOAs along with a minimum pos- sible number of passive components without requiring any component matching condition whatsoever are presented. Fig. 3.5 shows two circuits [7] of which that of Fig. 3.5a can be regarded as a floating GPII/GPIC configuration whereas the circuits of Fig. 3.5b is generalized configuration for realizing positive/negative floating impedances. Both the circuits are characterized by the following equation: Z3 i1 “ −i2 “ (v1 − v2 ) (3.6) Z1 Z2 From (3.6), it is obvious that a floating inductance or floating frequency-dependent- negative resistance (FDNR; an element having Z(s) “ 1/Ds2 ) by appropriate (resistive/capacitive) choice of impedance Z1 , Z2 and Z3 without requiring any component-matching and using least possible number of passive components. In Fig. 3.6 we show a floating linear voltage-controlled-impedance (VCZ) configuration [22] which can simultaneously realize VCR, VCL and VC-FDNC (frequency-dependent-negative-conductance; an element having impedance of type Z(s) “ Ms2 ) elements from the same configuration. From a straightforward analysis of the circuit of Fig. 3.6, the equivalent floating impedance realized by the circuit between terminals 1 and 2 is given by Vp2 Z1−2 “ (R1 R3 /Z2 Z4 )rDS , where rDS “ (3.7) 2IDSS (Vc − 2Vp) Linear floating positive, VCR, VCL and VC-FDNC elements can be realized from the circuit by the following choice (resistive/capacitive) of impedances Z2 and Z4 : (1) VCR: Z2 “ R2 and Z4 “ R4 ; (2) VCL: either Z2 “ 1/sC2 or Z4 “ 1/sC4 ; (3) VC-FDNC: Z2 “ 1/sC2 and Z4 “ 1/sC4 . It is interesting to mention that the various negative-valued elements correspond- ing to the equivalent impedance given in (3.7) can be obtained by the simple artifice 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 69 a Z1 w 2 Z2 z y x i2 V2 i1 x z Z3 y w w 1 y x z V1 b 1 i1 y z x w V1 x w Z2 y z Z1 Z3 x w y z 2 i2 V2 Fig. 3.5 Generalized floating impedance converters/inverters using CFOAs proposed by Senani c 1998 Schiele and Sch¨on) (adapted from [7] Fig. 3.6 Floating linear VCZ V1 configuration proposed by 1 i1 a1 a2 y z Senani, Bhaskar, Gupta and w 1 Singh (adapted from [22] R2 x c 2009 John Wiley & Sons) x w 3 Z1 z y x w 2 b1 b2 z y r0 2 y V2 4 w Z2 i2 x z r0 iD VC Z4 70 R. Senani et al. R3 x w 4 z y R1 x Vin4 R2 1 w x z 2 w x y z R4 y 3 w Vout Vin1 C1 z y Vin2 C2 Vin3 R5 Fig. 3.7 A multiple-input single output type universal biquad proposed by Nikoloudis and c 2010 Springer) Psychalinos (adapted from [13] of connecting a1 − b2 and a2 − b1 in the circuit of Fig. 3.6, thereby leading to floating negative impedance given by Z1−2 “ −(R1 R3 /Z2 Z4 )rDS (3.8) Furthermore, the grounded forms of all the above-mentioned floating impedances can be obtained by grounding either port-1 or port-2. However, in the circuit of Fig. 3.6, with port-2 grounded, CFOA2 becomes redundant (y-terminal of CFOA3 and R1 can be connected to ground directly) and as a consequence, the circuit can be simplified to have only three CFOAs while still being capable of realizing a grounded impedance: Zin “ ±(R1 R3 /Z2 Z4 )rDS (3.9) 3.6.4 Universal Biquad Filter Realizations Although a large number of CFOA-based universal biquads have been presented in literature, to demonstrate the versatility of CFOAs in these applications, we present here two examples. We first present a multiple-input single output (MISO) type universal biquad proposed by Nikoloudis and Psychalinos [13], using CFOAs, which is shown in Fig. 3.7. The expression for the output voltage in terms of input voltages is given by s2 RR45 vin3 − s RR45 1 1 R5 R2C2 vin2 − R3C2 vin4 + R1 R2 R4C1C2 vin1 vout “ (3.10) s2 + R3 RR54C2 s + R1 R2 RR54C1C2 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 71 r2 r6 x R1 Vin V x r1 w 03 V02 R2 z x y z w V01 y w x V04 z r4 y w C1 y z C2 r3 AP r7 BS r5 Fig. 3.8 A mixed-mode universal biquad proposed by Singh, Singh, Bhaskar and Senani (adapted c 2005 IEICE) from [23] The various realizations of the five filter functions are obtained as follows: Low pass filter: vin2 “ vin3 “ vin4 “ 0 and vin1 “ vin , high pass filter: vin1 “ vin2 “ vin4 “ 0 and vin3 “ vin , band pass filter: vin1 “ vin2 “ vin3 “ 0 and vin4 “ vin (non-inverting) or: vin1 “ vin3 “ vin4 “ 0 and vin2 “ vin (inverting), band stop filter: vin1“ vin3 “ vin , vin2 “ vin4 “ 0, all pass filter vin1 “ vin2 “ vin3 “ vin and vin4 “ 0. In addition, R2 “ R3 and R4 “ R5 . To the best knowledge of authors, no such op-amp RC structure is known which employs both grounded capacitor provides ideally infinite input impedance coupled with employing only four resistors and providing such versatility as exhibited by the circuit of Fig. 3.7. As another example we now present a mixed-mode universal biquad proposed by Singh, Singh, Bhaskar and Senani [23] which is shown in Fig. 3.8. A novel feature of this circuit is that universal biquad filters, in all the four possible modes, are realizable from this configuration. It may be noted that no such circuit using traditional VOAs is known to exist. (a) Voltage-mode universal biquad filter: The various voltage-mode transfer func- tions realized by this circuit are given by r2 r3 r3 s V01 /Vin “ − /D(s), V02 /Vin “ /D(s) r1 r2 R1C1 R2C2 r1 R1C1 (3.11) r3 r3 r3 V03 /Vin “ − s2 /D(s), V04 /Vin “ s2 + /D(s) r1 r1 r2 R1C1 R2C2 (3.12) 72 R. Senani et al. With the switch at BS position and choosing r2 “ r3 ; r4 “ r6 “ r7 ; one obtains: r3 s r3 V04 /Vin “ s2 − + /D(s) (3.13) r1 R1C1 r2 R1C1 R2C2 where s r3 D(s) “ s2 + + (3.14) R1C1 r2 R1C1 R2C2 Thus, the circuit realizes a LP response at V01 , BP response at V02 , a HP response at V03 , and notch and all pass responses at V04 under appropriate conditions. It is interesting to note that in all the five filters, all the three parameters of interest can be tuned through separate resistors as follows. After adjusting the bandwidth by R1 , desired ω0 can be adjusted by R2 and finally, the gain H0 of the filters (in all the five responses) is tunable by r1 . We now show how the same circuit, with simple modifications, can also realize universal biquad filters in the remaining three modes. (b) Current-mode universal biquad filters: With r1 and r7 deleted, the circuit can be converted into a universal current-mode biquad with ideally zero input impedance and ideally infinite output impedance. With an input current Iin injected into input terminal “m” and output current Iout taken out from the node “n”, the circuit can realize all the five filter functions in current mode. The general transfer function for this single-input-single-output universal current- mode filter is given by s2 1 Iout r3 r6 − C1 R1 r5 s + C1C2 R11 R2 r4 “ (3.15) Iin s2 + s C11R1 + C1C2 Rr31 R2 r2 The circuit realizes a LPF with r5 and r6 open circuited; a band pass with r6 and r4 open circuited; a high pass with r5 and r4 open circuited; a notch with r5 open circuited (along with r2 “ r4 “ r6 “ r0 (say) thereby yielding H0 “ r3 /r0 ) and finally, an all pass with r2 “ r3 “ r4 “ r5 “ r6 yielding H0 “ 1. The gains for LP, BP and HP responses are r3 /r4 , r3 /r5 and r3 /r6 respectively. In the CM biquads, LP and HP filters have only H0 controllable (though r4 and r6 respectively); in notch and AP, H0 is not tunable, however, BW and ω0 can be independently adjusted (through R1 and R2 ) respectively and finally, in BP realization, BW, ω0 and H0 , all are independently tunable (through R1 , R2 and r5 respectively). (c) Trans-admittance universal biquad filters: In this case, we retain the input resistor r1 but take the output Iout from z-terminal of the fourth CFOA. The various functions realized and their features are similar to those of case (b). (d) Trans-impedance universal biquad filters: In this case, with r1 deleted the input will be a current Iin , however, the output voltages will be V01 , V02 , V03 and V04 . The realisability conditions parameters of filters and their features are similar to those of case (a). Thus, the proposed circuit is a universal mixed-mode biquad. 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 73 Fig. 3.9 An analog divider VGA using CFOAs proposed by Liu and Chen (adapted from M3 M4 VGA+Vz [24] c 1995 IET) Vi VGA y y z w w Vo x z x M1 M2 VGA Lastly, it must be mentioned that no such mixed-mode universal biquad configura- tion is possible or known with traditional VOAs. 3.6.5 Analog Divider Using CFOAs and MOSFETs Among various non-linear applications of CFOAs evolved so far, an interesting application is that of realizing an analog divider using MOSFETs operating in triode region. One such circuit is shown in Fig. 3.9 [24]. Assuming the input signals Vx and Vy to be small permitting all MOSFETs to be operating in triode region and having same transconductance parameter K “ µS Cox (W/L) where symbols have their usual meaning, a straight forward analysis of Fig. 3.9 gives the output voltage as vy v0 “ (VGA − VGB ) (3.16) vx From where it is seen that the circuit functions as an analog divider with input signals as vx and vy where the scale factor (VGA -VGB ) is controllable through external voltages VGA and VGB . 3.6.6 MOSFET-C Biquad Using CFOAs It is well known that MOSFET-C filters using VOAs suffer from effect of the finite gain bandwidth product of the op-amps. Due to the various advantages offered by CFOAs, MOSFET-C filters using CFOAs have been investigated by several authors. Thus, using MOSFET-C lossless/lossy integrators and MOSFET-C lossless/lossy summing integrators, a variety of MOSFET-C biquad filters are realizable. Here, we present a typical biquad filter proposed by Mahmoud and Soliman [25] shown in Fig. 3.10 which employs a MOSFET-CFOA lossless integrator comprised of the middle pair of CFOAs the two capacitors therein along with the MOSFET connected 74 R. Senani et al. Vi VBP w z VLP y w z z y w V0 C1 y M2 C2 VG1 M1 VG2 VG3 M3 VG4 C1 M4 C2 x x z w -V0 z x w y z y -VLP w -Vi y -VBP Fig. 3.10 An exemplary MOSFET-C LP/BP filter proposed by Mahmoud and Soliman (adapted c 1998 Taylor & Francis) from [25] between X terminals of the two CFOAs, MOSFET-CFOA lossy integrator com- prised of the first pair of CFOAs along with the two capacitors and two MOSFETs therein, and a voltage to current converter formed by the last pair of CFOAs along with MOSFET M4 (acting as linear resistor). This biquad circuit realizes a low-pass response at VLP and a band pass response at VBP . Assuming MOSFETs to be operating in triode region where ith MOSFET has the transconductance parameter ki “ µs Cox (Wi /Li ) where (Wi /Li ) is the aspect ratio of the ith MOSFET, Cox is the gate oxide capacitance/unit area, µs is the electron mobility and VT is the threshold voltage (assumed same in case of identical devices), by a straight forward analysis of the circuit the two transfer functions realizable by this circuit are given by s 1 VBP R C VLP R3 R4C1C2 “ 1 1 and “ (3.17) Vi D(s) Vi D(s) where 1 1 ωo D(s) “ s2 + + “ s2 + s + ωo2 (3.18) R2C1 R3 R4C1C2 Q0 1/2 1 C1 ω0 “ , Q0 “ R 2 (3.19) (R3 R4C1C2 )1/2 R3 R4C2 and Ri “ 1/Ki (VGi − VT) for (i “ 1, 2, 3, 4) (3.20) From the above it is seen that for the realized filters, the parameter ω0 can be controlled by VG3 and/or VG4 whereas Q0 in case of LP and bandwidth ω0 /Q0 in case of BP can be controlled by external voltage VG2 . 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 75 Fig. 3.11 An exemplary full VIN y wave rectifier proposed by w Khan, Abou and Al-Turiagh x z D1 using CFOAs (adapted from [26] c 1995 Taylor & Francis) D2 R1 D4 D3 V0 x z w y R2 3.6.7 Design of Precision Rectifier Using CFOAs There have been several attempts of making precision current mode full wave rectifiers using current conveyors quite often realized with AD844 type CFOA. Here we present a typical design of a simple full wave precision rectifier circuit proposed in [26] (Fig. 3.11) which avoids the use of closely matched resistors and provides a wide dynamic input voltage range. The circuit provides a high performance over a wide frequency range of operation. An inspection of the circuit reveals that the current flowing into the X terminal of AD844 at the bottom and the one flowing out of Z terminal of AD844 at the top are given by: iz “ ix “ Vin /(R1 + 2rx). The diode combinations D1 –D2 and D3 –D4 are connected in such a manner that the output current of the CFOA will flow either into the load resistance R2 or will be bypassed to the ground depending upon the polarity of the input voltage Vin . In other words, when Vin is positive, ix , iZA and iZB have the directions such that diodes D1 –D2 allow iZ to be flowing into load resistance R2 whereas at the same time, diodes D3 –D4 allow iZB to the ground. Similarly, when Vin is negative, ix , iZA and iZB reverse their directions and as consequence, now iZB is taken to the load while iZA flows to the ground. It therefore follows that current through the load R2 will be uni-directional thereby resulting in an output voltage given by V0 “ iZA R2 “ iZB R2 “ (R2 /(R1 + 2rx))Vin (3.21) It is interesting to note that by reversing the connections of all the four diodes, one can obtain a full wave rectified signal with sign inversion (i.e. –V0 ). Lastly, it must be mentioned that as compared to VOA-based precision rectifiers, which generally require four or more matched resistors, the circuit using CFOA described here uses a bare minimum of (only two) resistors. 76 R. Senani et al. Fig. 3.12 Relaxation oscillator proposed by Abuelma’atti and Al-Shahrani (adapted from [27] c 1998 Taylor & Francis). (a) Triangular/square wave generator. (b) Transfer characteristic of the Schmitt Trigger composed of CFOA, R2 and R1 3.6.8 Realization of Relaxation Oscillator/Waveform Generator A triangular/square wave generator can be made from a single CFOA as shown in Fig. 3.12 [27]. In this circuit, the CFOA behaves as a Schmitt trigger with the input– output characteristic shown in Fig. 3.12b where the threshold voltages are given by R1 − rx R1 − rx VT H “ VsatH and VT L “ VsatL (3.22) R1 − R2 R1 − R2 where VsatH and VsatL are two stable states decided by the DC biasing power supply voltages of the CFOA and Rx is the input resistance of the CFOA looking into terminal X of the CFOA. The circuit can be analyzed by starting from any one of the two stable states of the output voltage V0 (for details the reader is referred to [27]). The circuit generates a square wave signal at V0 and a triangular wave signal at Vx the frequency of which is given by R1 − rx 1 R2 f “ 1/ 2CR3 , or f – 1+ for R1 >>Rx . (3.23) R1 + R2 2CR3 R1 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 77 3.7 Applications of CFOAs in Realizing Other Building Blocks It is worthwhile to point out that, apart from being employed as four terminal build- ing blocks in their own right, CFOAs have also been employed to realize other build- ing blocks in the analog circuits literature, for instance see [28–31]. Some important realizations have been summarized here in Fig. 3.13a–h, where input marked as “+” represents y-input and the one marked as “−” represents x-input of the CFOA. a CCII+ and CCII - b Voltage and Current Follower c A Four Terminal Floating Nullor d Current Differencing Buffer Amplifier (CDBA) (adapted from [28] © 1999 Elsevier) Fig. 3.13 Realization of various building blocks using CFOAs 78 R. Senani et al. Operation Transresistance Amplifier (OTRA) (adapted from [29] © 1992 IET) Current Differencing Transconductance Amplifier (CDTA) [30] Relaization of a CCIII+[31] Relaization of a DVCC+[31] Fig. 3.13 (continued) 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 79 3.8 Recent Developments in Bipolar and CMOS Implementation of CFOAs Although there have been hundreds of publications on improving the design of current conveyors, surprisingly, in spite of the wide spread applications of CFOAs as exemplified here and in the references cited therein, there have been comparatively a very much smaller number of efforts [32–36] on improving the design of bipolar or CMOS CFOAs. In [32] Tammam, Hayatleh and Lidgey have presented a new CFOA architecture with significantly improved CMRR and gain accuracy. In [33] Hayatleh, Tammam, Hart and Lidgey have introduced a new CFOA architecture using forward and reverse bootstrapping (reproduced here in Fig. 3.14). This circuit is shown to offer increase of CMRR by about 46 dB with a reduction of input- referred-offset-voltage by a factor of two. References [34–36] have dealt with the design of improved CFOAs for CMOS technology. Out of these [35] deals with fully differential CFOA design reproduced here in Fig. 3.15. A typical CMOS CFOA architecture from [36] provides improved performance in terms of low output resistance, high current drive and high slew rate capability as compared to a number of earlier designs. The continued efforts on improving the design of bipolar and CMOS CFOAs include a systematic synthesis of CFOAs advanced by Torres-Papaqui and Tlelo-Cuautle through manipulation of voltage followers and current followers [37]. It is hoped that continued work in this direction may result in better CFOAs in both bipolar and CMOS technologies in near future to facilitate the realization of numerous applications of CFOAs more efficiently and fruitfully. +Vcc Q7 Q19 Q8 Q26 Q34 Q42 Q35 Q17 Q9 Q36 Q24 Q13 Q15 Q27 Q47 Q28 Q44 Q11 Q22 Q46 Q29 RQ Q1 Q3 (+) (-) Z node O/P Q41 Q40 Q2 Q4 Q30 CP Q48 Q31 Q45 Q12 Q24 Q49 Q32 Q14 Q18 Q25 Q39 Q10 Q20 Q5 Q16 Q6 Q33 Q37 Q43 -Vee Fig. 3.14 CFOA using forward and reverse bootstrapping proposed by Hayatleh-Tammam, Hart c 2007 Taylor & Francis) and Lidge (adapted from [33] 80 R. Senani et al. Fig. 3.15 Schematic of the fully differential current feedback operational amplifier proposed by Soliman and Awad (adapted from [35] c Springer 2005) 3.9 Different Types of Modified CFOAs Proposed in Literature Due to popular appeal of CFOAs, a number of researchers have proposed, from time to time, a number of modified versions of CFOA such as specific current feedback operational amplifier (SCFOA) [38], differential voltage CFOA (DVCFOA) [39], differential difference complimentary CFOA (DDCCFA) [40] and modified CFOA (MCFOA) [41]. The SCFOA proposed by Erkan Yuce [38] is a seven port active building block which is unduly complex and except realizing a universal voltage mode/current mode filter using only a single SCFOA, along with three resistors and two capacitors as demonstrated by Yuce, does not appear to have attracted enough attention in the literature. On the other hand, the MCFOA proposed by Yuce and Minaei [41] is nothing but a composite connection of two complementary second generation current conveyors (CCII+ and CCII−) which was already proposed long back by Smith and Sedra [42] which they chose to call a “Composite current conveyor” which is a four port having exactly the same characterizing equations, as given for MCFOA. In fact, the AD844 based construction of Fig. 19 of [41] as well as the CMOS structure of Fig. 2 of [41] both are nothing but a composite connection of a CCII+ and CCII− thus, confirming its equivalence with the “composite current conveyor” of [42]. Another modification, called the differential voltage current feedback amplifier (DVCFA) was proposed by Gunes and Toker in 2002 [39] which is characterized by: iyk “ 0; k “ 1 − 2, vx “ vy1 − vy2, iz “ ix and vw “ vz . DVCFAs have been shown to be particularly useful building blocks for synthe- sizing SRCOs employing grounded capacitors (GCs) [39]. In this context it may be noticed that while it has been amply demonstrated by a number of researchers that single resistance controlled oscillators (SRCO) can be realized using only a single CFOA however, none of the circuits known so far is able to employ both GCs as 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 81 Fig. 3.16 Conversion of CFOA-based SRCO into DVCFA-based GC-SRCO as proposed by c 2002 Elsevier) Gunnes and Toker (adapted from [39] c 2005 IET) Fig. 3.17 CMOS implementation of the DDCCFA (adapted from [40] desirable for integrated circuit implementation. A DVCFA is particularly useful in removing this difficulty and it makes GC-SRCOs realizable from a single DVCFA. A family of eight such GC-oscillators has been derived by Gunes and Toker in [39] and an exemplary realization there from is shown here in Fig. 3.16. Both the circuits are characterized by exactly the same CO and FO which are given by C1 R1 “ C2 R2 (adjustable by R2 ); c 1 ω0 “ (adjustable by R3 ); (3.24) C1C2 R1 R3 Differential difference complementary current-feedback-operational-amplifier (DDCCFA): This extension of the CFOA is an active eight-port building block defined by the following characterizing equations: iyk “ 0; k “ 1 − 3, vx “ vy1 − vy2 + vy3, iz1 “ ix , iz2 “ −ix , vw1 “ vz1 and vw2“ vz2 and was formally introduced by Gupta and Senani in 2005 [40] (see Fig. 3.17). It was shown in [40] that a single DDCCFA is sufficient to generate SRCO circuits possessing the following properties simultaneously: (a) use of a single active building block, (b) employment of two GCs along with a minimum number 82 R. Senani et al. Fig. 3.18 An exemplary SRCO using a DDCCFA proposed by Gupta and Senani (adapted from [40] c 2005 IET) (only three) of resistors, (c) non-interacting controls of CO and FO, (d) a simple condition of oscillation (i.e. not more than one condition) and (e) availability of current-mode and voltage-mode outputs both explicitly. An exemplary SRCO using a DDCCFA proposed by Gupta and Senani is shown in Fig. 3.18. It has also been demonstrated in [40] that employing a single DDCCFAs, a large number of previously known building blocks can be derived as special cases while employing two DDCCFAs, still more number of other known building blocks can be realized. Thus, the present authors believe that DDCCFA can be considered to be one of the most universal building blocks known till date. 3.10 Further Research on CFOAs and Their Applications The following appear to be worthwhile ideas to be taken up for further research and investigations on CFOAs and their applications: (1) As of now, AD844 appears to be the only commercially available bipolar CFOA with an externally accessible Z-terminal. Although there are a variety of other CFOAs available from several manufacturers but they invariably do not provide an externally accessible Z-pin. In view of the versatility and flexibility provided by a 4-terminal CFOA, with an externally-accessible Z-terminal and their widespread and popular applications evolved so far, improved 4-terminal IC CFOAs having performance superior to AD844 are warranted and are expected to be widely welcome by the analog designers’ community. (2) Search for better CFOA-based configurations for various analog signal processing/signal generation applications such as MOSFET-C universal biquads capable of realizing all five standard filters and analog multiplier as counterpart to the analog divider of Fig. 3.9 appear to be two interesting problems. Thus, it is seen that there is enough scope for further research in these areas. (3) Work on the evolution of CMOS 3 Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations... 83 CFOAs, including their fully differential versions, is currently being carried out, for facilitating the implementation of CFOA-based circuits in CMOS analog VLSI. On another note, in view of their versatility evolution of fully integrated DVCFOA or DDCCFAs may be a welcome step. A preliminary design of the “DDCCFA” was proposed by Gupta and Senani, however, the problem of evolving fully Integratable, high performance DDCCFAs, as well as their newer applications, are open to investigation. Lastly, the evolution of topologies of CMOS CFOA suitable for Nanotechnological implementations is yet another worthwhile task which has not been attempted so far. References 1. Smith KC, Sedra A (1968) The current conveyor—A new circuit building block. Proc IEEE 56:1368–1369 2. Sedra A, Smith KC (1970) A second-generation current conveyor and its applications. IEEE Trans Circuit Theory CT-17:132–134 3. Toumazou C, Lidgey FJ (1994) Current feedback op-amps: A blessing in disguise? IEEE Circuits Devices Mag 10:34–37 4. Fabre A (1992) Gyrator implementation from commercially available transimpedance opera- tional amplifiers. Electron Lett 28:263–264 5. Soliman AM (1996) Application of the current feedback operational amplifiers. Analog Integr Circuits Signal Process 11:265–302 6. Lidgey FJ, Hayatleh K (1997) Current-feedback operational amplifiers and applications. Electron Commun Eng J 9:176–182 7. Senani R (1998) Realization of a class of analog signal processing/signal generation circuits: novel configurations using current feedback op-amps. Frequenz 52:196–206 8. Gilbert B (1975) Translinear circuits: a proposed classification. Electron Lett 11:14–16 9. Analog Devices, Linear Products Data Book, Norwood, MA, 1990 10. Wilson B (1989) Universal conveyor instrumentation amplifier. Electron Lett 25:470–471 11. Martinez PA, Celma S, Sabadell S (1996) Designing sinusoidal oscillators with current- feedback amplifiers. Int J Electron 80:637–646 12. Senani R, Singh VK (1996) Synthesis of canonic single-resistance-controlled-oscillators using a single current-feedback-amplifier. IEE Proc Circuits Devices Syst 143:71–72 13. Nikoloudis S, Psychalinos C (2010) Multiple input single output universal biquad filter with current feedback operational amplifiers. Circuits Syst Signal Process 29:1167–1180 14. Gupta SS, Senani R (1998) State variable synthesis of single-resistance-controlled grounded capacitor oscillators using only two CFOAs: additional new realizations. IEE Proc Circuits Devices Syst 145:415–418 15. Bhaskar DR (2003) Realization of second-order sinusoidal oscillator/filters with non- interacting controls using CFAs. FREQUENZ: J Telecommun 57:12–14 16. Senani R, Gupta SS (1997) Synthesis of single resistance controlled oscillators using CFOAs: simple state variable approach. IEE Proc Circuits Devices Syst 144:104–106 17. Bhaskar DR, Senani R (2006) New CFOA-based single-element-controlled sinusoidal oscilla- tors. IEEE Trans Instrum Meas 55:2014–2021 18. Abuelma’atti MT (2011) New two CFOA-based sinusoidal RC oscillators with buffered outlet. Analog Integr Circuits Signal Process 66:475–482 19. Senani R (1979) Novel active RC circuit for floating inductor simulation. Electron Lett 15:679–680 20. Senani R (1980) New tunable synthetic floating inductors. Electron Lett 16:382–383 84 R. Senani et al. 21. Senani R (1986) On the realization of floating active elements IEEE Trans Circuits Syst 33:323–324 22. Senani R, Bhaskar DR, Gupta SS, Singh VK (2009) A configuration for realizing floating, linear, voltage-controlled resistance, inductance and FDNC elements. Int J Circuits Theory Appl 37:709–719 23. Singh VK, Singh AK, Bhaskar DR, Senani R (2005) Novel mixed-mode universal biquads configuration. IEICE Electron Express l2:548–553 24. Liu, SI, Chen, JJ (1995) Realisation of analogue divider using current feedback amplifiers. IEE Proc Circuits Devices Syst 142:45–48 25. Mahmoud SA, Soliman AM (1998) Novel MOS-C balanced-input balanced-output filter using the current feedback operational amplifier. Int J Electron 84:479–485 26. Anwar KA, Abou El-Ela M, Al-Turaigh MA (1995) Current mode precision rectification. Int J Electron 79(6):853–859 27. Abuelma’atti MT, Al-Shahrani SM (1998) New CFOA-based triangular/square wave generator. Int J Electron 84:583–588 28. Acar C, Ozoguz S (1999) New versatile building block: current differencing buffered amplifier for analog signal processing filters. Microelectron J 30:157–160 29. Chen JJ, Tsao HW, Chen CC (1992) Operational transresistance amplifier using CMOS technology. Electron Lett 28:2087–2088 30. Biolek D (2003) CDTA-building block for current-mode analog signal processing. ECCTD’03. III:397–400 31. Yuce E, Minaei S (2007) Realisation of various active devices using commercially available AD844s and external resistors. Electron World 113:46–49 32. Tammam AA, Hayatleh K, Lidgey FJ (2003) High CMRR current-feedback operational amplifier. Int J Electron 90:87–97 33. Hayatleh K, Tammam AA, Hart BL, Lidgey FJ (2007) A novel current-feedback op-amp exploiting bootstrapping techniques. Int J Electron 94:1157–1170 34. Mita R, Palumbo G, Pennisi S (2005) Low-voltage high-drive CMOS current feedback Op-amp. IEEE Trans Circuits Syst II 52:317–321 35. Soliman AM, Awad IA (2005) Fully differential CMOS current feedback operational amplifier. Analog Integr Circuits Signal Process 43:61–69 36. Catalado GD, Grasso AD, Pennisi S (2007) Two CMOS current feedback operational amplifiers. IEEE Trans Circuits Syst II 54:944–948 37. Torres-Papaqui L, Tlelo-Cuautle E (2004) Synthesis of CCs and CFOAs by manipulation of VF and CFs. In: Behavioral modeling and simulation conference. Proceedings of the 2004 IEEE International, pp. 92–96 38. Yuce E (2010) Fully integrable mixed-mode universal biquads with specific application of the CFOA. Int J Electron Commun (AEU) 64:304–309 39. Gunes EO, Toker A (2002) On the realization of oscillators using state equations. Int J Electron Commun (AEU) 56:1–10 40. Gupta SS, Senani R (2005) New grounded-capacitor SRCOs using a single differential- difference-complementary-current-feedback-amplifier. IEE Proc Circuits Devices Syst 152:38–48 41. Yuce E, Minaei S (2008) A modified CFOA and its applications to simulated inductors, capacitance, multipliers, and analog filters. IEEE Trans CAS-I 55:266–275 42. Smith KC and Sedra AS (1970) Realization of Chua family of new nonlinear network elements using current conveyors. IEEE Trans Circuit Theory 17:137–139 Chapter 4 Generation of Grounded Capacitors Minimum Component Oscillators Ahmed M. Soliman 4.1 Introduction It is not possible to realize a sinusoidal oscillator using a single operational amplifier (Op Amp) and the minimum number of passive circuit elements namely two resistors and two capacitors. Several minimum passive circuit element oscillators are available in the literature [1–9] using a single voltage controlled voltage source (VCVS), a single voltage controlled current source (VCCS), a single current conveyor (CCII+) [10] and a single inverting current conveyor (ICCII−) [11]. The objective of this chapter is to apply nodal admittance matrix (NAM) expansion to generate three node, four node and five node oscillator circuits using members of the CCII and ICCII families. Recently, a symbolic framework for systematic synthesis of linear active circuits based on NAM expansion was presented in [12]. The matrix expansion process begins by introducing blank rows and columns, representing new internal nodes, in the admittance matrix. Then, nullators and norators are used to move the resulting admittance matrix elements to their final locations, properly describing either floating or grounded passive elements. Thus, the final NAM is obtained including finite elements representing passive circuit components and unbounded elements, so called infinity-variables, representing nullators and norators. In this framework, nullators and norators ideally describe active elements in the circuit are used. The nullator and norator are pathological or singular elements that possess ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. For the nullator shown in Fig. 4.1a V “ I “ 0, while the norator shown in Fig. 4.1b imposes no constraints on its voltage and current. The attractive feature of the two-nullor elements is their ability to model active A.M. Soliman () Electronics and Communication Engineering Department, Faculty of Engineering, Cairo University, Giza, 12613, Egypt e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 85 DOI 10.1007/978-1-4614-1383-7 4, © Springer Science+Business Media New York 2013 86 A.M. Soliman a b I I V V c d I2 I1 I1 I2 V1 V2 V1 V2 Fig. 4.1 (a) Nullator. (b) Norator. (c) Voltage mirror. (d) Current mirror circuits [13]. Despite the ability of nullor elements to describe many active building blocks, they fail to represent devices like the CCII+. Other passive elements like resistors are combined with nullators and norators in order to obtain the nullor representation of the CCII+ [6]. In order to avoid the use of passive elements in the nullor representation of any building block, additional pathological elements called mirror elements describing the voltage and current reversing actions are introduced in [11]. The voltage mirror (VM) shown in Fig. 4.1c, is a lossless two-port network element used to represent an ideal voltage reversing action and it is described by: V1 “ −V2 (4.1a) I1 “ I2 “ 0 (4.1b) The current mirror (CM) shown in Fig. 4.1d, is a two-port network element used to represent an ideal current reversing action and it is described by: V1 and V2 are arbitrary (4.1c) I1 “ I2 , and they are also arbitrary (4.1d) Very recently the systematic synthesis method based on NAM expansion using nullor elements [12] has been extended to accommodate mirror elements. This results in a generalized framework encompassing all pathological elements for ideal description of active elements [14]. Accordingly, more alternative realizations are possible and a wide range of active devices can be used in the synthesis procedure. In this chapter, the conventional systematic synthesis framework using NAM expansion presented in [15] to synthesize oscillator circuits is applied to the 4 Generation of Grounded Capacitors Minimum Component Oscillators 87 minimum passive component oscillators. The oscillators are classified according to the number of nodes in the circuit and the nature of the two resistors whether being grounded or floating as shown in Fig. 4.2. Several new as well as well-known oscillator circuits are generated in this chapter; using CCII or ICCII or combination of both. 4.2 Formulation of the NAM Equation The oscillators considered in this chapter are grounded capacitors second order oscillators using two resistors and two capacitors. The state matrix equation is described as follows: ⎡ ⎤⎡ ⎤ a11 a12 V1 sV1 (4.2) “⎣ ⎦⎣ ⎦ sV2 a21 a22 V2 The condition of oscillation and the radian frequency of oscillation are given by: ? a11 +a22 “ 0, ω o “ a11 a22 − a12a21 (4.3) From the above equation it is seen that a11 and a22 must have opposite polarities, also a12 and a21 must have opposite polarities. If both a11 and a22 are zero there will be no control on the condition of oscillation. The oscillator circuits considered in this chapter are canonic grounded capacitor oscillators represented by one of the four general configurations shown in Fig. 4.2. Four different classes of oscillators are considered in this chapter. The class I oscillators has one grounded resistor and one floating resistor and each of the two resistors shares a node with one of the capacitors and it is a three node oscillator circuit as shown in Fig. 4.2a. On the other hand in the class II oscillators the grounded resistor does not share a node with one of the capacitors and it is a four- node oscillator circuit as shown in Fig. 4.2b. In the class III oscillators both resistors are grounded and do not share nodes with the two-grounded capacitors and it is a four-node oscillator circuit as shown in Fig. 4.2c. This class of oscillators has no condition of oscillation and will be discussed briefly in this chapter. The class IV oscillators has two floating resistors and one of them shares a node with one of the capacitors and it is a five node oscillator circuit as shown in Fig. 4.2d. The class V oscillator has one grounded resistor and one floating resistor and both resistors do not share nodes with the two-grounded capacitors. It is also a five- node oscillator circuit with no control on condition of oscillation as in the class III and will not be discussed in this chapter. 88 A.M. Soliman a b 2 2 c 2 2 Fig. 4.2 (a) Class I three node generalized configuration. (b) Class II four-node configuration. (c) Class III four-node configuration. (d) Class IV five nodes generalized configuration 4.3 Class I Oscillators The generalized class I oscillator configuration shown in Fig. 4.2a has two types and can be described by the state equations as given in Table 4.1. The admittance matrix Y of the two-port oscillator circuit taking the capacitors C1 and C2 as external elements at ports 1 and 2 is formulated from the state matrix by interchanging the signs of the admittance parameters. 4.3.1 Class I-Type A The NAM in this case is given by: G1 − G1 Y“ (4.4) G1 −G1 + G2 Adding a third blank row and column to the above equation and connecting a nullator between columns 2 and 3 to move −G1 from 1, 2 position to the 1, 3 position and also to move −G1 from 2, 2 position to the 2, 3 position, the following NAM is obtained: 4 Generation of Grounded Capacitors Minimum Component Oscillators 89 Table 4.1 Summary of the state matrix equation of the four classes of oscillators Oscillation Number Class State matrix equation condition of nodes ⎡ ⎤⎡ ⎤ I- A −G1 ±G1 V1 sC1V1 C2 G2 I- B “⎣ ⎦⎣ ⎦ + “1 3 sC2V2 C1 G1 ∓G1 G1 − G2 V2 ⎡ ⎤⎡ ⎤ II- A −G1 ±G1 V1 sC1V1 II- B “⎣ ⎦⎣ ⎦ C2“ C1 4 sC2V2 ∓G1 ∓ G2 G1 V2 ⎡ ⎤⎡ ⎤ II- C −G1 ∓G1 ∓ G2 V1 sC1V1 II- D “⎣ ⎦⎣ ⎦ C2“ C1 4 sC2V2 ±G1 G1 V2 ⎡ ⎤⎡ ⎤ III- A 0 ∓G1 V1 sC1V1 III-B “⎣ ⎦⎣ ⎦ No condition 4 sC2V2 ±G2 0 V2 ⎡ ⎤⎡ ⎤ III- C 0 ±G2 V1 sC1V1 III-D “⎣ ⎦⎣ ⎦ No condition 4 sC2V2 ∓G1 0 V2 ⎡ ⎤⎡ ⎤ IV- A −G1 +G2 ∓G2 V1 sC1V1 IV-B “⎣ ⎦⎣ ⎦ G2 “ G1 5 sC2V2 ±G1 0 V2 ⎡ ⎤⎡ ⎤ IV- C −G1 +G2 ±G1 V1 sC1V1 IV-D “⎣ ⎦⎣ ⎦ G2 “ G1 5 sC2V2 ∓G2 0 V2 hkkkkkkkkkkj ⎡ ⎤ G1 0 −G1 Y “ ⎣ G1 G2 −G1 ⎦ (4.5) 0 0 0 Connecting a CM between rows 2 and 3 to move G1 from 2, 1 position to become −G1 at the 3, 1 position and also to move −G1 from 2, 3 to become G1 at the position to the position 3, 3, the following NAM is obtained: hkkkkkkkkkkj ⎡ ⎤ G1 0 − G1 Y “⎣ 0 G2 0 ⎦ (4.6) − G1 0 G1 The pathological realization for the above equation after adding the two capacitors at nodes 1 and 2 is shown in Fig. 4.3a. The nullator and CM are realizable by a CCII+, which results in the well-known oscillator circuit reported in [1, 4, 6]. 90 A.M. Soliman a G1 3 2 V1 V2 C1 G2 C2 b G1 V1 1 3 2 V2 C1 G2 C2 Fig. 4.3 (a) Pathological realization of class I-type A oscillator. (b) Pathological realization of class I-type B oscillator 4.3.2 Class I-Type B The NAM in this case is given by: G1 G1 Y“ (4.7) −G1 −G1 + G2 Adding a third blank row and column to the above equation and connecting a VM between columns 2 and 3 and a norator between rows 2 and 3 the following NAM is obtained: 4 Generation of Grounded Capacitors Minimum Component Oscillators 91 hkkikkj ⎡ ⎤ G1 0 − G1 Y “ ⎣ 0 G2 0 ⎦ (4.8) hkkkkj − G1 0 G1 The pathological realization for the above equation after adding the two capacitors at nodes 1 and 2 is shown in Fig. 4.3b. The VM and norator are realizable by an ICCII−, which results in the well known oscillator circuit reported in [1, 2]. For each of the two circuits of the class I oscillators the condition of oscillation and the radian frequency of oscillation are given by: c C2 G2 G1 G2 + “ 1, ω o “ (4.9) C1 G1 C1C2 Of course it is not possible to use equal G or equal C with this class of oscillators. 4.4 Class II Oscillators The class II oscillator configuration is shown in Fig. 4.2b has four types and can be described by the state equations as given in Table 4.1. The condition of oscillation for this class is C1 “ C2 . This class of oscillators was generated in [1] from eight alternative grounded frequency dependent negative resistor (FDNR) circuits. 4.4.1 Class II-Type A The NAM in this case is given by: G1 − G1 Y“ (4.10) G1 +G2 −G1 Adding a third blank row and column to the above equation and connecting a nullator between columns 2 and 3 to move −G1 from 1, 2 position to the 1, 3 position and also to move −G1 from 2, 2 position to the 2, 3 position, the following NAM is obtained: hkkkkkkkkkkj ⎡ ⎤ G1 0 −G1 Y “ ⎣ G1 +G2 0 −G1 ⎦ (4.11) 0 0 0 92 A.M. Soliman Connecting a CM between rows 2 and 3 to move G1 from 2, 1 position to become −G1 at the 3, 1 position and also to move −G1 from the position 2, 3 to become G1 at the diagonal position 3, 3 thus the following NAM is obtained: hkkkkkkkkj ⎡ ⎤ G1 0 −G1 Y “ ⎣ G2 0 0 ⎦ (4.12) −G1 0 G1 Adding a fourth blank row and column to the above equation and then adding a nullator between columns 1, 4 and a norator between rows 2, 4 in order to move G2 to the diagonal position 4, 4; the following NAM is obtained: hkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkj 0 −G1 0 ⎡ ⎤ G1 hkkkkkkkkkkj ⎢0 0 0 0 ⎥ (4.13) Y “⎢ ⎣ −G1 0 G1 ⎥ 0 ⎦ 0 0 0 G2 The pathological realization for the above equation after adding the two capacitors at nodes 1 and 2 is shown in Fig. 4.4a. The corresponding CCII− and CCII+ oscillator circuit is shown in Fig. 4.4b [1, 16]. There is a second circuit that belongs to class II-type A having the same topology, which can be generated and it uses an ICCII+ and a CCII+ and was introduced in [1]. 4.4.2 Class II-Type B The NAM in this case is given by: G1 G1 Y“ (4.14) −G1 − G2 −G1 Following similar steps as in the previous section two oscillator circuits having same circuit topology as the class II-type A can be generated. One of the two oscillators uses two ICCII− and the other uses a CCII+ and an ICCII−. 4.4.3 Class II-Type C This is the adjoint to class II-type A [17], the NAM in this case is given by: G1 G1 +G2 Y“ (4.15) −G1 −G1 4 Generation of Grounded Capacitors Minimum Component Oscillators 93 a 4 b X 4 CCII Z– Y 1 G1 Y 3 2 1 G1 3 1 X V1 V2 2 G2 V1 CCIIZ+ V2 G2 Y 2 C1 C2 C1 C2 c 4 d X 4 CCII Z– 1 Y G1 3 2 1 G1 1 3 G2 X V1 V2 2 V1 ICCII Z– V2 Y 2 G2 C1 C2 C1 C2 Fig. 4.4 (a) Pathological realization 1 of class II-type A oscillator. (b) CCII− and CCII+ oscillator circuit realizing Fig. 4.4a [1, 16]. (c) Pathological realization 1 of class II-type C oscillator. (d) CCII− and ICCII− oscillator circuit realizing Fig. 4.4c [1] Following successive expansion steps the following NAM is obtained: hkkkkkkkkkkkkkkkkj hkkkikkkj 0 −G1 0 ⎡ ⎤ G1 hkkkkkkkkkkkkj ⎢0 0 0 0 ⎥ (4.16) hkkk j Y “⎢ ⎣ −G1 ⎥ 0 G1 0 ⎦ 0 0 0 G2 The pathological realization for the above equation after adding the two capacitors at nodes 1 and 2 is shown in Fig. 4.4c. The corresponding CCII− and ICCII− oscillator circuit is shown in Fig. 4.4d [1]. There is a second circuit that belongs to class II-type C having the same topology that can be generated and it uses an ICCII+ and an ICCII− and was given in [1]. 94 A.M. Soliman 4.4.4 Class II-Type D This is the adjoint to class-type B [17], the NAM in this case is given by: G1 −G1 − G2 Y“ (4.17) G1 −G1 Following similar steps as in the previous section two oscillator circuits having same circuit topology as the class II-type C can be generated. One of the two oscillators uses two; CCII+ [1, 18] and the other use an ICCII− and a CCII+. It should be noted that the class II oscillators were generated in [1] from eight- grounded frequency dependent negative resistance (FDNR) circuits by terminating input port by a grounded capacitor. Two more circuits that belong to this class and have different topology can be generated from types type A and type C as follows. Starting from (4.11) and adding a fourth blank row and column and connecting a nullator between columns 1, 4 to move G2 to the position 2, 4 and a norator between rows 2 and 4 to move G1 and −G1 from row 2 to row 4, it follows that: hkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkj G1 0 −G1 0 ⎡ ⎤ ⎢0 0 0 0 ⎥ (4.18) hkkkkkkkkj Y “⎢ ⎣0 ⎥ 0 0 0 ⎦ G1 0 −G1 G2 Adding a CM between rows 4 and 3 to move G1 and −G1 from row 4 to row 3 to become −G1 and G1 , it follows that: hkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkj −G1 ⎡ ⎤ G1 0 0 ⎢0 0 0 0 ⎥ (4.19) hkkkkkkkkj Y “⎢ ⎣ −G1 ⎥ 0 G1 0 ⎦ 0 0 0 G2 The oscillator circuit representing the above equation uses a CCII+ and a CCII− and is shown in Fig. 4.5a [1, 19]. This oscillator circuit can be obtained from the unity gain current mode band-pass filter given in [20] by feeding-back output current to the input port. Similarly, expanding the NAM equation of the class II-type C can generate the circuit shown in Fig. 4.5b, this circuit was reported in [1,21]. It should be noted that the stray resistance RX of conveyor 1 and the capacitance CZ of conveyor 2 affect the circuits of Fig. 4.5. 4 Generation of Grounded Capacitors Minimum Component Oscillators 95 Fig. 4.5 (a) Alternative a topology of a class II-type A oscillator [1, 19]. 4 X (b) Alternative topology of a CCII V2 Z– Y class II-type B oscillator 1 2 Y CCII Z+ [1, 20] X 2 C2 G2 V1 1 3 G1 C1 b 4 X ICCII V2 Y Y 1 Z– 2 ICCII Z– X 2 C2 G2 V1 1 3 G1 C1 4.5 Class III Oscillators The class III oscillator configuration shown in Fig. 4.2c has four types and can be described by the state equations as given in Table 4.1. There is no condition of oscillation for this class. The eight oscillators belonging to this class can be obtained from the eight gyrators reported in [22] by terminating the two ports of the gyrators by the two capacitors. 4.5.1 Class III-Type A The NAM in this case is given by: 0 G1 Y“ (4.20) −G2 0 96 A.M. Soliman Fig. 4.6 (a) CCII+ and a CCII− class III-type A oscillator circuit 1 [23]. (b) ICCII− and CCII− class 1 Y V1 V2 III-type C oscillator adjoint to CCII Z+ Y 1 2 Fig. 4.6a X CCII 4 Z– X 2 3 C1 G2 C2 G1 b 2 Y V2 ICCII Z– V1 Y 1 1 X CCII 4 Z– X 2 3 C2 G2 C1 G1 By successive expansions the following NAM is obtained: hkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkj ⎡ ⎤ 0 0 0 0 hkkkkkkkkj ⎢0 0 0 0 ⎥ (4.21) Y “⎢ ⎣ 0 0 G1 ⎥ 0 ⎦ 0 0 0 G2 The above equation results in the class III-type A realization 1 using a CCII+ and a CCII− as shown in Fig. 4.6a [23]. The class III-type-A oscillators include three more realizations and can be obtained in a similar way and are summarized as follows: realization 2; using a CCII+ and an ICCII+, realization 3; using an ICCII− and a CCII−, realization 4; using an ICCII− and an ICCII+. 4 Generation of Grounded Capacitors Minimum Component Oscillators 97 4.5.2 Class III-Type B The class III-type B oscillators include also four circuits and can be obtained in a similar way and are realizable using CCII−, CCII+ or ICCII+, CCII+ or CCII−, ICCII− or ICCII+, ICCII−. 4.5.3 Class III-Type C This represents the adjoint oscillator circuits to class III-type A oscillator circuits. The four oscillator circuits realizing the type A realize also the type C oscillators after inter-changing ports 1 and 2. For example the oscillator circuit shown in Fig. 4.6b is the adjoint of that of Fig. 4.6a and is also obtainable from realization 3 of class III-type A after interchanging the two ports 1 and 2. 4.5.4 Class III-Type D This represents the adjoint oscillator circuits to class III-type-B. The four oscillator circuits realizing the type-B realize also the type-D oscillators after inter-changing ports 1 and 2. The oscillators of the class III can be designed with equal C and equal G. 4.6 Class IV Oscillators The class IV oscillator configuration is shown in Fig. 4.2d has four types and can be described by the state equations as given in Table 4.1. 4.6.1 Class IV-Type A The NAM in this case is given by: G1 − G2 G2 Y“ (4.22) −G1 0 98 A.M. Soliman Adding a third blank row and column to the above equation and connecting a norator between columns 2 and 3 in order to move −G1 from the 2, 1 position to the position 3, 1 the following NAM is obtained: ⎡ ⎤ G1 − G2 G2 0 Y “⎣ 0 0 0⎦ (4.23) hkkkkj − G1 0 0 Adding a fourth blank row and column to the above equation and then adding a nullator between columns 2, 4 in order to move G2 to from the position 1, 2 to the position 1, 4 the following NAM is obtained: hkkkkkkkkkkkkj G1 − G2 ⎡ ⎤ 0 0 G2 (4.24) 0 0 0 0 ⎥ hkkk j ⎢ Y “⎢ ⎣ −G1 ⎥ 0 0 0 ⎦ 0 0 0 0 Adding a norator between rows 1, 4 in order to move −G2 and G2 to from the first row to the fourth row the following NAM is obtained: hkkkkkkkkkkkkj ⎡ ⎤ G1 0 0 0 hkkkkkkkkkkkkj ⎢0 0 0 0 ⎥ hkkk j Y “⎢ ⎥ (4.25) ⎣ −G1 0 0 0 ⎦ −G2 0 0 G2 Adding a fifth blank row and column and connecting a nullator between columns 1 and 5 in order to move −G2 from the position 4, 1 to the position 4, 5 therefore: hkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkj ⎡ ⎤ hkkkkkkkkkkkkj G1 0 0 0 0 ⎢0 (4.26) 0 0 0 0 hkkk j ⎥ ⎢ ⎥ Y “ ⎢ −G1 0 0 0 0 ⎢ ⎥ ⎥ −G2 ⎦ ⎢ ⎥ ⎣0 0 0 G2 0 0 0 0 0 The indefinite admittance matrix has the property that each row and each column sum to zero [24]. Connection of a norator between nodes 5 and zero will allow the row zero terms to be brought to row 5. Similarly, a connection of a nullator between nodes 3 and zero will allow the column zero to be brought to column 3 [24] as follows: 4 Generation of Grounded Capacitors Minimum Component Oscillators 99 Fig. 4.7 (a) Pathological a 5 realization 1of class IV-type A oscillator. (b) Three CCII− G2 4 realization 1of class IV-type A oscillator 2 3 G1 1 C2 C1 b G2 Y X 5 4 X CCII CCII 1 Z− 2 Z− Y G1 X V1 CCII 3 1 V2 Z− 2 3 Y C2 C1 hkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkkkkkj hkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkj ⎡ ⎤ 0 −G1 0 hkkkkkkkkkkkkj G1 0 (4.27) ⎢0 0 0 0 0 hkkk j ⎥ ⎢ ⎥ Y “ ⎢ −G1 0 G1 0 0 ⎢ ⎥ ⎥ −G2 ⎦ ⎢ ⎥ ⎣0 0 0 G2 0 0 0 −G2 G2 hkkk j The above equation results in the class IV-type A pathological realization 1 shown in Fig. 4.7a. The corresponding realization using three CCII− is shown in Fig. 4.7b. It should be noted that this new oscillator circuit can also be obtained from the unity gain band-pass filter introduced in [25] by connecting the band-pass output to the input port through a voltage follower to provide isolation to band-pass output port. Following similar steps as in the previous section a second pathological realiza- tion is obtained and is shown in Fig. 4.8a and the corresponding current conveyor circuit realization is shown in Fig. 4.8b. 100 A.M. Soliman Fig. 4.8 (a) Pathological a 5 realization 2 of class IV-type A oscillator. (b) CCII and G2 4 ICCII realization 2 of class IV-type A oscillator 2 3 G1 1 C2 C1 b G2 5 4 Y X X ICCII ICCII 1 Z+ 2 Z– Y G1 X V1 V2 CCII 3 1 Z– 3 2 Y C1 C2 4.6.2 Class IV-Type B The NAM in this case is given by: G1 − G2 −G2 Y“ (4.28) G1 0 Successive NAM expansion steps can expand the above Y matrix to the following form: hkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkikkkkkkkj hkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkj ⎡ ⎤ hkkkkkkkkkkkkj G1 0 −G1 0 0 (4.29) hkkikkj ⎢ 0 0 0 0 0 ⎥ ⎢ ⎥ Y “ ⎢ −G1 0 G1 0 0 ⎥ ⎢ ⎥ −G2 ⎦ ⎢ ⎥ ⎣ 0 0 0 G2 0 0 0 −G2 G2 hkkk j 4 Generation of Grounded Capacitors Minimum Component Oscillators 101 Fig. 4.9 (a) Pathological a 5 realization 1 of class IV-type B oscillator. (b) Pathological G2 realization 2 of class IV-type 4 B oscillator 3 G1 1 2 C2 C1 b 5 G2 4 3 G1 1 2 C2 C1 The above equation results in the class IV-type B pathological realization 1 shown in Fig. 4.9a. The second pathological realization of the class IV- type B is shown in Fig. 4.9b. The realizations of class IV-types C and D can be obtained following similar steps as before. 102 A.M. Soliman 4.7 Alternative Topology Realizations of Class IV Oscillators In this section a brief discussion on a second topology realization of class IV- types A and B is given. 4.7.1 Class IV-Topology II-Type A Apply NAM expansion to (4.22) the following Y matrix is obtained: hkkkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkkkkkkkkkkkkkkkkkkkj hkkkkkkkkkkkkkkkkkkkkkkkkkkj ⎡ ⎤ 0 −G1 hkkkkkikkkkkj G1 0 0 (4.30) ⎢ 0 0 0 0 0 ⎥ hkkk j ⎢ ⎥ Y “ ⎢ −G1 0 G1 0 0 ⎥ ⎢ ⎥ −G2 ⎦ ⎢ ⎥ ⎣ 0 0 0 G2 0 0 0 −G2 G2 hkkk j The above equation results in the pathological realization 1 shown in Fig. 4.10a. The corresponding realization using a CCII+ and two CCII− is shown in Fig. 4.10b. A second pathological realization can be derived and results in the pathological realization shown in Fig. 4.11. Similarly for the class IV-type B a second topology can be derived and results in the pathological realization 1 shown in Fig. 4.12a. The corresponding realization using two; CCII+ and one ICCII− is shown in Fig. 4.12b. A second pathological realization can be derived and results in the pathological realization shown in Fig. 4.12c. 4.8 Conclusions Systematic generation method for realizing grounded capacitor oscillator circuits using NAM expansion was given. The oscillators considered in this chapter uses the minimum number of passive elements namely two capacitors and two resistors. All generated oscillator circuits except those of Fig. 4.5 have the advantage of their ability to absorb parasitic resistance and parasitic capacitance elements effects. Four classes of oscillators are generated in this chapter, the class I oscillator circuits include three nodes, the classes II and III oscillator circuits include four nodes and the class IV oscillator circuits include five nodes. 4 Generation of Grounded Capacitors Minimum Component Oscillators 103 Fig. 4.10 (a) Class IV-type G2 A topology II pathological a 4 5 realization 1. (b) Three CCII realization of Fig. 4.10a 1 G11 3 2 C1 C2 b Y X X 4 G2 5 CCII CCII Z– 1 2 Z+ Y V1 G1 X 1 3 V2 CCII Z– 3 2 C1 Y C2 Fig. 4.11 Class IV-type 4 G2 5 A topology II pathological realization 2 1 G1 3 2 C1 C2 104 A.M. Soliman a b G2 Y X X 5 4 5 4 G2 CCII ICCII Z– 1 2 Z+ Y V1 G1 3 X 1 V2 CCII Z+ 3 2 C1 Y 1 G1 C2 3 2 C1 C2 G2 5 c 4 1 G1 3 2 C1 C2 Fig. 4.12 (a) Class IV-type B topology II pathological realization. (b) Two CCII one ICCII realization of Fig. 4.12a. (c) Class IV-type B topology II pathological realization 2 References 1. Soliman AM (2009) Generation of oscillators based on grounded capacitor current conveyors with minimum passive components. J Circ Syst Comput 18:857–873 2. Soliman AM (2011) Generation of the minimum component oscillators from Sallen Key filters. J Circ Syst Comput 20:1165–1183 3. Bhattacharyya BB, Sundaramurthy M, Swamy MNS (1981) Systematic generation of canonic sinusoidal RC active oscillators. IEE Proc Circ Dev Syst 128:114–126 4. Celma S, Martinez PA, Carlosena A (1994) Approach to the synthesis of canonic RC-active oscillators using CCII. IEE Proc Circ Dev Syst 141:493–497 5. Abuelmatti MT (1987) Two minimum components CCII based RC oscillators. IEEE Trans Circ Syst 34:980–981 6. Svoboda JA (1989) Current conveyors operational amplifiers and nullors. IEE Proc Circ Dev Syst 136:317–322 7. Budak A, Nay K (1981) Operational amplifier circuits for Wien bridge oscillators. IEEE Trans Circ Syst 28:930–934 8. Soliman AM, Al-Shamaa MH, Dak Al-Bab M (1988) Active compensation of RC oscillators. Frequenz 42:325–332 9. Martinez PA, Celma S, Gutierrez I (1995) Wien type oscillators using CCII+. Analog Integr Circ Sig Process 7:139–147 4 Generation of Grounded Capacitors Minimum Component Oscillators 105 10. Sedra AS, Smith KC (1970) A second generation current conveyor and its applications. IEEE Trans Circ Theor 132:132–134 11. Awad IA, Soliman AM (1999) Inverting second generation current conveyors: the missing building blocks, CMOS realizations and applications. Int J Electron 86:413–432 12. Haigh DG, Clarke TJW, Radmore PM (2006) Symbolic framework for linear active circuits based on port equivalence using limit variables. IEEE Trans Circ Syst I 53:2011–2024 13. Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E, Tan SXD (2011) Pathological element- based active device models and their application to symbolic analysis. IEEE Trans Circ Syst I 58:1382–1395 14. Saad RA, Soliman AM (2008) Use of mirror elements in the active device synthesis by admittance matrix expansion. IEEE Trans Circ Syst I 55:2726–2735 15. Soliman AM (2010) Generation of current conveyor based oscillators using nodal admittance matrix expansion. Analog Integr Circ Sig Process 65:43–59 16. Fongsamut C, Anuntahirunrat K, Kumwachara K, Surakampontorn W (2006) Current- conveyor-based single element controlled and current controlled sinusoidal oscillators. Int J Electron 93:467–478 17. Director SW, Rohrer RA (1969) The generalized adjoint network and network sensitivities. IEEE Trans Circ Theor 16:318–323 18. Horng JW (2001) A sinusoidal oscillator using current-controlled current conveyors. Int J Electron 88:659–664 19. Horng JW, Chang CW, Lee MH (1997) Single-element-controlled sinusoidal oscillators using CCIIs. Int J Electron 83:831–836 20. Soliman AM (1997) In-sensitive band-pass Filter. Electron Eng 69:18–20 21. Soliman AM (2011) Generation of oscillators from current mode band-pass filters using single output ICCII. Journal of Active and Passive Electronic Devices 6:251–264 22. Saad RA, Soliman AM (2008) Generation, modeling, and analysis of CCII-based gyrators using the generalized symbolic framework for linear active circuits. Int J Circ Theor Appl 36:289–309 23. Soliman AM (1975) Simple sinusoidal active RC oscillators. Int J Electron 39:455–458 24. Haigh DG, Tan FQ, Papavassiliou C (2005) Systematic synthesis of active-RC circuit building- blocks. Analog Integr Circ Sig Process 43:297–315 25. Soliman AM (1998) Generation of CCII and CFOA Filters from passivwe RLC filters. Int J Electron 85:293–312 Chapter 5 Active Filter Design Using a Two-Graph Based Transformation Technique Mourad Fakhfakh and Marian Pierzchała 5.1 Introduction Active filter synthesis and design has been thoroughly investigated in the literature. The discovery of new active RC-circuits has been accomplished by using a variety of techniques. The modified nodal approach (MNA) has become the industry standard for both numerical and symbolic analysis [1, 2]. For the MNA, dimensions of the matrix and its representation are dependent on the type of elements encompassed in the circuit. This does not greatly obstruct the circuit’s analysis where the circuit elements are known in advance and the matrix dimensions and basis can be set accordingly. However, this is a problem for circuit synthesis where the types of elements that are needed for the construction of the “new” active circuit are not known a priori. For a framework encompassing both circuit analysis and synthesis, it is necessary to respect the dimensionality, and that the chosen basis be independent of the type of elements. The admittance matrix satisfies these conditions, as the number of nodes in the circuit determines the dimensions of the matrix. However, the admittance matrix representation (NAM) suffers from the problem that key ideal circuits elements, including nullors and most dependent sources, require infinite matrix elements. The problem of the infinity elements in the NAM has been solved by using a form of a limit variable, called an infinity-variable, or ∞-variables [3]. The physical interpretation of such variables is not obvious and the synthesis method of active RC-circuits [4] with these elements is complicated. In this chapter we propose a new method that overcomes the abovementioned difficulties. Our method uses the two-graph technique, which was first developed by Mielke in [5]. M. Fakhfakh () University of Sfax, Sfax, Tunisia e-mail: [email protected] M. Pierzchała Wroclaw University of Technology, Wroclaw, Poland e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 107 DOI 10.1007/978-1-4614-1383-7 5, © Springer Science+Business Media New York 2013 108 M. Fakhfakh and M. Pierzchała Instead of using the incidence matrix to express KCL and KVL relationships, our method uses the fundamental and cutset matrices. For any given R, C, L, E, I, cs1 network, we first form a closed system [6], and then construct the corresponding voltage graph GV and current graph GI . For the arbitrarily chosen common tree T , we construct the fundamental loop matrix BVT and the fundamental cutest matrix QCI in both GV and GI . (We refer the reader to [5–7] for further details regarding the two-graph technique). The classical two-graph method works only on R, L, C, E, I networks that may contain voltage controlled current sources (VCCS) (for network containing other elements, some preliminary network transformation might be required [6]). In this chapter we will also deal with the improved approach proposed in [8] which enables supporting the remaining controlled sources. Actually, the design of new active RC-filters has been accomplished by using a variety of techniques. This includes proposing a general architecture, proposing a particular circuit topology, analyzing it and matching its coefficients, applying a transformation to a known circuit, dealing with some general approaches, such as the morphological approach and the computer generation of all possible topologies, and deriving an active RC-circuit from a symbolic transfer function by admittance matrix transformations [4]. In this chapter we deal with the transformation technique that is applied to a known circuit, because in many practical situations, engineers prefer to use the LC- filter prototype as a basis of the active RC-circuits synthesis. The proposed work is mainly composed of two parts. The first part (Sect. 5.2) briefly recalls the transformation technique and provides necessary details on the use of the two-graph technique for synthesizing lossless inductor based circuits. The second part (Sect. 5.3) proposes a novel approach to generate lossy induc- tors. Adaptation and improvement of the transformation technique are detailed. Viability of the proposed technique is highlighted via the design of active filters using CMOS second generation current conveyors. SPICE simulations are given for this purpose. 5.2 Transformation of Lossless LC-Filters to Active RC-Circuits 5.2.1 The Two-Graph Technique The two-graph technique [5–7] operates using two weighted graphs: a voltage graph (GV ) and a current graph (GI ). The classical approach works only on RLC-networks that may contain voltage controlled current sources (VCCS). The approach has been 1 R,C,L,E,I,cs stand for resistors, capacitors inductors, independent voltage and current sources, and all types of controlled sources. 5 Active Filter Design Using a Two-Graph Based Transformation Technique 109 Table 5.1 TCI “ − (QCI )t IE ICT ILT IRT I (−QI,E )t (−QI,CT )t (−QI,LT )t (−QI,RT )t ICC (−QCC ,E )t (−QCC ,CT )t (−QCC ,LT )t (−QCC ,RT )t ILC (−QLC ,E )t (−QLC ,CT )t (−QLC ,LT )t (−QLC ,RT )t IGC (−QGC ,E )t (−QGC ,CT )t (−QGC ,LT )t (−QGC ,RT )t Table 5.2 BVT E VCT VLT VRT VI BI,E BI,CT BI,LT BI,RT VCC BCC ,E BCC ,CT BCC ,LT BCC ,RT VLC BLC ,E BLC ,CT BLC ,LT BLC ,RT VGC BGC ,E BGC ,CT BGC ,LT BGC ,RT improved and has been extended to support the remaining controlled sources [8] and two-graph stamps of the other linear controlled sources were proposed. In short, the two-graph technique consists of the following: the network is topologically represented by a linear graph that is composed of a voltage-graph and a current- graph, as stated above. Independent sources are replaced by dependent sources that are controlled by the desired output variable, thus forming a closed system [6]. The corresponding matrix equation system can be represented by expression (5.1). −I ⎛ ⎞⎛ ⎞ ⎛ ⎞ 0 ZT 0 VT 0 ⎜ BV −I 0 0 ⎟ ⎜ VC ⎟ ⎜ 0 ⎟ ⎟ ⎜ ⎟ ⎜ Hx“⎜ T “ ⎟ (5.1) ⎝0 0 −I QCI ⎠ ⎝ IT ⎠ ⎝ 0 ⎠ 0 YC 0 −I IC 0 ZT and YC refer to matrices of the impedances of the tree elements and the admittances of the co-tree elements, respectively. I is the identity matrix and (BVT ,QCI ) denote the fundamental loop matrix and the fundamental cut-set matrices (of orders (m,n) and (n,m), respectively). Tables 5.1 and 5.2 give the general forms of the transposed cutest-matrix and the loop-matrix, where the first column and the first row of each table refer to the considered tree and cutset elements, respectively. Indexes C and T refer to the cotree and the tree position, respectively. Further information and details regarding the two-graph technique can be found in [5–7]. 5.2.2 Application to the Synthesis of Active Filters This section details operations for replacing the loop and cutset matrices of the LC- filter [(BVT )LC , (TCI )LC ] by the matrices of the RC-circuit [(BVT )RC , (TCI )RC ]. 110 M. Fakhfakh and M. Pierzchała Table 5.3 (BVT )LC and (a) VCT (TCI )LC “ ((−QCI )t )LC for VI BI,CT LC-filters with independent current sources TCI “ − (QCI )t VLC BLC ,CT (a) (BVT )LC (b) (b) ICT (TCI )LC “ ((−QCI )t )LC I (−QI,CT )t ILC (−QLC ,CT )t Table 5.4 The 1/s2CY LX submatrix. (a) Element of (a) VCy BLC ,CT for an LC-filter. VLx 1 (b) Element of TCT ,LC for an (b) ICy LC-filter ILx 1 Table 5.5 The 1/s2 (a) VCy1 VCy2 RX1 RX2CY 1CY 2 submatrix. VRx1 1 0 (a) Element of BCT ,RC for an VRx2 0 1 RC-circuit. (b) Element of (b) ICy1 ICy2 TCT ,RC for an RC-circuit IRx1 0 1 IRx2 −1 0 The networks to be considered are connected, linear, time-invariant LC-filters. It is assumed that any independent voltage source has been replaced by a dependent voltage source controlled by the desired output variables, thus forming a closed system [6]. For instance, the fundamental circuit matrix (BVT )LC and the transpose of the cut- set matrix (TCI )LC “ ((−QCI )t )LC for LC-filters with independent current sources (the inductors in the cotree branches and the capacitors in the tree branches), can be presented as follows (see Table 5.3). Each single element 1/s2Cx Ly of the submatrices BLC ,CT , TCT ,LC (see Table 5.4) may be replaced by two capacitors and two resistors Cx1 , Cx2 , Ry1 , Ry2 in appropriate configuration (see Table 5.5). It has been shown in [9] that 16 combinations are possible to generate the equivalent submatrix. It is easy to notice that this configuration of capacitors and resistors has also dimension of 1/s2 (i.e. the term: 1/s2 Ry1 Ry2Cx1Cx2 ) in the network function, similarly as the inductor L and the capacitor C (i.e. the term: 1/s2 LyCx )). According to Table 5.5, it is obvious that the equivalent RC-circuit should have special kind of switches, i.e. switches that connect in the different ways the voltage and the current graphs. Indeed, and as an example, (V(RX1 ) “ V(CY 1 ) and V(RX2 ) “ V(CY 2 )), however, (I(CY 1 ) “ I(RX2 ) and I(CY 2 ) “ −I(RX1 )). It has been shown in [10] that nullors can ensure such special switching functions. In the following the switches are represented in the voltage position, i.e. the short- cut position fulfils the relations imposed by the voltage graph, whereas the open position is relative to the current graph. 5 Active Filter Design Using a Two-Graph Based Transformation Technique 111 Fig. 5.1 A lossless parallel LC-filter (corresponding IL (BVT )LC and IC (TCI )LC “ ((−QCI )t )LC matrices are given in VC I in L C Table 5.6): Example #1 Table 5.6 (BVT )LC and (a) VC (TCI )LC “ ((−QCI )t )LC for VIin −1 lossless parallel LC-filters with independent current. VL 1 (a) (BVT )LC (b) IC (b) (TCI )LC “ ((−QCI )t )LC Iin −1 IL 1 Table 5.7 (BVT )LC and (a) VC1 VC2 (TCI )LC “ ((−QCI )t )LC for lossless RC-filters with VIin −1 0 independent voltage source. VR1 0 1 (a) (BVT )LC (b) (TCI )LC VR2 1 0 (b) IC1 IC2 Iin −1 0 IR1 1 0 IR2 0 −1 5.2.2.1 Application Example #1 As an application example, let’s consider the lossless LC-filter presented in Fig. 5.1. The basic idea consists of replacing the inductor L, from the cotree branch, by a capacitor C in the tree branch and adding elements to change directions of the transmissions (from the current to the voltage on the direction from the voltage to the current). This function can be realized using resistors, which will be placed, in the cotree branches of the graph. Accordingly, the B and T matrices, given in Table 5.6 will be modified as given in Table 5.7. It is simple to check that in this RC- configuration we have a similar network functions as in the LC-circuit. For example, in the LC-circuit the voltage on the capacitor C is given by expression (5.2) and for the RC-circuit, the output voltage is given by (5.3). sL VC “ I 1+s2 LC in (5.2) sR1 R2C2 Vout “ I 1+s2 R1 R2C2 in (5.3) 112 M. Fakhfakh and M. Pierzchała Fig. 5.2 A bi-band filter: Example #2 L2 Vout I in RS C1 L1 C2 Table 5.8 B and T matrices (a) VL1 VL2 of the bi-band circuit of Fig. 5.2. (a) The B matrix. VIin −1 0 (b) The T matrix VRS 1 0 VC1 1 0 VC2 1 −1 (b) IC1 IC2 Iin −1 0 IRS 1 0 IC1 1 0 IC2 1 −1 Table 5.9 B and T matrices of the RC equivalent circuit. (a) VR1 VR2 VR3 VR4 (a) The B matrix. (b) The T VIin −1 0 0 0 matrix VRS 1 0 0 0 VC1 1 0 0 0 VC2 0 1 0 0 VC3 1 0 1 0 VC4 0 0 0 1 (b) IR1 IR2 IR3 IR4 Ii 0 −1 0 0 IRS 0 1 0 0 IC1 0 1 0 0 IC2 −1 0 0 0 IC3 0 1 0 1 IC4 0 0 −1 0 5.2.2.2 Application Example #2 As a second application example, let us consider the bi-band circuit presented in Fig. 5.2, where two inductors are considered; a grounded inductor and a floating one. Table 5.8 presents the corresponding B and T matrices. By adopting the proposed method of transformation of the inductor using capacitors and resistor, the following matrices can be constructed. Using the software proposed in [11], it is easy to compute both transfer functions using the B and T matrices corresponding to Tables 5.8 and 5.9, respectively. 5 Active Filter Design Using a Two-Graph Based Transformation Technique 113 Fig. 5.3 Screenshot of the transfer function corresponding to Table 5.8 obtained using [11]. (a) The product matrix coefficients. (b) The numerator coefficients. (c) The denominator coeffi- cients Coefficients relative to the numerator and to the denominator of both transfer functions are given in Figs. 5.3 and 5.4, respectively. Thus, by identifying results shown in Figs. 5.3 and 5.4, we have: C1 “ C2 , C2 “ C3 , L1 “ R2 R1C1 and L2 “ R4 R3C4 . Accordingly, the “switched” circuit can be constructed. Figure 5.5 presents the equivalent “switched” circuit that satisfies the relationships presented in Table 5.9. 114 M. Fakhfakh and M. Pierzchała Fig. 5.4 Screenshot of the transfer function corresponding to Table 5.9 obtained using [11]. (a) The product matrix coefficients. (b) The numerator coefficients. (c) The denominator coeffi- cients R4 C3 C2 Vout Iin RS C1 R2 R1 C4 R3 Fig. 5.5 The “switched” circuit obtained from Table 5.9 5 Active Filter Design Using a Two-Graph Based Transformation Technique 115 5.3 Designing Lossy Filters In the following, we propose the application of the above-introduced technique to the synthesis of active lossy filters while minimizing the number of additional resistors. Let’s consider the lossy filter given in Fig. 5.6. The corresponding B and T matrices are given in Table 5.10. Coefficients of the transfer function of the passive RLC circuit are given in Fig. 5.7. Applying the technique introduced above, allows removing the two inductors and replacing each of them by two resistors and one capacitor. Accordingly, the modified B and T matrices can be presented, as it is given in Table 5.11. It is possible to further simplify the equivalent circuit that can be constructed from Table 5.11. Indeed, one can notice that the contribution of resistor R2 , i.e. the term s powered to 1 in the corresponding product matrix can be reproduced by substituting that resistor by another one from those already encompassed in the table, i.e. in the new RC-circuit. Four candidates exist, namely Rd1 , Rd2 , Rd3 and Rd4 . Using the symbolic analyzer proposed in [11], one can easily check that only Rd3 and Rd4 allow obtaining the expected transfer function that is equivalent to the ideal LC-circuit transfer function. Fig. 5.6 An RLC biband filter: Example #3 Table 5.10 B and T matrices of the circuit shown in (a) VL1 VR2 VL2 Fig. 5.6. (a) The B matrix. (b) VIin −1 0 0 The T matrix VR1 1 0 0 VC1 1 0 0 VC2 1 −1 −1 (b) IL1 IR2 IL2 Iin −1 0 0 IR1 1 0 0 IC1 1 0 0 IC2 1 −1 −1 116 M. Fakhfakh and M. Pierzchała Fig. 5.7 Screenshot of the transfer function corresponding to Table 5.10 obtained using [11]. (a) The numerator coefficients. (b) The denominator coefficients. (c) The product matrix coeffi- cients For example, Table 5.12 gives B and Q tables corresponding to the substitution of R2 by Rd3 . The corresponding transfer function can be obtained using [11]. Figure 5.8 gives coefficients of the transfer function (numerator and denominator) and the corresponding product matrix elements. Accordingly, we have L1 “ Rd1 Rd2Cd1 , and L2 “ Rd3 Rd4Cd2 . 5 Active Filter Design Using a Two-Graph Based Transformation Technique 117 Table 5.11 B and T matrices (a) VRd1 VRd2 VR2 VRd3 VRd4 of the active circuit equivalent to the passive circuit shown in VI 0 −1 0 0 0 Fig. 5.6. (a) The B matrix. VR1 1 0 0 0 (b) The T matrix VC1 0 1 0 0 0 VCd1 1 0 0 0 0 VC2 0 1 −1 −1 VCd2 0 0 0 1 0 (b) IRd1 IRd2 IR2 IRd3 IRd4 I −1 0 0 0 0 IR1 1 0 0 0 IC1 1 0 0 0 0 ICd1 0 −1 0 0 0 IC2 1 0 −1 −1 0 ICd2 0 0 0 0 −1 Table 5.12 Substitution of R2 by Rd3 . (a) The modified (a) VRd1 VRd2 VRd3 VRd4 B matrix. (b) The modified T VI −1 0 0 matrix VR1 1 0 0 VC1 1 0 0 VCd1 1 0 0 0 VC2 0 1 −1 −1 VCd2 0 0 1 0 (b) IRd1 IRd2 IRd3 IRd4 I −1 0 0 0 IR1 1 0 0 IC1 1 0 0 0 ICd1 0 −1 0 0 IC2 1 0 −1 0 ICd2 0 0 0 −1 In order to design an equivalent circuit that reproduces the current and voltage relationships given by the B and T matrices given in Table 5.12, the use of the special switches is mandatory, as it was explained above. The equivalent circuit is shown in Fig. 5.9. As introduced in [9], nullors can emulate such weird behavior of switches. Accordingly, a nullor based circuit can be constructed. The equivalent circuit is shown in Fig. 5.10. Knowing that a nullor can be considered as a universal element since it can reproduce the ideal behavior of many circuits, such as an Op-Amp, a current conveyor etc. The later was used to design the equivalent “switched” circuit. Figure 5.11 gives the current conveyor based RC-circuit. The circuit presented in Fig. 5.11 was designed using the second generation current conveyor used in [9]. In Fig. 5.12 we present corresponding SPICE simulations, where we notice a good agreement between the ideal LC-filter 118 M. Fakhfakh and M. Pierzchała Fig. 5.8 Screenshot of the transfer function corresponding to Table 5.12 obtained using [11]. (a) The numerator coefficients. (b) The denominator coefficients. (c) The product matrix coeffi- cients Fig. 5.9 The “switched” circuit (according to Table 5.12) 5 Active Filter Design Using a Two-Graph Based Transformation Technique 119 Fig. 5.10 The nullor based circuit that is equivalent to the “switched” circuit shown in Fig. 5.10 Fig. 5.11 The equivalent current conveyor based filter 70 60 Active RC filter 40 Passive RLC filter 20 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz Frequency Fig. 5.12 (Vout /Iin )dB “ f (frequency) response and the active RC-circuit. Component values are as follows: R1 “ 1 kΩ, C1 “ 1 nF, Rd2 “ 1 kΩ, C2 “ 1 nF, Rd1 “ 1 kΩ, Cd1 “ 1 nF, Rd4 “ 1 kΩ, Cd2 “ 10 nF, R2 “ 100 Ω. 5.4 Conclusions The use of the two graph technique for the synthesis of active filters was detailed in this chapter. Firstly, designing lossless filters was presented. Then, adapting this technique to the design of active lossy circuits was proposed. Minimizing the use 120 M. Fakhfakh and M. Pierzchała of passive components, i.e. additional resistors, was also proposed. Designing such lossy active filter using “active” switches, and then using current conveyors, was highlighted. Application examples were given and SPICE simulation results were provided to show viability of the proposed technique. References 1. Haigh DG, Clarke TJ, Radmore PM (2006) Symbolic framework for linear active circuits based on port equivalence using limit variables. IEEE Trans Circ Syst I, Regular Papers 53(9):2011–2024 2. Biolek D, Biolkova V (2011) Modified nodal analysis. In: Fakhfakh M, Tlelo-Cuautle E, Fernandez FV (eds) Design of analog circuits through symbolic analysis. Bentham Science Publisher, United Arab Emirates 3. Haigh DG, Radmore PM (2006) Admittance models for the nullor using limit variables and their applications to circuit design. IEEE Trans Circ Syst I, Regular Papers 53(10):2214–2223 4. Haigh DG (2006) A method of transformation from symbolic transfer function to active RC-circuits by admittance matrix expansion. IEEE Trans Circ Syst I, Regular Papers 53(12):2715–2728 5. Mielke RR (1978) A new signal flowgraph formulation of symbolic network functions. IEEE Trans Circ Theor CT-25(6):334–340 6. Lin P-M (1991) Symbolic network analysis.Elsevier Amsterdam 7. Rodanski BS, Hassoun M (2003) Symbolic analysis. In: Chen, WK (ed) The circuits and filters handbook, CRC Press, New York 8. Pierzchala M, Rodanski B (2004) Two-graph stamps for linear controlled sources. In: The international workshop on symbolic analysis and application in circuit design, SMACD. Wroclaw, Poland 9. Pierzchala M, Fakhfakh M (2011) Tranformation of LC-filters to active RC-circuits via the two-graph method. Microelectronic J 42(8):999–1005 10. Rodanski B (2002) Extension of the two-graph method for symbolic analysis of circuits with non-admittance elements. In: The international workshop on symbolic analysis and application in circuit design, SMACD, Sinaia, Romania 11. Pierzchala M, Fakhfakh M (2008) An open environment for calculating expanded symbolic network function. In: The international workshop on symbolic and numerical methods, modelling and application in circuit design, SM2ACD. Erfurt, Germany Chapter 6 Analog Baseband Filter Design Considerations for Wireless Receivers Jose Silva-Martinez and Raghavendra Kulkarni 6.1 Introduction Wireless systems have received significant attention in the recent years due to increased demand for high performance yet portable handheld receivers. This demand coupled with continued device scaling has led to design of multi-million transistor system-on-chip (SoC) solutions with rich digital signal processing (DSP) capabilities. A simple block level partitioning of the receiver is shown in Fig. 6.1. In addition to digital demodulation and signal processing, SoC solutions also require a high performance RF (radio-frequency) receiver in the signal chain. The RF front-end and analog-baseband can be termed as radio. The goal of radio is to deliver the desired signal to the demodulator with tolerable impairments (due to circuit non- idealities). Wireless receivers must extract a weak desired signal buried within a crowded spectrum from plethora of standards supporting variety of analog and digital modulation formats. Successfully tolerating and rejecting undesired spectral content (termed as blockers) within the vicinity of the desired signal demands attentive planning of the analog signal processing chain that precedes the digital demodulator. In the absence of RF pre-filtering, analog baseband signal chain must efficiently handle the blocker power along with the desired signal prior to the analog-to-digital converter (ADC). As a result, the incoming blocker profile affects design of the baseband filter and requirements of a subsequent ADC in the signal chain. Design of analog baseband for a direct-conversion UHF receiver serves as an example to underscore the impact of blockers in this chapter. Section 6.2 highlights the importance of out-of-band linearity specifications and also presents a systematic analysis to understand the interlaced filter specifications and ADC dynamic range (DR) requirements. Two popular filter approximations (Butterworth and Inverse J. Silva-Martinez () • R. Kulkarni Texas A&M University, College Station, TX, USA e-mail: [email protected]; [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 121 DOI 10.1007/978-1-4614-1383-7 6, © Springer Science+Business Media New York 2013 122 J. Silva-Martinez and R. Kulkarni “RADIO” “DSP” Analog Digital Signal-Processing Signal-Processing User Interface RF Front-end Demodulator and Air Analog Baseband Decoding other features Interface Analog-to-Digital Fig. 6.1 Block level partitioning of a modern wireless device Chebyshev) are evaluated for blocker filtering efficacy in the presence of analog and digital adjacent blockers since UHF spectrum (470–860 MHz) contains spectral content from both analog and digital modulation sources [1,2]. Section 6.3 provides implementation details of a filter for the UHF receiver example followed by experimental results of the filter and the receiver in Sect. 6.4. 6.2 Analog Baseband Dynamic Range Requirements A wireless receiver using the direct conversion architecture is shown in Fig. 6.2. The input signal is down-converted (frequency translated from RF passband to lowpass baseband using I/Q demodulation), amplified, filtered by the analog baseband and after A/D conversion is presented to the demodulator. The RF and the baseband signal chain preceding the demodulator is often treated as an impairment block affecting the system performance. The quality of the delivered signal measured by the ratio of desired to undesired signal power (including phase noise, quantization noise, thermal noise and other impairments) depends on the modulation scheme and the bit-error-rate (BER) requirement of the system. Blockers present at the RF input create several challenges since the entire input spectral content should be handled by the receiver front-end without degrading the signal quality for demodulation. For the UHF spectrum example, the undesired analog and digital adjacent blockers could be up to 40 dB higher than the desired signal power raising DR requirements of the receivers. LNAs in the RF signal chain provide broadband amplification and do not perform any channel-selection filtering. But an I/Q demodulator implemented using a passive current-mode mixer can be terminated using a transimpedance amplifier to implement a single-pole that provides first order filtering after signal down-conversion. This filter provides attenuation for blockers located far from the desired channel, but leave the spectral energy from immediate adjacent channels almost un-filtered. As a result majority of the near broadband spectral energy shows up un-filtered at the input of the analog baseband section. Typically, analog baseband signal chains utilize cascaded filtering 6 Analog Baseband Filter Design Considerations for Wireless Receivers 123 (Optional) Analog Baseband Off-chip band- I/Q Digital LNA Demod. A/D select Demodulation filter RF Cascaded filter and Input variable gain stages Fig. 6.2 A typical wireless radio using direct conversion architecture and gain stages as shown in Fig. 6.2. While filtering stages reduce the blocker power successively, the gain stages increase the desired signal. In the following sections we will address how the presence of blockers affects the performance specifications of the analog baseband, and the resolution and cost of a subsequent ADC. 6.2.1 Spurious-Free-Dynamic-Range Requirements As the signal is processed in the baseband chain, the signal gets corrupted due to additive noise from the active devices and nonlinear distortion components due to weakly-nonlinear behavior of these active devices. While the magnitude of the additive noise is independent of the input signal power, magnitude of the distortion generated depends on input signal to the active device. Higher the magnitude of the input power, larger the distortion. Although signal-to-noise ratio (SNR) increases by increasing the input power, the signal-to-distortion ratio (SDR) drops with increasing input power. This is indeed very critical for the design of first filtering blocks in the baseband signal chain when the blocker is relatively unattenuated. Hence we should expect an optimal input signal power at which the overall signal- to-noise-and-distortion ratio (SNDR) can be maximized. This SNDR value denotes the available Spurious-Free-Dynamic-Range (SFDR) of the system. An example of the effect of distortion due to out-band blocker on signal dynamic range is shown in Fig. 6.3. The figure plots the desired signal power, blocker power, integrated noise power (input referred) and 3rd order intermodulation distortion (IM3) power (input referred) as the input signal increases on a log–log scale. The blocker is UDdB “ 30 dB higher than the desired signal power (UD denotes undesired-to-desired ratio). The distortion power is generated due to the intermodulation of two un-filtered out-band blockers such that the IM3 term falls in-band. In this example, the integrated noise power is independent of the input power and is indicated at −76 dBm (or 40 uVrms), while the linearity performance is specified at different third-order intercept points (IIP3) of +20 to +35 dBm. As expected, IM3 power increases with a slope of +3 dB/dB with the input power while the desired (or the fundamental) increases with a slope of 1 dB/dB. As indicated in the figure, the distortion power rises out of the output noise floor at different 124 J. Silva-Martinez and R. Kulkarni 10 IIP3 = 20dBm 0 −2dBm IIP3 = 25dBm Input Referred Power Level (dBm) −10 Blocker Power IIP3 = 30dBm IM3=74dBc −20 IIP3 = 35dBm −30 Desired Power −40 −50 UDdB = 30dB 33dB 43dB −60 Peak SNDR Power of IM3 tone −70 −80 Noise Floor = −76dBm=40uVrms −90 −80 −70 −60 −50 −40 −30 −20 −10 Desired Signal Power Level (dBm) Fig. 6.3 Typical desired, blocker and intermodulation signal power for different out-band IIP3 values input power levels depending on the linearity performance. Higher the out-band IIP3, higher is the blocker power (and hence the signal power for a given UDdB ) at which the distortion power rises above the noise floor. Any increase in the blocker power beyond this will result in SNDR of the desired channel being limited by the distortion power, while any reduction in the signal power leads to drop in the SNR. As illustrated, compared to general filtering applications, analog baseband section of a wireless receiver signal chain exhibits an important difference. Inter- modulation of out-of-filter-band blockers generates output terms that reside together with the desired signal affecting the signal quality. In summary, with regard to baseband SFDR requirements, we make the following observations relevant to design of filters for wireless receivers, • For low input power levels of the desired channel, the input referred noise of the analog baseband must be minimized such that the in-band SNR does not limit the system performance. • Since the input power levels of the desired channel are lower than the blocker power, distortion components generated due to in-band signals do not limit the SDR. • Distortion due to large out-of-band blockers (UDdB higher than desired) can limit the overall SNDR performance. Analog baseband must exhibit very good out-of- band linearity performance to keep the distortion components below noise floor. Hence blocker tolerance is very critical in the first filtering blocks in the signal chain after signal down-conversion. 6 Analog Baseband Filter Design Considerations for Wireless Receivers 125 Pk-to-Avg Ratio 9d B (PAR) PRF,max ADC Fullscale PAR 9dB Blocker 40dB Filter Power Residual Blocker Total ADC DR Power Signal Variation -AGC Input signal C Variation AG 40dB SNRdesired 25dB PRF,min Margin 20dB SNRdesired 25dB Nreceiver ADC Noise Floor NFdB 5dB DRmin> 54dB (kTB)dBm At LNA Input At ADC Input Fig. 6.4 Effect of filtering and AGC on dynamic range requirements from Antenna to ADC 6.2.2 Interdependence of Baseband Filter and ADC Requirements In this section we further investigate the impact of blocker power in the receiver chain at the analog baseband and ADC interface. As illustrated in Fig. 6.2, the RF input signal is sensed first at the LNA input and is processed to extract the desired spectral content. The signal DR requirements from LNA input to the ADC input in the receiver are illustrated in Fig. 6.4. Typical numbers relevant to an UHF receiver example are also indicated in the figure. As illustrated in the figure, the input noise floor of the receiver in dBm is Receiver noise floor “ Nreceiver “ (kTB)dBm + NFdB. (6.1) where B is the channel bandwidth and NFdB is the noise figure of the receiver. Then, the sensitivity of the receiver defined as the minimum desired signal power to meet the SNR requirement for the modulation scheme is, Receiver sensitivity “ PRF,min “ Nreceiver + SNRdesired . (6.2) As indicated in Fig. 6.4, the signal power of the desired channel received at the antenna can vary by up to 40 dB. In addition to this variation, undesired blocker 40 dB larger than the desired channel could appear at the LNA input (in the worst case) raising the dynamic range of the signal. Peak-to-average Ratio (PAR) indicated 126 J. Silva-Martinez and R. Kulkarni in the figure is an attribute of the orthogonal-frequency-division-multiplexing (OFDM) based modulation schemes which results due to multiple carriers. Hence the radios built for OFDM systems must budget for PAR in the DR calculations to avoid severe distortion and clipping in the signal chain. Analog baseband that resides in the signal chain after the I/Q demodulation but prior to an ADC processes the input signal after signal down-conversion and performs two important tasks: (1) filter undesired adjacent blocker power; and (2) deliver constant power to the ADC with the desired SNDR. Hence for a given input signal and blocker profile, choice of the baseband filter (order and approximation type) determines the DR of a subsequent ADC. As indicated in Fig. 6.4, ADC DR should do the following: 1. Be greater than the minimum SNR requirement of the modulation scheme plus a design margin to minimize the SNR loss due to quantization noise of the ADC. In Fig. 6.4, a 20 dB margin («3 bits) is indicated [3–5]. 2. Accommodate the peak-to-power-average ratio (PAR) of the received signal. 3. Include the input signal power variation that is not covered by automatic gain control (AGC). The residual desired signal power variation must also account for the resolution and the range of the AGC in the system. 4. Accommodate the residual unfiltered blocker power at the ADC input after the baseband filter. 5. Meet the outband linearity performance requirement based on the residual blocker power. It should be noted from Fig. 6.4 that, for the UHF receiver example the DRmin > 54 dB (« 9 bits) even assuming a perfect AGC to compensate for the input signal power variation and also complete blocker filtering prior to the ADC. In addition, the minimum sampling frequency of the ADC should be chosen to keep the undesired aliased signal power below the desired signal power by at least DRmin . The effect of Butterworth filter order on sampling frequency and resolution of the ADC has been analyzed in [6]. We focus on item (4) in this chapter and quantify the component of the ADC DR required to accommodate the residual blocker power for Butterworth and Inverse Chebyshev analog filters with orders ranging from 3 to 8.1 These two filters are chosen so that we can compare the impact of an all-pole approximation (Butterworth) and an approximation with poles and stop-band zeros (Inverse Chebyshev). The residual power evaluation is performed for both digital and analog adjacent channels as undesired blockers in the UHF receiver example can employ either modulation scheme. In analog channels, the bulk of the signal energy is concentrated near the carrier, resulting in strong peaks. In contrast, the energy in a multi-carrier modulated digital channel is spread smoothly across the 1A 1st order pole is added to an (n − 1)th Inverse Chebyshev filter for comparison to nth order Butterworth filter. This addition improves the high frequency attenuation for even order Inverse Chebyshev filters. 6 Analog Baseband Filter Design Considerations for Wireless Receivers 127 Input Power Total sub-carriers M=[f max Δf ] Pu ∇ f Input power per PN+1 subcarrier in UDdB ACdB Nth (N+1) Remaining undesired Pd In desired channel Channel Channel channels up to fmax PN+1 In (N+1) channel Pd 2fg 2Nt 2fg 2Nt Nt Pu In remaining channels 0 B 3B 5B fmax Fig. 6.5 Baseband input spectrum with digital adjacent channels channel [7]. Understanding the impact of this difference is important as analog modulation techniques continue to be used along with digital broadcast [8]. The following analysis will show that the higher order Inverse Chebyshev filters perform better at reducing the undesired power in the presence of analog adjacent channels. 6.2.2.1 Residual Undesired Power from Digital Adjacent Channels To evaluate the residual undesired power for digital channels, the baseband input spectrum is modeled as shown in Fig. 6.5. From this figure: • The input power spectral density (PSD) Sin ( f ) is defined for a broadband frequency range (0, fmax ). Sub-carriers in the input spectrum are separated by △ f , resulting in M “ ⌊ fmax /Δ f ⌋ total sub-carriers. • The desired channel resides in a single-sided bandwidth of (0, B) with Nt sub- carriers in (0, B − fg ) and a guard band fg with zero power carriers. Each undesired channel has a two-sided bandwidth of 2B with 2Nt sub-carriers in 2(B − fg ). • The input sub-carrier power in the desired channel is set to Pd . The power of sub- carriers PN+1 in the first adjacent channel (referred as the N + 1 channel) is set ACdB higher than Pd . For the remaining undesired channels (> N + 1), the power of sub-carriers Pu is UDdB higher than the desired channel. Total integrated input power Pin is f max Pin “ Sin ( f ) d f . (6.3) 0 This input spectrum is filtered using a transfer function H( f ). Hence, the integrated output power within the frequency range ( f1 , f2 ) is f2 P“ Sin ( f ) |H( f )|2 d f . (6.4) f1 128 J. Silva-Martinez and R. Kulkarni f2 2 Output Power ∫ Px = S in ( f ) H ( f ) df f1 Filter Response Px f1 f2 | H (f ) | Pdesired 0 B-f g Pd Pres,N+1 B+fg 3B-f g Nt 2f g 2N t 2f g 2Nt Pres,Total B+fg f max 0 B 3B 5B fmax freq Fig. 6.6 Output power density and definitions of integrated power in the desired channel, residual N+1 adjacent channel, and residual power in all undesired channels Table 6.1 Parameters used Parameter Values for the analysis B, f g , f max 4 MHz, 200 kHz, 396 MHz ACdB , UDdB 38 dB, 45 dB 2Nt 3800 sub-carriers Pin +6 dBm Using (4), integrated power in the desired channel (Pdesired ), the residual inte- grated power due to the N + 1 channel (Pres,N+1 ), and the residual integrated power due to all the undesired channels (Pres,Total ) are evaluated as indicated in Fig. 6.6. To quantify the component of the ADC DR required to accommodate the N + 1 channel residual power and total residual power, we evaluate Pdesired +Pres,N+1 P ResidualDRN+1 “ 10 log10 Pdesired “ 10 log10 1 + Pres,N+1 desired . (6.5) Pdesired +Pres,Total P ResidualDRtotal “ 10 log10 Pdesired “ 10 log10 1 + Pres,Total desired . (6.6) We find ResidualDRtotal and ResidualDRN+1 for Butterworth and Inverse Cheby- shev filters as the first adjacent channel power changes relative to the desired power (indicated by ACdB ). Corner frequency is set to 4 MHz for both the filters as applicable to UHF receiver example. Sub-carrier powers Pd , PN+1 and Pu are suitably adjusted to maintain fixed total input power (Pin “ +6 dBm) with UDdB “ 45 dB. Values of the other parameters are indicated in Table 6.1. Figure 6.7 shows ResidualDRtotal and ResidualDRN+1 for filters of order 3 to 8 as ACdB is varied from +10 dB to +40 dB in 10 dB step size. As expected, Fig. 6.7 indicates that the residual DR requirement for the ADC (ResidualDRtotal ) reduces with increasing filter order. The two important observations from Fig. 6.7 are: 1. If the undesired input power is dominated by high-frequency (> (N + 1)) channels (ACdB “ 10 dB), then the first adjacent channel power is easily filtered 6 Analog Baseband Filter Design Considerations for Wireless Receivers 129 a 35 ResidualDRtotal Residual Dynamic Range (dB) 30 ResidualDRN+1 25 ACdB = 40dB 20 ACdB = 30dB 15 10 ACdB = 20dB 5 ACdB = 10dB 0 3 4 5 6 7 8 Filter Order b 35 ResidualDRtotal 30 ResidualDRN+1 Residual Dynamic Range (dB) 25 ACdB = 40dB 20 ACdB = 30dB 15 ACdB = 20dB 10 5 ACdB = 10dB 0 3 4 5 6 7 8 Filter Order Fig. 6.7 Residual dynamic requirement for digital adjacent channels with (a) Butterworth filter (b) Inverse Chebyshev filter by both Butterworth and Inverse Chebyshev filters. In this case, lower order Butterworth filters (3–5) are quite effective compared to Inverse Chebyshev filters. 2. If the undesired input power is dominated by the (N +1) channel (ACdB “ 40 dB), then ResidualDRtotal ≈ ResidualDRN+1 . In this case, both Butterworth and Inverse Chebyshev filters have comparable ResidualDRtotal requirement from the ADC. 130 J. Silva-Martinez and R. Kulkarni P o wer PAN, u PAN, N+1 N th Channel Remaining Analog analog Pd Nt foffset Channel channels Frequency 0 B 3B Fmax Fig. 6.8 Analog adjacent channels with single analog carrier per channel 6.2.2.2 Residual Undesired Power from Analog Adjacent Channels Compared to digital channels, analog channels use two narrow band carriers (one for video and one for audio) located within the channel bandwidth. The video carrier is 13 dB higher than the audio carrier and is located closer to the pass band edge [2]. Hence, a single worst-case carrier at foffset from the edge of the channel is modeled as shown in Fig. 6.8. For fair comparison, the input power of the single carrier is set equal to the integrated power from the undesired digital channel. As indicated in Fig. 6.8, the power of the analog carrier in the (N + 1) adjacent channel and remaining channels is PAN,N+1 “ PN+1 (2Nt ) (6.7) PAN,u “ Pu (2Nt ). (6.8) Similar to the previous analysis, ACdB measures the difference in the desired and undesired first adjacent channel input power. As the ResidualDRtotal requirement for worst case high ACdB values is dominated by ResidualDRN+1 , the difference in the performance of the two filters is highlighted with ResidualDRN+1 . For foffset “ 1.25MHz, ResidualDRN+1 for Butterworth and Inverse Chebyshev filters are evaluated and the results are shown in Fig. 6.9. The key observations are: 1. For lower filter orders (3 to 5), both Butterworth and Inverse Chebyshev filters provide similar attenuation for the adjacent analog channel leading to comparable ResidualDRtotal requirement from the ADC. 2. For higher order Inverse Chebyshev filters (7 and 8), the ResidualDRN+1 is 12dB lower than that for Butterworth filters. This improvement results from the sharp transition band and nulls in the transfer function due to stop-band jω -axis zeros in the Inverse Chebyshev approximation. 6 Analog Baseband Filter Design Considerations for Wireless Receivers 131 40 ACdB = 40dB Butterworth ResidualDRN+1 35 Inv Cheby ResidualDRN+1 Residual Dynamic Range (dB) 30 AC = 30dB dB 25 20 ACdB = 20dB 15 10 ACdB = 10dB 5 0 3 4 5 6 7 8 Filter Order Fig. 6.9 Residual dynamic range for the analog adjacent channel In summary: (1) Low order Butterworth filters are more efficient at reducing the undesired blocker power when it is dominated by far out blockers (> N + 1) for both digital and analog modulation; (2) Butterworth and Inverse Chebyshev filters provide comparable performance when the residual power is dominated by the (N + 1) channel with digital modulation; and (3) Higher order Inverse Chebyshev filters (orders 7 to 8) are favorable than Butterworth filters when the residual power is dominated by the (N + 1) channel with analog modulation. The drop in the required ADC DR due to filtering translates to reduction in ADC power consumption. ADC power consumption has a strong structural dependency [9]. According to [10], the power efficiency of the ADC for a given SNDR can be predicted using power per conversion bandwidth (P/ fsig ) metric. Published ADC data indicates that P/ fsig increases approximately at 2X per additional bit but may approach 4X per additional bit for noise limited high DR ADCs [10, 11]. Based on the survey in [11], we estimate the power consumption of a 4 MHz signal bandwidth ADC as shown in Fig. 6.10. This estimation shows that drop in ADC power consumption due to filtering depends on the targeted SNDR and filtering can result in significant ADC power saving for high SNDR ranges. Low order Butterworth filters fare better than low-order Inverse Chebyshev filters if the undesired power is dominated by far out blockers. But in the presence of a strong (N + 1) blocker, high order Inverse Chebyshev filters have either similar(digital blocker) or better (analog blocker) performance than Butterworth approximation of the same order. As quantified by the previous analysis, Inverse Chebyshev filters offer up to +12 dB additional ADC DR reduction in the presence of strong analog adjacent blockers. 132 J. Silva-Martinez and R. Kulkarni 105 Estimated ADC Power Consumption (mW) 104 103 102 101 100 10−1 Published ADC data scaled 10−2 to 4MHz signal bandwidth Trendline 10−3 10 20 30 40 50 60 70 80 90 100 110 SNDR Fig. 6.10 Estimated ADC Power consumption (for 4 MHz signal bandwidth) based on the data in [11] Hence for the UHF receiver example case, to tolerate the presence of strong (N + 1) adjacent channels (both analog and digital), Inverse Chebyshev approxima- tion is selected for implementation as detailed in the following section. 6.3 Circuit Implementation Building block specifications for the UHF receiver and the analog baseband can be obtained using the cascaded noise figure and IIP3 equations ‘ [12, 13]. For the analog baseband, the input referred noise should be < 31nV / Hz over a 4 MHz bandwidth, which translates to −73 dBm (using a 75Ω reference). The RF front-end includes a variable gain LNA and a passive mixer for I/Q demodulation with a +18dB gain. The RF take over point (i.e. when the LNA switches from gain to attenuation) is set to −20 dBm at the output of the LNA. This condition sets the blocker tolerance requirement and hence the out-band IIP3 of the analog baseband should be over 33 dBm to tolerate two input blockers at −2 dBm each. Also, based on the analysis in the previous Section, an Inverse Chebyshev ap- proximation is chosen for the 4 MHz bandwidth filter to provide >29 dB attenuation at 5.25 MHz for the implementation. This results in an 8th -order approximation with pole-zero locations as indicated in Table 6.2. Excellent linearity performance of active RC filters makes them suitable for broadband receivers [14–20]. However, the accuracy of pole-zero ratios limits roll- off sharpness, and process variations limit the absolute accuracy in active RC filters unless an automatic tuning scheme is employed. The complexity of the filter tuning scheme to mitigate this variation depends on the desired precision. In contrast, 6 Analog Baseband Filter Design Considerations for Wireless Receivers 133 Table 6.2 Pole-zero placement for baseband inverse chebyshev approximation Complex pole pairs (MHz) Complex zero pairs (MHz) Realization 4.05/5.40, Q “ 0.71 21.89/29.19 Active RC (Zero not realized) 4.66/6.21, Q “ 0.52 7.69/10.25 Switched capacitor 3.49/4.66, Q “ 1.23 5.14/6.85 Switched capacitor 3.21/4.29, Q “ 3.79 4.35/5.81 Switched capacitor 8th order Low Pass Inverse Chebyshev Approximation (3/4 MHz bandwidth setting) Coarse Tuning +/-10% Discrete Time Mixer + − Output − + Switched capacitor PGA Active RC filter cascaded biquads Passband gain: 0 dB -6 to +18dB 0 to +18dB 0 to +12dB Fig. 6.11 Analog baseband architecture switched capacitor (SC) filters can implement precise transfer functions without tuning but require anti-alias filtering. A 700 kHz SC filter for channel selection using an anti-alias filter with >2X larger bandwidth (1.5 MHz) has been reported in [21]. A solution that implements an SC ladder filter with embedded anti-aliasing has been reported previously [22]. The required frequency and gain programmability of the baseband filter in this work precludes the use of such hybrid ladder architecture. 6.3.1 Cascaded Hybrid Baseband Architecture The hybrid active RC and SC filter with built-in anti-aliasing shown in Fig. 6.11 is suitable for realizing cascaded transfer functions. The desired Inverse Chebyshev approximation is realized as a cascaded function of 4 biquad stages [23, 24]. Each biquad transfer function is given by 2 s 1+ ωz,i Hi (s) “ Ki 2 , (6.9) s s 1+ ω p,i Q p,i + ω p,i where Ki is the DC gain, ω p,i is the location of the complex pole-pair with quality factor Qi , and ωz,i is the location of the jω -axis zero pair. The required anti-aliasing transfer function is realized using a part of the Inverse Chebyshev approximation. Thus, the overall filter transfer function is ′ H(s) “ H1 (s) H2 (s) H3 (s) H4 (s), (6.10) 134 J. Silva-Martinez and R. Kulkarni Gain Decoder Control Switch Control Ru Ru Ru Ru 8R sw R4 C5 4R sw Ru Ru Ru Ru Mixer R1 R3 - Ru Ru Output 2R sw C2 + 2R sw R sw R sw - Vout Nominal Design Values + (For 4MHz setting) R1 3.12 kΩ C5,C2 7.8pF, 35.1 pF R4, R3 3125 , 781Ω Nominal Design Values Ru 732Ω m= (R3/R1) 0.25 Rsw 2.5V NMOS device n = (C2/C5) 4.5 4(6.4µm/0.32µm) Fig. 6.12 Active RC multi-feedback-filter and programmable gain amplifier (single-ended structure shown) ′ where H2 (s), H3 (s), and H4 (s) are realized with SC filters while H1 (s) is approx- imated from H1 (s) by ignoring the highest zero pair from the Inverse Chebyshev approximation (29 MHz in Table 6.2) to provide anti-aliasing. The cascaded SC biquads implement precise stop-band zeros to provide accurate transition band positioning. 6.3.2 Active RC Implementation Single-opamp multi-feedback (MFB) filter structure shown in Fig. 6.12 is used to ′ implement H1 (s). This structure has the advantages of low sensitivity (to Q and ωo variations) as well as low power consumption. The transfer function of the filter is given by ′ K1 H1 (s) “ 2 (6.11) 1 + ω p Q p + ωsp s where ? R4 1 n K1 “ ; ωp “ ? ; Qp “ ? b (6.12) R1 RC mn 2 m + m1 6 Analog Baseband Filter Design Considerations for Wireless Receivers 135 with K1 “ 1, R1 “ R4 “ R, resistor ratio m “ RR31 and a capacitor ratio n “ CC2 . For 5 a given Q p , m and n are interdependent and thus cannot be set independently. The output spot noise spectral density for the filter is 2 a 2 s n 1 2 1 + 2ω p m v2on “ 16 kTR 2 + 8 kTmR 2 1 + ω psQ p + ωsp 1 + ω psQ p + ωsp 2 2 2 1 + ω sQ + ωs z z z 2 + vamp 2 , (6.13) 1+ s s ωpQp + ωp where v2amp is the input referred noise density of the amplifier. The first term repre- sents the noise contribution from R1 and R4 ; the second term represents the noise contribution from R3 “ mR; and the third term represents the noise contribution from the amplifier. Parameters ωz and Qz are ? ? 2mn ωz “ ω p 2; Qz “ . (6.14) (2m + n + 1) For a fully differential filter, the total capacitance is Ctotal “ C22 + 2C5 “ ( n2 + 2)C. For a given Ctotal , depending on the choice of m (and hence n as set by Q p ), the integrated noise is plotted in Fig. 6.13. The optimum range of resistor ratio m for reducing the noise for a given capacitance budget is in the range 0.2–0.4. Hence, we choose m “ 0.25 (resulting in n “ 4.54) and size the capacitors accordingly to meet the noise figure requirement. Programmable capacitors C2 and C5 (cf. Fig. 6.12) are adjusted using digital control bits to implement 3 and 4 MHz bandwidth settings in the filter. The filter linearity requirement (IIP3 > 33 dBm) sets the minimum loop-gain in the filter passband to suppress distortion adequately. The minimum loop-gain and hence, the gain-bandwidth (GBW) of the amplifier is obtained using simulations and thus, we designed a two-stage Miller amplifier with 160 MHz GBW. The amplifier consumes 2.15 mA from a 1.8 V supply. The input resistor R1 (3.12 kΩ ) is split into two 1.56 kΩ resistors with an addi- tional shunt-capacitance (single-ended 10pF ) resulting in 3rd order filter to further enhance the anti-aliasing and rejection of far-out blockers. For a fully differential implementation (floating 5pF), the additional capacitance simply provides a low impedance return path and recirculates the high frequency blocker power, improving the blocker tolerance and relaxing the out-band linearity requirements of the subsequent filter stages. The additional capacitance also limits the noise bandwidth and hence the integrated output noise contribution from the input resistor R1 . A continuous time programmable gain amplifier (PGA) with a gain range of (−6 to +18 dB) follows the MFB filter. The PGA resistors are sized to minimize the 136 J. Silva-Martinez and R. Kulkarni Fig. 6.13 Variation of integrated noise for a given total capacitance budget with varying resistor ratio input-referred noise of the PGA in the maximum gain setting. The switches and resistor arrays are ratioed proportionately to keep the gain of the PGA independent of switch size to the first order. The PGA provides a low closed-loop output impedance to drive the subsequent SC filter. 6.3.2.1 SC Implementation Three cascaded SC biquads implement the transfer functions H2 (s), H3 (s), and H4 (s). Each biquad is a two integrator loop implemented using operational transcon- ductor amplifiers (OTA) as shown in Fig. 6.14. The preceding PGA allows to relax the input-referred noise density of the SC section in the maximum gain setting. For a sampling frequency of 80 MHz (Ts “ f1s “ 12.5 ns), 1 ns is budgeted for slew rate effects, 1 ns for switch resistance delay, and 0.9 ns for the non-overlapping time, yielding a Tlinear−settling on the order of 3.35 ns [25]. The desired open-loop GBW ( fu,i Hz) of each OTA is designed for 0.5% settling (6τ ). Programmable capacitor arrays (C1 , C3 and C6 in Fig. 6.14) are used in the biquads to achieve accurate gain (0 or 6 dB) and frequency programming (3 or 4 MHz). Computation of the required capacitor ratios and OTA GBW account for dynamic range node scaling and noise estimation. The noise constraint (kB T /C) determines the unit capacitor size, which in turn sets the power consumption of each 6 Analog Baseband Filter Design Considerations for Wireless Receivers 137 φ2 φ1 C0 φ1 φ2 C4 φ1 VOUT C1 C3 φ1 φ1 VIN + + C6 φ2 C2 φ2 - - G m1 C5 Gm2 φ1 φ2 (φ1 ⋅gain) φ1 _ early (φ1 ⋅gain) C5 φ2 gain _ control Fig. 6.14 Switched-capacitor biquad implementation (single-ended structure shown) OTA for a desired fu . We selected Cunit “ 113 f F (minimum value imposed by‘the process), which results in a cascaded input referred noise density <100nV/ Hz for the SC sections in the maximum gain setting. Fully differential, folded cascode transconductors (PMOS input) with switched capacitor common-mode feedback are used for the OTAs. Including the biasing circuits, the three biquads consume 6.3, 7.7, and 6.7 mA from a 1.8 V supply. The input referred noise density requirement for second and third biquads can be reduced allowing to relax the minimum Cunit and the total capacitance used in the biquads. Such a power optimization will allow to reduce the power consumption of later stages of filter. In this work, the process imposed constraint of minimum Cunit “ 113 f F, prevented such optimization. The switches are implemented with 2.5 V NMOS devices to provide headroom for the signal swing. Hence the digital clocking circuits to drive the switches are implemented using a 2.5 V digital supply. The active RC section provides 24 dB variable gain and a 3rd order filter response with an attenuation of 4 dB at 5.25 MHz. With the additional SC filter (6th order), this attenuation increases to 29 dB (42 dB) at 5.25 MHz (5.75 MHz) with an additional 18dB variable gain. This improved attenuation and variable gain consumes 37.3 mW (limited by the high Cunit of the technology in this design). The passband group delay resulting from filter response adds to the total wireless channel delay which is time-variant and has to be compensated by the adaptive channel equalizer in the digital demodulator. Frequency dependent gain and phase mismatch between I/Q branches causes sub-carrier dependent errors within the bandwidth, but can be reduced at the system-level using digital compensation techniques [26]. 138 J. Silva-Martinez and R. Kulkarni 6.4 Experimental Results The analog baseband was integrated and fabricated as part of a UHF receiver along with an RF front-end using the IBM 0.18 µm RFCMOS technology. Figure 6.15 shows the chip micrograph. Only one baseband signal path was realized (out of I and Q) in the prototype due to area constraints; however, analog performance verification only requires testing of one channel. The system occupies 2.14 mm2 of active area and was characterized in a QFN80 package. 6.4.1 Baseband Response and Residual DR Measurements The measured baseband transfer functions are shown in Fig. 6.16. Figure 6.16a shows the frequency (3 and 4 MHz) and gain programmability (−6 dB to +18 dB with 6 dB per step) of the continuous time section. Figure 6.16b shows frequency programmability of the composite hybrid filter (3 and 4 MHz options) along with the additional gain programmability of the SC section (0 to +18 dB range with 0 or 6 dB per biquad). For the 4 MHz setting, the measured frequency response indicates a stopband attenuation of >29 dB for frequencies >5.25 MHz, while the continuous time filter provides >2.8 dB attenuation at the same frequency. To measure the ResidualDR, input power spread over two channels (generated using two signal generators and a power combiner) is injected into the filter. A digital channel is generated using 64-QAM modulation employing Root-Nyquist (RNYQ) pulse shape with appropriately scaled symbol rate to generate a flat PSD through-out the channel, while an analog channel is generated using a single carrier. The output power levels between the desired and the undesired channels is suitably adjusted to vary the ACdB values to obtain a wide range of measurements. Filtered PSD is measured at both the continuous- and discrete-time outputs. Figure 6.17 shows the measured input and filtered outputs with digitally modulated desired Fig. 6.15 Chip Micrograph of the UHF receiver 6 Analog Baseband Filter Design Considerations for Wireless Receivers 139 Fig. 6.16 Measured baseband transfer function (a) continuous-time section (b) continuous- and discrete-time sections together and N + 1 adjacent channel with ACdB “ 30 dB. The PSD shows attenuation below 1 MHz due to the frequency limitation from the power combiner. Table 6.3 indicates the computed ResidualDR from measurements for near digital and analog blocker (N + 1 channel) and far out digital blocker (N + 3 channel) for varying ACdB values. The filtered PSD at the hybrid filter output for the N + 3 channel is below the output noise floor for ACdB values of 10 and 20 dB. The hybrid filter reduces the 140 J. Silva-Martinez and R. Kulkarni −60 Desired Channel N+1 Adjacent Channel −70 −80 Input −90 PSD (dBm/Hz) −100 CT output −110 SC output −120 −130 −140 0 2 4 6 8 10 12 14 Frequency (Hz) x 106 Fig. 6.17 Measured filtered output PSD with combined input of two 64-QAM digital modulated channels (desired and N+1 adjacent) with ACdB “ 30 dB Table 6.3 Measured ResidualDR with near (N + 1) and far (N + 3) blockers Continuous-time filter (dB) Hybrid filter (dB) Blocker Profile with ACdB a ⇒ 10 20 30 40 10 20 30 40 Digital (N + 1) channel 7.5 16.5 26.4 34.5 1.3 2.9 8.8 17.0 Analog (N + 1) channel 10.6 20.2 30.2 40.2 0.15 1.3 6.3 15.3 Digital (N + 3) channel 0.53 0.84 3.12 9.83 – – 0.45 0.51 a By definition, equivalent integrated power of the (N + 1) channel is (AC + 3)dB higher than the integrated power of the desired channel due to 2X integrating bandwidth of (N + 1) channel ResidualDRN+1 by +17.5 dB («3 bits using Nbits “ (DR − 1.76)/6.02) for digital N + 1 channel and +24.9 dB (≈4 bits) for analog N + 1 channel. Improvement in ResidualDRN+1 is better in the presence of analog adjacent channel for the hybrid filter as predicted by the analysis in Sect. 6.2.2. 6.4.2 System Performance Table 6.4 summarizes the experimental results of the UHF receiver and compares the entire receiver to published UHF receivers. The system linearity and noise measurement results reflect the performance of the receiver including the analog baseband. To obtain the out-band linearity performance, two out-of-channel RF tones located at N + 2 (516 MHz) and N + 4 (531 MHz) are injected at the LNA input, and the in-band distortion tone located at 1 MHz at the baseband filter output Table 6.4 Experimental results with comparison to previous work 6 Analog Baseband Filter Design Considerations for Wireless Receivers This Work [14] [15] [16] [17] [18] [20] Frequency 470–862 470–862 470–862 470–890 470–890 470–850 470–862 range 1670–1675 1400–1800 1670–1675 1670–1675 (MHz) RFVGA gain 29.2 (15.2 to −14) 40 35 >50 20 Not Available 40 range (dB) (N.A.) Channel 6/8 8 7/8 6/7/8 4 to 10 5/6/7/8 2–5 bandwidth (MHz) Maximum >80 75 85 94 to 100 86 95 95 gain (dB) Overall AGC >75 75 65 >98 80 95 103.5 range (dB) NF at Max 7.9 8.5 3.6 3.1 to 4.6 3.5/4 4.5/5 3.7/4.3 gain (dB) IIP3 at Max −8 N.A. N.A. −13 N.A. N.A. −13 gain (dBm) IIP3 (dBm) +2 at 9 dB RF attn +12 at 20 dB RF +4 at 20 dB RF −6.8 at 8 dB RF −9/−3/0.5 at −5/−6 at 64 dB +5 at 15 dB RF attna attn attn 0/6/10 dB RF system gain attn attn Power con- 120 mW (182 mWb ) 240 mW at 2.78 V 340 mW at 2.7 V 184 mW at 2.8 V 295 mW at 2.8 V 184/207 mW at 114 mW at 1.2 V sumption at 1.8 V analog 2.8 V and 2.5 V digital supply Die Size 2.14c 11.5 12.25 16 9.7 7.8 7.2 (mm2 ) Technology CMOS 0.18 µm SiGe 0.35 µm SiGe 0.35 µm SiGe 0.5 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.13 µm a Measured with an external LNA of 10 dB gain b Includes estimated additional power for Q-baseband channel 141 c Does not include the area for Frequency synthesizer and Q-baseband channel 142 J. Silva-Martinez and R. Kulkarni 20 Input referred output power level (dBm) 0 Fundamental −20 −40 −60 3rd harmoni c 3rd harmonic (at max. gain) (at 9dB RF −80 attenuation) −100 IIP3=−8dBm IIP3=+2dBm −120 −50 −40 −30 −20 −10 0 10 Input Power (dBm) Fig. 6.18 Measured linearity performance using two-tone measurement results for the system after down conversion was measured. The system IIP3 is −8 and +2 dBm for the highest gain and 9 dB RF attenuation cases, respectively as indicated in Fig. 6.18. Also, the 3rd order harmonic saturation is measured at −23 dBm for the highest gain setting but is not detected for 9 dB RF attenuation showing better linearity performance. The power consumption and the area metrics indicated for this work in Table 6.4 do not include the frequency synthesizer, and quadrature generator. The RF front end and baseband blocks consume 58 and 52 mW from a 1.8 V supply respectively. The digital clock tree to drive the SC filter switches consumes 10 mW from a 2.5 V digital supply. Compared to the previously published UHF receiver solutions, this work implemented in CMOS process offers competitive performance. 6.5 Conclusion Impact of blockers on analog baseband filter design in wireless receivers has been addressed in this chapter. Analog baseband design for an UHF receiver served as an example to illustrate the concepts. Analog baseband filters for wireless receivers must exhibit excellent out-of-band linearity performance and blocker tolerance. In addition, the analysis presented in Sect. 6.2 systematically evaluates the dynamic range requirements based on the blocker type (analog/digital), relative strength 6 Analog Baseband Filter Design Considerations for Wireless Receivers 143 (based on UDdB ), and spectral location (near or far). Analysis concludes that (1) for digital modulated channels, the majority of the undesired residual power after filtering resides in the first adjacent channel, and (2) In the presence of narrow band analog adjacent channel, high order Inverse Chebyshev filters are favorable for baseband filter implementations compared to Butterworth approximations. An implementation of the filter using a hybrid combination of continuous-time and switched-capacitor techniques is demonstrated. Acknowledgements The authors would like to recognize that the UHF receiver was developed in collaboration with Dr. Jianhong Xiao, Jusung Kim, and Hyung-Joon Jeon. The authors would like to thank the MOSIS educational research program and IBM Corp. for chip fabrication. References 1. Faria G, Henriksson JA, Stare E, Talmola P (2006) DVB-H: digital broadcast services to handheld devices. Proc IEEE 94(1):194–209 2. European Information & Communications Technology Industry Association (EICTA): Mobile and Portable DVB-T Radio Access Interface Specification,Version 1.0. Jan 2004 3. Vejlgaard B, Mopensen P, Knudsen JB (1999) Performance analysis for UMTS downlink receiver with practical aspects. In: Proceedings of IEEE Vehicular Technology Conference, pp 998–1002 4. Razavi B (1999) CMOS RF Receiver Design for Wireless LAN Applications. In: Proceedings of IEEE Radio and Wireless Conference, pp 275–280 5. Giannini V, Craninckx J, Baschirotto A (2008) Baseband analog circuits for software defined radio. Springer, Berlin, Germany 6. Jussila J, Halonen K (2004) Minimization of power dissipation of analog channel-select filter and Nyquist-rate A/D converter in UTRA/FDD. In: Proceedings of ISCAS 2004, pp IV-940-3 7. Norsworthy J. Broadband tuners for modern systems, [Online]. Available: http:// mobiledevdesign.com/images/archive/0601Norsworthy67.pdf 8. Sheng S (2009) Mobile television receivers: a free-to-air overview. IEEE Commun Mag 47(9):142–149 9. Le B, Rondeau TW, Reed JH, Bostian CW (2005) Analog-to-digital converters. IEEE Signal Process Mag 22(6):69–77 10. Murmann B (2006) Limits on ADC power dissipation. In: Steyaert M, Roermund AHM, Huijsing JHv (eds) Analog circuit design. Springer, Berlin, Germany 11. Murmann B. ADC performance survey 1997–2010 [Online]. Available: http://www.stanford. edu/„murmann/adcsurvey.html 12. Razavi B (1998) Basic concepts in RF design. In: RF microelectronics. Prentice Hall, NJ 13. Xiao J (2007) CMOS RF Front-end design for terrestrial and mobile digital television systems, Ph.D. dissertation, Dept. Electr. Comput. Eng., Texas A&M Univ., College Station, TX 14. Antoine P, Bauser P, Beaulaton H, Buchholz M, Carey D, Cassagnes T, Chan TK, Colomines S, Hurley F, Jobling DT, Kearney N, Murphy AC, Rock J, Salle D, Cao-Thong T (2005) A direct-conversion receiver for DVB-H. IEEE J Solid State Circuits 40(12):2536–2546 15. Womac M, Deiss A, Davis T, Spencer R, Abesingha B, Hisayasu P (2006) Dual-band single- ended-input direct-conversion DVB-H receiver. In: IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb 2006, pp 610–611 144 J. Silva-Martinez and R. Kulkarni 16. Iizuka K, Kawamura H, Fujiwara T, Kagoshima K, Kawama S, Kijima H, Koutani M, Toyoyama S, Sakuno K (2007) A 184mW fully integrated DVB-H tuner with a linearized variable gain LNA and quadrature mixers using cross-coupled transconductor. IEEE J Solid State Circuits 42(4):862–871 17. Vassiliou I, Vavelidis K, Bouras S, Kavadias S, Kokolakis Y, Kamoulakos G, Kyranas A, Kapnistis C, Haralabidis N (2006) A 0.18µ m CMOS Dual-band direct conversion receiver. In: IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2006, pp 606–607 18. Kim YJ, Kim JW, Parkhomenko VN, Baek D, Lee JH, Sung EY, Nam L, Park BH (2006) A multi band multi-mode CMOS direct conversion DVB-H tuner. In: IEEE International Solid- State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2006, pp 608–609 19. Vassiliou I, Vavelidis K, Haralabidis N, Kyranas A, Kokolakis Y, Bouras S, Kamoulakos G, Kapnistis C, Kavadias S, Kanakaris N, Metaxakis E, Kokozidis C, Peyravi H (2008) A 65 nm CMOS multistandard, multiband TV tuner for mobile and multimedia applications. IEEE J Solid State Circuits 43(7):1522–1533 20. Kuo M-C, Kao S-W, Chen C-H, Hung T-S, Shih Y-S, Yang T-Y, Kuo C-N (2009) A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µ m CMOS. IEEE J Solid State Circuits 44(3):740–750 21. Cho TB, Chien G, Brianti F, Gray PR (1996) A power-optimized CMOS baseband channel filter and ADC for cordless applications. In: Symposium on VLSI Circuits Digest, June 1996, pp 64–65 22. Azuma S, Kawama S, Iizuka K, Miyamoto M, Senderowicz D (2002) Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. IEEE J Solid State Circuits 37(3):349–356 23. Kulkarni R, Kim J, Jeon H-J, Xiao J, Silva-Martinez J (2010) A broadband 470–862 MHz direct conversion CMOS receiver. In: Proceedings of ISCAS, pp 2227–2230 24. Kulkarni R, Kim J, Jeon H-J, Xiao J, Silva-Martinez J (2012) UHF receiver front-end: imple- mentation and analog baseband design considerations. IEEE Trans VLSI Syst. 20(2):197–210 25. Adut J, Silva-Martinez J, Rocha-Perez M (2006) A 10.7-MHz sixth-order SC ladder filter in 0.35µ m CMOS technology. IEEE Trans Circuits Syst I Reg Papers 53(8):1625–1635 26. Horlin F, Bourdoux A (2008) Digital compensation for analog front-ends: a new approach to wireless transceiver design. Wiley, New York Chapter 7 Flexible Nanometer CMOS Low-Noise Amplifiers for the Next-Generation Software-Defined-Radio Mobile Systems Edwin C. Becerra-Alvarez, F. Sandoval-Ibarra, and J.M. de la Rosa 7.1 Introduction The increasing number of personal wireless applications demands for Radio Frequency (RF) front-ends capable to handle different standard specifications, signal conditions and battery status [1]. The trend is towards a maximum hard- ware reuse, by making as many transceiver building blocks as possible, digitally programmable, reconfigurable and compatible with mainstream nanometer CMOS technologies [2]. Among other RF circuits, the design of the LNA is specially critical, due to its early position at the very beginning of the receiver chain, that makes this block a determinant factor in the overall system performance. The LNA has to simultaneously match the antenna and to amplify weak input signals with reduced noise contribution, high linearity and isolation from the rest of the receiver chain. This problem is aggravated in the case of multi-standard applications, in which LNAs must operate over different frequency ranges, whereas keeping reduced number of passive circuit elements to increase integration [1]. The majority of multi-standard LNAs are based on the use of switchable passive networks to select the resonance frequency, thus preserving immunity to out-of-band interferers, although only one signal band is received at one time [3, 4]. Besides, E.C. Becerra-Alvarez IMSE-CNM, CSIC/University of Seville, Seville, Spain CUCEI, University of Guadalajara, Guadalajara, Mexico e-mail: [email protected] F. Sandoval-Ibarra Cinvestav-Unidad Guadalajara, Guadalajara, Mexico e-mail: [email protected] J.M. de la Rosa () IMSE-CNM, CSIC/University of Seville, Seville, Spain e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 145 DOI 10.1007/978-1-4614-1383-7 7, © Springer Science+Business Media New York 2013 146 E.C. Becerra-Alvarez et al. the use of switches forces a discrete frequency selection and introduces parasitic switch-on resistances and capacitances, with the subsequent trade-off between linearity, noise and speed. This limitation can be partially solved by using concurrent multi-band LNAs [5, 6] which allows a simultaneous reception of multiple signal bands without using switches. However, the spurs in one band may corrupt signals in the other band due to the LNA non-linear operation. A common issue in most reported multi-standard LNAs is the increase of the number of integrated passive elements (basically capacitors and inductors) as compared to their mono-standard counterparts, not offering a clear advantage with respect to using separate mono-standard LNAs [1,2]. Moreover, most circuit topolo- gies are based on stacked amplifiers (usually simple cascode) in either common- source or common-gate configuration, which are not very suited for low-voltage operation. Recently, the used of folded-cascode topology has been applied to the de- sign of LNAs, although very little has been done for multi-standard applications [7]. The work in this chapter contributes to this topic and presents the practical design and implementation of a continuously reconfigurable LNA integrated in a 90-nm CMOS technology. The circuit employs a topology which is based on MOS-varactor tuning networks to make the resonance frequency continuously programmable without needing any RF switches. The resulting circuit adapts its performance to the requirements of different wireless standards without increasing the number of inductors as compared to conventional mono-standard LNAs (considering that they are tested as stand-alone circuits). Layout-extracted simulations and experimental measurements are shown to validate the presented approach. 7.2 Background on Reconfigurable CMOS LNAs The LNA is one of the most important building blocks in RF transceivers. Its design becomes specially critical due to its early position in the receiver chain— connected just after the antenna and the RF filter. Therefore, LNA circuits have to accomplish many requirements, namely: antenna’s filter coupling for the input signal, enough gain for weak signals, low noise performance, high linearity as well as a proper isolation with respect to the rest of receiver building blocks [8]. All these requirements become more demanding in multi-standard applications, where LNAs must handle a number of different specifications within a widely programmable frequency range, while keeping an adaptive power consumption and reduced number of passive elements in order to minimize the effective area, and hence the final product cost [9]. 7.2.1 Switchable Resonant Tank As stated in the Introduction, a number of circuit techniques have been reported in the last few years to implement multi-standard CMOS LNAs [3–6, 10–16]. Some of 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 147 a b Ld1 Ld2 Ld Lg vo Vc1 Mp2 Mp3 Vc2 vi Mn1 Lg Cg vo Vc Mn2 vi Mn1 Ls Ls Fig. 7.1 Multi-standard LNA: (a) Based on switchable resonant tank [11] and (b) With an external switchable capacitor them are based on the use of a switchable passive network, as shown in Fig. 7.1a, to select the resonance frequency, thus preserving immunity to out-of-band interferers, although only one signal band is received at one time [3, 4, 10, 11]. Besides, the use of switches forces a discrete frequency selection and introduces parasitic switch-on resistances and capacitances, with the subsequent trade-off between noise and speed. Thus, if a low switch-on resistance is used, the size of transistors implementing the switches—M p2 and M p3 in Fig. 7.1a—must be enlarged, thus increasing the associated parasitic capacitances, whereas small switches lead to high switch-on resistances, with the subsequent NF degradation. Assuming that inductors Lg and Ls are ideal, the input impedance of the LNA in Fig. 7.1a is approximately given by: gmn1 1 ZinSI « Ls + + sLgs (7.1) Cgsn1 sCgsn1 where Lgs “ Lg + Ls , gmn1 and Cgsn1 are the small-signal transconductance and gate- source capacitance of Mn1 . The real part of ZinSI , given by gmn1 Ls /Cgsn1 , is usually chosen to be equal to the RF source resistance, RRF , in the band of interest. Note that the impedance derived from (7.1) is similar to the one obtained in the mono-standard case [17]. However, the LNA gain is degraded due to the effect of transistors M p2 and M p3 —connected to load inductors Ld1 and Ld2 , respectively. This can be mathematically expressed as: −gmn1 (1 + gmp2sLdn ) AvSI « (7.2) (1 + gmn1sLs + s2Cgsn1 Lgs ) (1 + s2CL Ldn gmp2 ) where gmp2 is the small-signal transconductance of M p2 , Ldn is the selected load inductor during LNA operation—either Ld1 or Ld2 —and CL is the load connected at the amplifier output. 148 E.C. Becerra-Alvarez et al. In addition to the LNA gain degradation expressed in (7.2), the effective silicon area increases significantly with the number of targeted standards and/or operation modes because the number of load inductors in Fig. 7.1a increases as well, and these passive elements are typically the most area consuming in RF integrated circuits. 7.2.2 External Switching Capacitor The problems associated to the area penalty in the LNA shown in Fig. 7.1a can be partially alleviated by switching capacitors instead of inductors. This technique— often referred to as external switching capacitor strategy [18]—is conceptually depicted in Fig. 7.1b. This LNA uses an external switchable capacitor, Cg , to change the overall gate-source capacitance of Mn1 in order to operate at two different frequencies (in this example). The switch used to either connect or disconnect Cg is implemented by Mn2 transistor. Assuming that inductors Ld , Lg and Ls are ideal, the input impedance of the LNA in Fig. 7.1b is approximately given by: Ls 1 ZiEC « gmn1 + + sLgs (7.3) Cg + Cgsn1 s (Cg + Cgsn1 ) Expression (7.3) shows that capacitor Cg allows to change ZiEC depending on the operating state of Mn2 transistor. As an illustration, Fig. 7.2a shows the variation of S11 with Cg —derived from (7.3). It can be noted how increasing Cg improves S11 performance at the price of reducing the resonant frequency. Therefore, there is a trade off between the resonant frequency and the input impedance matching. On the other hand, assuming the same considerations used to calculate ZiEC , it can be shown that the LNA gain, is approximately given by: gmn1 sLd AvEC « − (7.4) (1 + s2CL Ld ) (1 + gmn1sLs + s2Cg Ls + s2Cgsn1 Lgs ) is also degraded by Cg . The external capacitor Cg also penalizes the noise factor, which can be approxi- mated by the following expression: c ! ω γ γδ αδ 1 2 FEC « 1 + − 2|c|Qi + 1 + Qi ωci Qi α 5 5 ω γ αδ 3 2Cg Ls + + (7.5) ωci Qi α 5 where gmn1 1 gmn1 α“ ; Qi “ ; ωci “ (7.6) gdsn1 ω RRF Cgsn1 Cgsn1 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 149 Fig. 7.2 Cg effect in a LNA a with external switched 0 capacitor for: (a) S11 and Cg ≈ 0.25pF (b) NF -5 -10 S11(dB) -15 Cg ≈ 0.4pF -20 -25 -30 1.8 2.0 2.2 2.4 2.6 Frequency (GHz) b 0.5 4 3 2 1 0.4 Cg (pF) 0.3 0.2 1.5 0.1 2.5 4.5 3.5 2.5 0 1 1.5 2 2.5 3 Frequency (GHz) with gdsn1 being the small signal drain-source conductance of Mn1 ; c is the correlation factor, which has a value of −0.395 j and −0.5 j for long and short channel transistors respectively [17]; σ is a technology parameter used to model the gate noise; and γ is a technology parameter ranging from 2 3 for long-channel transistors to 2–3 for short-channel transistors [19]. As an illustration, Fig. 7.2 shows the noise increment due to Cg , derived from (7.5). Note that there is a trade off between noise performance and the maximum frequency for a given value of Cg . For example, according to Fig. 7.2b, when noise requirement is NF < 2 dB at 2 GHz, Cg must be at least 0.26 pF. 7.2.3 Multi-band LNA The aforementioned limitations can be partially solved by using concurrent multi- band LNAs [5, 6], as illustrated in Fig. 7.3, which allows a simultaneous reception of multiple signal bands without using any switches. However, this approach has two main drawbacks. On the one hand, the spurs in one band may corrupt signals in 150 E.C. Becerra-Alvarez et al. Cg1 Cg2 Cgn Ld vo vi Mn1 Lg1 Lg2 Lgn Ls Fig. 7.3 Multi-standard LNA with multi-band matching network other band due to the LNA non-linear operation [20]. On the other hand, the number of passive circuit elements—particularly inductors—increases significantly with the number of operation modes and wireless standards because each tuned band requires adding an additional LC network. The LNA shown in Fig. 7.3 must match the antenna at each resonant frequency corresponding to the different operation modes. This requirement is fulfilled when a resonant frequency is generated by each LC network. Indeed, a multi-band LNA should have the same number of input signals and resonant frequencies. Assuming ideal inductors and capacitors for the LNA shown in Fig. 7.3, the input impedance for n LC networks is approximately given by: gmn1 1 sLg1 sLgn ZinLC « Ls + + sLs + + ¨¨¨+ (7.7) Cgsn1 sCgsn1 1 − ω 2Cg1 Lg1 1 − ω 2Cgn Lgn In order to get the required resonant frequencies for the different input signals, the oscillation condition must be satisfied, yielding: 1 sLg1 sLg2 sLgn + sLs + + + ¨¨¨ + «0 (7.8) sCgsn1 1 − ω Cg1 Lg1 1 − ω Cg2 Lg2 2 2 1 − ω 2Cgn Lgn Note that the complexity of (7.8) increases with the number of LC tanks, i.e. with the number of standards being processed. The simplest case is given for n “ 1, which correspond to two resonant frequencies, with an oscillation condition given by: 1 sLg1 + sLs + «0 (7.9) sCgsn1 1 − ω 2Cg1 Lg1 Solving the above equations it can be shown that the values of Cgs1 and Lg1 in this case are given by: Cgsn1 Cg1 « (7.10) −1 + Cgsn1Ls ω12 −1 + Cgsn1Ls ω22 −1 + Cgsn1Ls ω12 −1 + Cgsn1Ls ω22 Lg1 « 2 L ω 2ω 2 (7.11) Cgsn1 s 1 2 where ω1 and ω2 stand for the resonant frequencies. 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 151 Fig. 7.4 S21 and NF variation due to gmn1 on a 25 inductively source degenerated LNA 20 Magnitude (dB) S21 15 NF 10 5 0 10 20 30 40 50 gmn1 (mS) Fig. 7.5 Coupling input a network sizing: (a) Cg1 (pF) y 3.0 (b) Lg1 (nH) 2.5 0.1 ω2 (GHz) 2.0 0.5 1.5 1 2.5 1.0 1.0 1.5 2.0 2.5 3.0 ω1 (GHz) b 3.0 8 2.5 7 ω2 (GHz) 2.0 6 1.5 2 4 1.0 1.0 1.5 2.0 2.5 3.0 ω1 (GHz) The above design equations can be used to obtain the required performance in terms of NF and gain (S21 ) for given values of the resonant frequencies. In order to illustrate the trade-off between gain and noise, Fig. 7.4 shows S21 and NF for different values of gmn1 . The dependency of the resonant frequency with respect to Cg1 and Lg1 is illustrated in Fig. 7.5, where the required values of the input coupling network can 152 E.C. Becerra-Alvarez et al. be obtained graphically. Note that there is an inverse relationship between Cg1 and Lg1 . For example, Cg1 is increased when ω1 and ω2 becomes 1 GHz respectively— see Fig. 7.5a—and Lg1 is reduced proportionally—see Fig. 7.5b. 7.3 Two-Stage Inductively Degenerated Common-Source LNA This chapter presents an alternative strategy for the implementation of reconfig- urable LNAs intended for multi-standard wireless applications. The principle of operation is based on using varactors to continuously tune the resonant frequency in the required bandwidth, without increasing the number of inductors as compared to the mono-standard case. An implementation of this idea will be discussed, considering the target requirements shown in Table 7.1, that covers four standards, namely: GSM, WCDMA, Bluetooth and WLAN. These requirements were obtained from experimental results reported by several ICs involving stand-alone LNAs and direct conversion receivers [12, 21–29]. Note from the data in Table 7.1 that Bluetooth has the least demanding NF requirement, which results in the lowest power consumption. On the other hand, GSM requires the minimum value of NF. In general, it should be noticed that the overall requirements for a multi-standard LNA could be more restrictive than the mono-standard case, since the same circuit can not be optimized (in terms of target specifications and power consumption) for all operation modes involved. Figure 7.6 shows the schematic of the LNA proposed in this chapter. The circuit employs a two-stage topology to separately control the input impedance and the signal gain. A MOS-varactor tuning network is used in both stages in order to make the resonance frequency programmable without penalizing the LNA noise performance. The input stage—formed by transistors MnNF and M pNF1,2 —uses an inductively degenerated common-source structure to provide a specified real part for the input impedance and signal gain at a given frequency. The output stage is made up of transistors MnG and M pG1,2 , in order to provide higher gain without significantly degrading the noise performance. Strictly speaking, this proposal adds several properties of well-known topologies in a unique reconfigurable architecture in order to minimize power consumption, reduce integration area and low cost by making an extensive use digital signal processing. Table 7.1 Design requirements for the inductively degenerated common- source two-stage LNA Standard Bandwidth (GHz) NF (dB) S21 (dB) IIP3 (dBm) GSM (PCS 1900) 1.85–1.99 4.2 11.5 −7.0 WCDMA (Band I) 1.92–2.17 3.2 14.0 −21.0 Bluetooth 2.40–2.48 4.7 12.5 −3.5 WLAN (b/g) 2.40–2.48 4.5 15.5 −5.4 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 153 Programmable Load MpNF1 MpNF2 MpG1 MpG2 Bonding PAD IbG PAD PADs IbNF RNF RG VT O Ld1 Cd Ld2 VT I Cg Ci Rb2 Lo Co vi MnNF vo PAD Lg MnG PAD Rb1 PAD Bonding Ls Inductor Fig. 7.6 Inductively degenerated common-source two-stage LNA An active load formed by M pNF1,2 and M pG1,2 transistors is used to provide a way to control voltage gain on each stage. Although, it is very common on reported LNAs to have RLC loads [30–39]. Note that a cascode stage could be used to increase the voltage gain compared with the single stage with inductively source degeneration. However, cascode stages limit the resonant frequency tuning in terms of voltage gain. Such a trade-off is illustrated in Fig. 7.7, where an inductively source degeneration (ISD) and a cascode with an inductively source degeneration (CISD) LNAs are compared respectively, considering a variation of gmn1 . Note that a lower tuning range is obtained by the CISD topology. For that reason, a simple input stage was considered in this design. 7.3.1 Input Impedance Assuming ideal inductors and all transistors in Fig. 7.6 operating in the saturation region, and neglecting the effect of Rb1,2 ,1 it can be shown that input impedance of the LNA is approximately given by: Cgi + CgsnNF + sCgi gmnNF Ls + s2CgsnNFCgi Lgs ZiIDCSA » (7.12) sCi (Cg + sCg gmnNF Ls + s2CgCgsnNF Lgs ) where CgsnNF and gmnNF are respectively the small-signal gate-source capacitance and transconductance of MnNF transistor and Cgi “ Cg + Ci ; Lgs “ Lg + Ls (7.13) 1 This approximation is only valid if Rb1,2 ≫ 50Ω, as it is the case in this design. 154 E.C. Becerra-Alvarez et al. 30 25 CISD LNA S21 (dB) 20 15 10 5 ISD LNA 0 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) Fig. 7.7 Dependency of the voltage gain in CISD and ISD LNAs due to gmn1 variation The real part of ZiIDCSA , given by (gmnNF Ls /CgsnNF ), must be set equal to the RF source resistance, RRF , in the band of interest—1.85–2.48 GHz in this design. In this prototype, as the LNA is fully integrated as a stand-alone circuit, a termination of 50 Ω is needed not only at the input terminal but also at the output one, as will be shown in the next section. The tuning mechanism of the LNA is achieved by varying the resonance frequencies of the passive input/output tuning network. This way, a variation in ZiIDCSA produces a change in S11 , because they are related by [40, 41]: ZiIDCSA − RRF S11 “ (7.14) ZiIDCSA + RRF As an illustration Fig. 7.8 depicts S11 parameter for the LNA operating in the GSM standard, comparing theoretical predictions given by (7.14) with electrical simulations that take into account layout-extracted parasitics as well as chip- package parasitics. Both theory and simulations match well within the signal band, where the condition S11 < −10 dB is satisfied. Main differences between theory and simulation are obtained outside the signal band, and are mainly caused by the effect of the circuit element parasitics—not considered in the theoretical analysis described above. Matching conditions can be obtained from the value of the LNA input impedance at the resonant frequency, where the imaginary part of Zi becomes zero and its real part is approximately given by: 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 155 5 Simulator 0 S11(dB) -5 -10 -15 Equation (7.12) -20 -25 1.6 1.8 2 2.2 2.4 2.6 2.8 Frequency (GHz) Fig. 7.8 S11 parameter on GSM standard CgsnNF gmnNF Ls Re|Zi | » 2 (7.15) Cg gmnNF Ls ω + (Cg + CgsnNF − CgCgsnNF Lgs ω 2 ) 2 2 2 2 where ω stands for the angular frequency, expressed in rad/s. Therefore, the input impedance of the LNA must be equal to the antenna output impedance in order to obtain the required coupling. This condition can be written as: CgsnNF gmnNF Ls RRF » 2 (7.16) Cg gmnNF Ls ω + (Cg + CgsnNF − CgCgsnNF Lgs ω 2 ) 2 2 2 2 On the other hand, making Im|Zi | “ 0, the resonant (angular) frequency can be calculated, giving: g b f f CgsnNF Lgs z2 − z1 − z21 − 2CgsnNF Lgs z1 z2 + CgsnNF 4 Ci2 L2gs e ωiIDCSA » 2 (7.17) 2CgCgsnNF Cgi L2gs where Cgi2 “ 2Cg + Ci ; z1 “ CgCgi g2mnNF L2s ; z2 “ 2CgCgi + CgsnNFCgi2 (7.18) Note that a variation of Cg allows us to properly set up the LNA operating bandwidth. This effect can be used for frequency tuning without needing any switches. As an illustration, Fig. 7.9a, represents the S11 variation with Cg for different operating frequencies. These curves can be used to optimize the LNA performance for a given set of specifications in a given frequency tuning range. Note from Fig. 7.9a that there is not a linear relation between S11 parameter and Cg . As a consequence, depending on the absolute values of the operating frequen- cies, a different tuning range will be required for the value of Cg . For instance, the 156 E.C. Becerra-Alvarez et al. Fig. 7.9 Resonant frequency a tunning for S11 using: (a) Cg varactor and (b) Lg inductor −5 1.5 −5 1.0 Cg (pF) −7 −7 0.5 −25 −15 −10 0 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) b 10 −8 −14 8 −6 Lg (nH) 6 −10 4 −18 −8 2 0 −6 −10 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) frequency band ranging from 2.4 to 2.6 GHz requires a variation range for Cg smaller than in the case of 1.6–1.8 GHz band. This behavior translates into a maximum frequency tuning range that will depend on the maximum variation allowed by the physical implementation of Cg —based on the use of varactors in this case. Inductor Lg can be combined with Cg varactor to set up the resonant frequency. This is illustrated in Fig. 7.9b for S11 , showing an inverse relation between the tuned frequency and Lg . This way, both the resonant frequency and the quality factor, Q, increases as Lg is reduced, at the price of increasing the sensitivity to circuit parasitics. 7.3.2 Voltage Gain The proposed LNA shown in Fig. 7.6 has two amplification stages. In addition to increasing the overall gain, the second stage is used to improve the isolation. Assuming that inductors are ideal, the voltage gain at each stage, denoted as Av1IDCSA and Av2IDCSA , can be approximated expressed as: 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 157 −Ci gmnNF (1 + gdspNF2 sLd1 ) Av1IDCSA » (7.19) sCgiCgsnG (1 + gmnNF sLs + s2CgsnNF Lgs ) Av2IDCSA » −gmnG RL (1 + gdspG2 sLd2 ) (7.20) where gdspNF2 is the small-signal drain-source conductance of M pNF2 transistor, CgsnG and gmnG are the small-signal gate-source capacitance and transconductance of MnG transistor, respectively, gdspG2 is the drain-source conductance of M pg2 transistor and RL is the load resistance connected at the output of the LNA. The total voltage gain of the LNA can be calculated from (7.19) and (7.20), giving: AvIDCSA “ Av1IDCSA Av2IDCSA (7.21) Ci gmnNF gmnG RL (1 + gdspNF2 sLd1 )(1 + gdspG2 sLd2 ) AvIDCSA » (7.22) sCgiCgsnG (1 + gmnNFsLs + s2CgsnNF Lgs ) Note that a resistive load, RL , has been considered to compute (7.22) because the measurement equipment requires such a load impedance. However, if a capacitive load, CL , is used, the voltage gain can be approximated written as: Ci gmnNF gmnG (1 + gdspNF2 sLd1 )(1 + gdspG2 sLd2 ) AvCLIDCSA » (7.23) s2CgiCgsnGCL (1 + gmnNF sLs + s2CgsnNF Lgs ) A performance metric typically used to characterize the voltage gain of LNAs is the S21 parameter, which can be calculated as [42]: c RRF |S21 | “ 2AvIDCSA (7.24) ZL As an illustration Fig. 7.10a represents S21 versus frequency, showing a good agreement between simulation results and theoretical predictions. 7.3.3 Output Impedance As the LNA is tested as a stand-alone circuit, a varactor-based tuning network is also used at the output of the LNA. To this purpose, an accumulation-MOS varactor— labelled Cd in Fig. 7.6—was used. Proceeding in a similar way as in previous sections and assuming that inductors Ld2 and Lo are ideal, the output impedance of the LNA is approximately given by: 1 1 + sLd2 gdspG2 + sCd ZoIDCSA » + sLo + (7.25) sCo sgdsnG gdspG2 Ld2 + z3 (1 + s2Cd Ld2 ) 158 E.C. Becerra-Alvarez et al. a 20 15 Simulator S21 (dB) 10 Equation (7.22) 5 0 1 1.5 2 2.5 3 Frequency (GHz) b 0 Equation (7.25) -10 S22 (dB) -20 Simulator -30 -40 1.6 1.8 2 2.2 2.4 2.6 2.8 Frequency (GHz) Fig. 7.10 Tunning S-parameters: (a) S21 for WLAN and (b) S22 in WCDMA where z3 “ gdsnG + gdspG2 (7.26) and gdsnG is the small-signal drain-source conductance of MnG . The output reflection parameter, S22 , can be calculated as [40, 41]: ZoIDCSA − ZL S22 “ (7.27) ZoIDCSA + ZL As an illustration, Fig. 7.10b depicts S22 , comparing theoretical predictions with electrical simulations. The main differences between both curves are caused by circuit element parasitics, although a similar qualitative behavior is obtained. Note that in this example, the condition S22 < −10 dB is satisfied in the band of interest. 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 159 A similar procedure to the one followed to establish the condition applied on input coupling network could be used for the output coupling network. In this case, coupling is achieved if the imaginary part of ZoIDCSA becomes zero when output network is operating at resonant frequency. Under these conditions, the real part of ZoIDCSA is approximately given by: 2 gdsnG g2dspG2 L2d2 ω 2 + z3 −1 + Cd Ld2 ω 2 Re|Zo | » (7.28) g2dsnG g2dspG2 L2d2 ω 2 + z23 (−1 + Cd Ld2 ω 2 )2 Assuming that there is a load resistance, RL , connected at the output of the LNA, the coupling condition can be written as: 2 gdsnG g2dspG2 L2d2 ω 2 + z3 −1 + Cd Ld2 ω 2 RL » 2 (7.29) g2dsnG g2dspG2 L2d2 ω 2 + z23 (−1 + Cd Ld2 ω 2 ) On the other hand, assuming that Im|ZoIDCSA | “ 0, the output resonant frequency can be calculated as: d 5.2Cd g2dsnG + 6Co gdspG2 ωoIDCSA » Ld2 gdspG2 (7.30) 3g2dsnG Lo Note that Lo can be combined with Cd to operate at a given frequency while keeping the coupling condition. As an illustration, Fig. 7.11a shows how S22 parameter is tuned by varying Cd . Similarly, Lo can be adjusted to obtain the required value of S22 , as illustrated in Fig. 7.11b. 7.3.4 Noise Factor Noise factor, F, is one of the most important performance metrics of LNAs. For the circuit under study, a noise analysis was carried out following the methodology described in [17], giving that the input referred equivalent noise sources of the LNA in Fig. 7.6 can be approximated by: −gmnNF ingnNF + sCg indnNF i2ni » (7.31) gmnNF gmnNF ingnNF + sCgi indnNF v2ni » (7.32) sCi gmnNF where indnNF and ingnNF are respectively the internal noise sources associated to the gate and channel of MnNF . 160 E.C. Becerra-Alvarez et al. Fig. 7.11 Setting S22 a parameter by using: (a) Cd 3.0 -2 varactor and (b) Lo inductor -10 2.5 6 2.0 0 Cd (pF) -6 1.5 -2 -2 1.0 2 -10 -6 0.5 -10 0 0.0 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) b 10 0 -8 8 -10 0 -4 6 -2 Lo (nH) 4 4 -2 -6 2 -4 -42 4 0 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) Noise factor, F, can be easily obtained by replacing (7.31) and (7.32) in the following expression [43]: v2ni + R2RF i2ni F “ 1+ (7.33) v2nRF After some approximations, the noise factor for the proposed LNA shown in Fig. 7.6 can be approximated given by: 2γ Cgi Cg2 RRF γω 2 gmnNF α FIDCSA » 1 + + + 2 Ci gmnNF RRF α 2 gmnNF α Ci RRF ωT2 ? gmnNF RRF αω 2 2 γω + − (7.34) ωT2 ωT 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 161 where gmnNF gmnNF α“ ; ωT “ (7.35) gdsnNF CgsnNF As expected, the main contribution to the noise figure is due to the first stage, because the noise sources of the second stage are attenuated by the gain of the first stage within the signal bandwidth. Another interesting design issue is that the varactor capacitance, Cg , affects the noise performance—apart from its effect on the resonant frequency discussed in previous sections. 7.3.5 Design Procedure The expressions described above have been used in a systematic design procedure, consisting of the following steps: • Transistors MnNF and M pNF1,2 are sized in order to obtain the minimum value required for NF in the signal bandwidth, see (7.34), while trying to achieve the maximum voltage gain possible with the least power dissipation, see (7.22). An important consideration is the fact that voltage gain is separated in two factors, because the proposed LNA topology has two amplification stages. This strategy allows to separately control the voltage gain and noise performance for a different set of specifications as will be shown later on. Thus, it contributes to achieve NF requirement with more freedom from voltage gain. • Transistor MnG and M pG1,2 are sized in order to achieve the maximum volt- age gain through the proper adjustment of Ld1 and Ld2 inductors respec- tively, see (7.22). • Passive elements of the input matching network (Ci , Cg , Lg and Ls ) are derived in order to get the required impedance at resonant frequency, by using (7.12). This is a critical step, because LNA tuning depends on it. Lg inductor fixes frequency where operating mode will be adjusted by Cg varactor. Ls inductor allows to achieve real part of ZiIDCSA at resonant frequency, and it must be equal to antenna impedance—see (7.16). • The values of Cd , Co and Lo are also calculated to get the output impedance matched at each required standard, using (7.25). However, Lo inductor is also used to establish frequency where it will be tunned by using Cd varactor, it is shown in Fig. 7.11b. • Finally, technology parasitics are considered in an interactive electrical simula- tion process to re-fine the sizing and biasing obtained in the previous steps. The outcome of the design procedure described above is the sizing and biasing of the LNA, summarized in Table 7.2, where C is capacitance, L and W are length and width for transistors respectively, I is the inductance and R is the resistance. Cda,b and Cga,b are varactor arrays which allows to implement varactors with better performance. 162 E.C. Becerra-Alvarez et al. Table 7.2 Programmable Element Sizing load LNA sizing Cda,b C “ 4.051 pF n f v “ 19 L “ 1 µm wv “ 18 µm Cga,b C “ 0.711 pF n f v “ 6 L “ 1 µm wv “ 10 µm Ci C “ 1.5 pF Co C “ 0.64 pF Ld1 dl “ 140 µm I “ 12.08 nH ntl “ 6.5 wl “ 10 µm Ld2 dl “ 99.2 µm I “ 4.733 nH ntl “ 4.75 wl “ 10 µm Lg dl “ 140 µm I “ 5.87 nH ntl “ 4.5 wl “ 10 µm Lo dl “ 100 µm I “ 7.049 nH ntl “ 5.75 wl “ 10 µm Ls I “ 0.7 nH MnNF L “ 0.3 µm W “ 220 µm MnG L “ 0.3 µm W “ 124 µm M pG1 L “ 0.1 µm W “ 1 µm M pG2 L “ 0.1 µm W “ 124 µm M pNF1 L “ 0.1 µm W “ 1 µm M pNF2 L “ 0.1 µm W “ 124 µm Rb1 R “ 6 kΩ Rb2 R “ 4 kΩ Ld1 Ld Co Cg vo Cd RF PAD Lo vi Lg Active RF PAD area Ci Fig. 7.12 LNA layout implemented in 90-nm CMOS technology 7.3.6 Layout, Packaging and Simulation Results The LNA has been designed and implemented in a 90-nm CMOS technology with a single 1-V supply voltage. Figure 7.12 shows the layout of the chip highlighting their main parts. Integrated inductors have a patterned ground shield and octagonal shape—see Fig. 7.13a. Input/output capacitors are implemented by MOM structures, which are based on the combination of stacked and finger 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 163 a b Fig. 7.13 Cross-section of the physical structure for: (a) Inductors and (b) Varactors RNF RG VT O Right PIN L2 Ccr L1 Rs2 vo VDD PAD vi Rp1 Rs1 Ccc Rp2 Common node VDD PIN C1 Ccl C2 vi vo Left PIN VT I Fig. 7.14 Conceptual schematic of the PCB including the QFN package metal-metal capacitors. MOS varactors shown in Fig. 7.13b are formed by source- drain connection in a MOS transistor. All PADs are Electrostatic Discharged (ESD) protected. The die area, including PADs, is 1.8 mm2 , with the core occupying 1.0 mm2 . As usual, a significant portion of this area corresponds to integrated inductors. However, in this circuit, and contrary to most reported multi-standard LNAs, the number of inductors is not increased as compared to the mono-standard case, with the subsequent area saving. The circuit has been extensively verified using CADENCE SpectreRF. c Technology parasitics and package effects were considered in the simulations. For that purpose, the circuit in Fig. 7.14 was used. This circuit includes the package and the external components to be included in the PCB. A 4 mm× 4 mm 12-pin QFN plastic package has been used. This package has been modeled using CADENCE PKG c tool in order to take into account their associated parasitics during the design process. Figure 7.15a represents NF vs input frequency for all the standards under study. The overall minimum value of NF is 1.9 dB, obtained at 2.4 GHz, which corresponds to the WLAN operation mode. Figure 7.15b–d show respectively the 164 E.C. Becerra-Alvarez et al. a b 5.5 25 GSM WCDMA 5 20 4.5 Bluetooth WCDMA 15 S21 (dB) NF (dB) 4 3.5 10 GSM 3 Bluetooth WLAN 5 2.5 2 0 WLAN 1.5 -5 1 1.5 2 2.5 3 1 1.5 2 2.5 3 c Frequency (GHz) d Frequency (GHz) 5 0 0 -5 WCDMA GSM -10 -5 -15 S11 (dB) S22 (dB) WCDMA -10 -20 GSM WLAN -15 -25 -20 -30 -35 Bluetooth -25 -40 Bluetooth WLAN -30 -45 1 1.5 2 2.5 3 1 1.5 2 2.5 3 Frequency (GHz) Frequency (GHz) Fig. 7.15 Simulation of NF and S-parameters: (a) NF (b) S21 (c) S11 and (d) S22 Table 7.3 Simulated LNA performance Standard IIP3 (dBm) NF (dB) S21 (dB) S11 (dB) S22 (dB) PDC (mW) GSM 17.6 2.2 20.7 −9.0 −20.8 21.7 WCDMA 17.5 2.0 20.0 −8.6 −14.7 21.7 Bluetooth 10.9 2.7 13.3 −16.5 −21.8 17.4 WLAN b/g 19.0 1.9 17.2 −16.4 −18.2 21.7 input and output reflection coefficient (S11 and S22 ) and forward-gain (S21 ). The minimum value of S21 within the band of interest is above 13 dB—corresponding to Bluetooth—whereas S11 and S22 are below −8.6 dB for all standards. On the other hand, the linearity of the LNA has been also taken into ac- count in the design process. The minimum and maximum values achieved of the 3rd-order intermodulation intercept point, IIP3, are 10.9 dBm and 19 dBm, respec- tively for Bluetooth and WLAN. In addition to the nominal simulations describe above, Monte Carlo (100-run) and technology corners analysis were carried out. Finally, Table 7.3 sums up the simulated performance of the LNA by showing the worst-case values of the different figures for each standard. Power consumption has a variation range of 4 mW, where the minimum power dissipation is for Bluetooth standard, but it has the minimum forward-gain and noise contribution is increased— worst case NF. 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 165 Fig. 7.16 (a) Chip microphotograph and (b) Test PCB 7.3.7 Experimental Results Figure 7.16a shows a microphotograph of the chip highlighting their main parts, namely integrated inductors, capacitors, PMOS varactors and CMOS active area. The chip has been tested using the PCB shown in Fig. 7.16b, that includes the necessary filtering for biasing and power supplies as well as off-chip resistors and connectors for the instruments. Figure 7.17a shows the measured NF vs input frequency, corresponding to different values of tuned frequencies, demonstrating the reconfigurability capability of the proposed LNA with a programmable NF within the band of interest. Reconfiguration of S21 parameter is illustrated in Fig. 7.17b, where value of S21 varies from 19.8 dB at 2.23 GHz to 23.4 dB at 1.9 GHz. This feature is a direct con- sequence of using MOS varactors in the resonance tuning networks, which provides approximately up to 700-MHz tuning range. Indeed, this is a peculiarity of the presented chip as compared to previously reported multi-standard LNAs—mostly based on using switchable LC tanks to select the resonant frequency in a discrete way and using varactors to fine tuning the selected band. The difference in the presented design is that it achieves a coarse continuous frequency tuning capability, just using varactors. This characteristic constitutes a first step towards achieving a tuning range in the order of GHz—required in future software defined radios. 7.4 State of Art on Reconfigurable LNAs To conclude this chapter, Table 7.4 sums up the state of the art on reconfigurable LNAs reported so far. The performance of the chips in this table is compared by using the following Figures of Merit (FOM) [39]: S21 S21 IIP3 fc FOM1 “ ; FOM2 “ (7.36) |NF − 1|PDC |NF − 1|PDC where fc is the resonant frequency of the LNA. 166 E.C. Becerra-Alvarez et al. Fig. 7.17 Illustrating the a 6 LNA reconfiguration: (a) NF 2.5dB and (b) S21 5 Operating frequency NF (dB) 4 3 0.6 1 1.4 1.8 2.2 2.6 Frequency (GHz) b 24 22 20 S 21 (dB) 18 16 14 1.6 1.8 2 2.2 2.4 Frequency (GHz) The LNA circuit presented in this chapter is included in the table for the sake of completeness. Note that the experimental results achieved by the proposed LNA compares favourably to previous LNAs while covering a larger number of standards. 7.5 Conclusions Main circuit techniques for the design of reconfigurable LNAs intended for multi- standard wireless telecom systems have been overviewed. The use of varactors to continuously tune the operation frequency has been analyzed. This technique has been applied to the design and implementation of a two-stage LNA circuit which uses an inductively degenerated common-source configuration at the input stage. The use of MOS-varactor based tuning networks allows the circuit to adapt its performance to the specifications of different wireless standards in a continuously way, covering not only the target specifications at a given set of 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 167 Table 7.4 Comparison with the state-of-the-art reconfigurable CMOS LNAs IIP3 NF PDC S21 Ref. Standard (dBm) (dB) (mW) (dB) FOM1 FOM2 [6] GSM 900 −12.8 4.6 32.4 18.0 0.1 0.0 WLAN b/g −15.3 4.43 24.0 0.3 0.0 WLAN a −14.7 4.42 23.0 0.2 0.0 [44] 2.4 GHz–5.4 GHz −2.5 3.1 4.7 22.2 2.6 5.7 [45] 2.9 GHz–3.5 GHz −10.0 3.6 18.0 9.0 0.1 0.0 [5] WLAN b/g 0.0 2.3 4.0 14.0 1.8 4.3 WLAN a 5.6 4.5 15.5 0.8 16.0 [18] CDMA −5.8 1.8 7.5 8.4 0.7 0.3 WCDMA −5.3 2.0 11.0 0.8 0.5 [12] GSM −7.5 5.2 24.0 28.5 0.5 0.2 WCDMA 0.0 5.6 29.5 0.5 0.9 WLAN b/g −4.8 5.8 23.4 0.2 0.2 [46] WLAN b/g 4.0 2.8 16.0 14.0 0.3 2.1 WLAN a −3.0 3.9 19.0 16.0 0.2 0.6 [47] WLAN b/g −21.4 3.1 1.1 10.0 2.8 0.0 WLAN a −6.7 3.8 1.0 10.1 2.3 2.6 [10] ISM −6.6 2.6 3.0 22.8 5.6 3.0 UNII −1.0 6.2 9.1 22.2 0.4 1.9 This work 1.78 GHz −9.74 3.6 19.74 0.3 0.1 1.84 GHz −10.24 3.7 19.6 0.3 0.1 1.92 GHz (GSM) −10.11 3.6 23.0 22.82 0.3 0.1 1.98 GHz −10.22 3.7 22.31 0.5 0.1 2.04 GHz (WCDMA) −10.5 3.4 20.49 0.4 0.1 2.1 GHz −10.5 3.5 20.53 0.4 0.1 operation frequencies, as well as other operation modes in between. Experimental measurements of the prototype demonstrates a competitive behavior with the state of the art, showing that the proposed techniques are very suited for the implementation of continuously-tuned LNAs in future Software-Defined-Radio mobile systems. References 1. Brandolini M et al (2005) Toward multistandard mobile terminals - Fully integrated receivers requirements and architectures. IEEE Trans Microw Theor Tech 53:1026–1038 2. Mak PI, Martins RP (2007) Transceiver architecture selection: review, state-of-the-art survey and case study. IEEE Circ Syst Mag, Second Quarter, pp. 6–25. (ISSN: 1531-636X) 3. Vidojkovic V et al (2004) Fully-integrated DECT/Bluetooth multi-band LNA in 0.18µm CMOS. Proceedings of IEEE international symposium on circuits and systems, pp 565–568 4. Koolivand Y et al (2005) A new technique for design CMOS LNA for multi-standard receivers. Proc IEEE Int Symp Circ Syst 4:3231–3234 5. Hashemi H et al (2002) Concurrent multiband low-noise amplifiers-theory, design, and applications. IEEE Trans Microw Theor Tech 50:288–301 168 E.C. Becerra-Alvarez et al. 6. Ang C-W et al (2007) A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless Receivers. Proceedings of IEEE international symposium on circuits and systems, pp 2802–2805 7. Hsieh H-H et al (2008) Gain-enhancement techniques for CMOS folded cascode LNAs at low-voltage operations. IEEE Trans Microw Theor Tech 56(8):1807–1816 8. Ahola R (2004) A single-chip CMOS transceiver for IEEE 802.11a/b/g wireless LANs. Proc IEEE J Solid State Circ, pp 2250–2258 9. Li X, Ismail M (2002) Multi-standard CMOS wireless receivers: analysis and design. Kluwer Academic Publishers, New York 10. Li Z et al (2004) A dual-band CMOS front-end with two gain modes for wireless LAN applications. IEEE J Solid State Circ 39:2069–2073 11. Wang C-S et al (2005) A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications. Proceedings of IEEE international symposium on circuits and systems (ISCAS), pp 3974–3977 12. Liscidini A et al (2006) A 0.13µm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. IEEE J Solid State Circ 41:981–989 13. Wu C, Lu L (2006) A 2.9–3.5-GHz tunable low-noise amplifier. Proceedings of the 2006 IEEE silicon monolithic integrated circuits in RF systems (SiRF), pp 206–209 14. Zhan J-H et al (2006) A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications. Proceedings of IEEE solid-state circuits conference, pp 721–730 15. Martins M et al (2007) Techniques for dual-band LNA design using cascode switching and inductor magnetic coupling. Proceedings of IEEE international symposium on circuits and systems (ISCAS), pp 1449–1452 16. Vidojkovic M et al (2007) A broadband, inductorless LNA for multi-standard applications. Proceedings of European conference on circuit theory and design, pp 260–263 17. Shaeffer D et al (1997) A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J Solid State Circ 32:745–759 18. Song H et al (2008) A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applica- tions. IEEE Microw Wireless Compon Lett 18:212–214 19. Tividis Y (2003) Operation and modelling of the MOS transistor, 2nd edn. Oxford Press, New York 20. Lee TH (2004) The design of CMOS radio-frequency integrated circuits, 2nd edn. Cambrige University Press, Cambridge 21. Abou-Allam E et al (2001) Low-voltage 1.9-GHz front-end receiver in 0.5-µm CMOS technology. IEEE J Solid State Circ 36:1434–1443 22. Hioe W et al (2004) 0.18µm CMOS Bluetooth analog receiver with -88-dBm sensitivity. IEEE J Solid State Circ 39:374–377 23. Jarvinen J et al (2004) 2.4-GHz receiver for sensor applications. Proceedings of the European solid-state circuits conference, pp 91–94 24. Komurasaki H et al (2003) A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications. IEEE J Solid State Circ 38:817–825 25. Rogin J et al (2003) A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13µm CMOS. IEEE J Solid State Circ 38:2239–2248 26. Sjoland H et al (2003) A merged CMOS LNA and mixer for a WCDMA receiver. IEEE J Solid State Circ 38:1045–1050 27. Sivonen P et al (2006) A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13µm CMOS. IEEE J Solid State Circ 41:384–394 28. Tiebout M et al (2002) LNA design for a fully integrated CMOS single chip UMTS transceiver. Proceedings of the European solid-state circuits conference, pp 835–838 29. Yang Y-C et al (2006) Reconfigurable SiGe low-noise amplifiers with variable miller capaci- tance. IEEE Trans Circ Syst 53:2567–2577 30. Andreani P et al (2001) Noise optimization of an inductively degenerated CMOS low noise amplifier. IEEE Trans Circ Syst II: Analog and Digit Signal Process 48:835–841 7 Flexible Nanometer CMOS LNAs for Software-Defined-Radio 169 31. Hsiao C-L et al (2003) A 1V fully differential CMOS LNA for 2.4GHZ application. Proceedings of the 2003 international symposium on circuits and systems (ISCAS), vol 1, pp 245–248 32. Cha C-Y et al (2002) A 5.2GHz LNA in 0.35µm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. Proceedings of the European solid-state circuits conference, pp 339–342 33. Cha C-Y et al (2003) A 5.2-GHz LNA in 0.35µm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. IEEE J Solid State Circ 38:669–672 34. Dupuis O et al (2005) 24GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors. Proceedings of the European solid-state circuits conference, pp 89–92 35. Fujimoto R et al (2002) A 7-GHz 1.8-dB NF CMOS low-noise amplifier. IEEE J Solid State Circ 37:852–856 36. Goo J-S et al (2002) A noise optimization technique for integrated low-noise amplifiers. IEEE J Solid State Circ 37:994–1002 37. Han K et al (2005) Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier. IEEE J Solid State Circ 40:726–735 38. Linten D et al (2004) A 5 GHz fully integrated ESD-protected low-noise amplifier in 90nm RF CMOS. Proceedings of the European solid-state circuits conference, pp 291–294 39. Linten D et al (2005) A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. IEEE J Solid State Circ 40:1434–1442 40. White JF (2004) High frequency techniques - An introduction to RF and microwave engineer- ing. Wiley, Hoboken 41. Everard J (2001) Fundamentals of RF circuit design with low noise oscillators. Wiley, Chichester 42. Leenaerts D et al (2001) Circuit design for RF transceivers. Kluwer Academic Publishers, Boston 43. Stenman A-K (2001) Some design aspects on RF CMOS LNAs and mixers. PhD thesis, Lund University 44. Fu C-T et al (2007) A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistan- dard wireless receiver. Proceedings of IEEE radio frequency integrated circuits symposium, pp 65–68 45. Wu C-R et al (2006) A 2.9–3.5-GHz tunable low-noise amplifier. Topical meeting on silicon monolithic integrated circuits in RF systems, pp 206–209 46. Kao S-W et al (2005) A low-power dual-band WLAN CMOS receiver. Proceedings of Asian solid-state circuits conference, pp 397–400 47. Tzeng F et al (2008) A multiband inductor-reuse CMOS low-noise amplifier. IEEE Trans Circ Syst II: Express Briefs 55:209–213 Chapter 8 Clocked Nanometer CMOS Comparators Bernhard Goll and Horst Zimmermann 8.1 Introduction A circuit block, which is mostly used in the link between the analog and the digital domain, e.g. in an analog-digital converter (ADC), is the clocked, regenerative comparator. This type of comparator is implemented mostly in ADCs with a fast conversion rate, e.g. in flash-ADCs [1–4] because of its capability of a fast decision. A comparator is a circuit, which typically compares two analog input voltages (VA p , VAn ), currents or charges and delivers a logical level at the output, which indicates, what of the compared values was higher (see Fig. 8.1). In other words the comparator gives as a result a logical value which indicates the polarity of the difference of the sizes of the input values. In common the circuit of a clocked, regenerative comparator is based on a cross-coupled inverter (latch) [5, 6] to force a fast decision with the help of positive feedback (see Fig. 8.2). With reset switches, which are not shown in Fig. 8.2, the latch is forced into a metastable point (see Fig. 8.2b), where both voltages u1 and u2 of the output nodes are equal. Therefore the regenerative comparator is clocked to reset the comparator during a part of the clock cycle, which means that for a following comparison phase an initial condition of a metastable point is forced. If comparison starts an initial voltage difference Δ U0 is introduced to the latch after releasing the reset switches. Depending on the polarity of Δ U0 , u2 is pulled to the stable point VDD (e.g. the logical High) and u1 is pulled to VSS (e.g. the logical Low) or vice versa in case of inverse polarity (see Fig. 8.2b,d). Figure 8.2c shows the small-signal equivalent circuit of a latch. Index 1 marks the small-signal parameters (transconductance gm , output resistance r) of inverter 1 (transistors N1 and P1) and index 2 is referred to inverter 2 (N2, P2). Voltage u1 is the output voltage of inverter 1 (loaded with the capacitance C1 ) and the input voltage of inverter 2. On the other hand u2 is the output B. Goll () • H. Zimmermann Vienna University of Technology, EMCE, Gußhausstraße 25/354 1040 Vienna, Austria e-mail: [email protected]; [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 171 DOI 10.1007/978-1-4614-1383-7 8, © Springer Science+Business Media New York 2013 172 B. Goll and H. Zimmermann Fig. 8.1 Ideal comparator OUT OUT OUT VAp VAn VAp-VAn VAp-VAn OUT a VDD b u1 Stable points Inverter N2, P2 VDD P1 P2 Metastable point VDD-|Vtp| u1 u1 u2 u2 VM N1 N2 Vtn ΔU0 Inverter N1, P1 VSS Vtn VM VDD u2 VDD-|Vtp| c u1 u2 d VDD u2 r1 gm1u2 gm2u1 r2 C1 C2 ΔU0 u1 VSS t VSS Fig. 8.2 The static latch: cross-coupled inverters (a), the characteristic (b), small-signal equivalent circuit (c), voltage-time dependence (d) voltage of inverter 2 (loaded with capacitance C2 ) and the input voltage of inverter 1. With the help of this small-signal representation a differential equation for the difference output-voltage Δ u(t) “ u2 − u1 with the initial condition Δ u(t “ 0) “ U0 can be stated (see (8.1)), where the solution is shown in (8.2) [5]. d 1 1 Δ u(t) “ Δ u(t) gm − (8.1) dt C r gm − 1r Δ Uend C Δ u(t) “ Δ U0 e C t → td “ ln , gm r > 1 (8.2) gm − 1r Δ U0 8 Clocked Nanometer CMOS Comparators 173 A delay time td can be also stated in (8.2) as the time duration till a distinct output voltage difference Δ Uend has been reached. It can be seen, that the delay time td lasts longer, if C is larger and gm , r and Δ U0 are smaller. 8.2 Characterization of Comparators There are several characteristic values to describe a clocked regenerative compara- tor, which are treated in this chapter. The principle influence of an offset and a hysteresis to a clocked comparator, where additionally the decision is affected by noise, is depicted in Fig. 8.3. At the input nodes INP and INN the voltages to be compared are applied. In Fig. 8.3 at INN a reference voltage and at INP a triangle signal slowly varying compared to the clock period are applied. The influence of noise can be seen as an uncertainty in the decision near the crossover points of INP and INN, where the noise causes the comparator to perform random decisions [7]. The higher the input voltage difference INP − INN, the lower is the chance for a wrong decision. In most cases the noise is assumed to be a stationary random stochastic process, where the probability density function (pdf) of the amplitude of the noise is assumed to be mean free and Gaussian. There are different noise sources, which can be combined to an overall input referred noise source. • Noise of the sources of the signals: The noise of the sources of the signals, which are applied to the input of the comparator disturb the decision. This might be uncertainty in amplitude or in time (jitter). Furthermore noise via the supply- voltage and ground-lines, which occur mostly due to switching of neighboring circuit components, may also cause a wrong decision of the comparator. CLK CLK t INP OUT INN OUT INN INP t OUT-OUT OUT-OUT Influence of noise Vhigh Vhigh t VOS Vlow OUT-OUT Influence of noise and an offset VOS Vhigh INP-INN t Vlow VOS VOS Vlow Vhyst OUT-OUT Influence of noise and a hysteresis V high (VOS =0V) t Vlow Vhyst /2 Vhyst /2 Fig. 8.3 Offset and hysteresis of a comparator, which is affected by noise 174 B. Goll and H. Zimmermann • Noise caused by circuit elements: In principle there are three sources of noise in CMOS devices [7]. Shot noise is the superimposed random variation of a current caused by fluctuation of charge carriers (electrons or holes) in pn- junctions. The mean square i2sn of this variation is given by i2sn “ 2eI Δ f , where e “ 1.602 × 10−19C is the elementary charge, I is the average current and Δ f is the bandwidth. Thermal noise is dominating in MOSFETS and exists due to random thermal motion of electrons in a real resistor at temperature ϑ . The mean square of the fluctuating voltage vtn 2 and of the equivalent current i2 is given by tn 2 “ i2 R2 “ 4kϑ RΔ f . For a MOS transistor in saturation the approximation vtn tn R « 2g3m can be used. Flicker (1/f) noise appears because of extra electron states at the boundary between Si and SiO2 , which trap and release electrons in a relatively slow time. Therefore most of the noise energy is located at lower frequency. An approximation of the mean square of the gate referred noise voltage of a MOS transistor is v2f n “ CoxKW L Δf f , where K depends on the temperature and the fabrication process, Cox is the gate capacitance per area and W L is the gate area. • Kickback noise: Kickback noise [8] is caused by the comparator itself, when at the output nodes a fast transition due to positive feedback in the decision phase or due to pulling the output nodes to a defined voltage level in the reset phase occurs, which is coupled back via parasitic capacitances to the input nodes. Another source of disturbances coupled back is caused by the fast ramps of the clock. In most cases this noise can be neglected, because it results mostly in a common-mode disturbance at the inputs if also equal signal-source impedances are considered at each input. Also at the time, when the output nodes regenerate or reset, the output nodes cause a considerable voltage at the input nodes, the comparator has already done most of the decision and is therefore more immune against noise, if also a small enough source resistance is considered. The real problem of kickback noise occurs, if e.g. more comparators are placed in parallel in e.g. a flash ADC, where the reference and input voltages are affected by several comparators or e.g. the comparators decide at different times due to clock delays. • Static noise: Static noise [9] is a DC disturbance, e.g. a disturbance of the working point, that is present in logic gates. This noise can be either series- voltage noise, parallel-current noise or voltage noise at the ground or power supply line. These noise sources might also appear in combination. In static random access memory (SRAM) cells, which consist in principal of static latched circuits to store a logical value, the static noise margin (SNM) is the minimal magnitude Δ Vser , which has to be applied both at u1 and in opposite sign at u2 to change the logic state. Also for a comparator, which has already decided, it may be considered, that static noise may also affect the decision. But due to the fact, that a decision of the comparator in common only lasts for a half clock cycle and the clock period is small in the case of a fast comparator, the influence of DC disturbances can be neglected in most cases. A calculation of SNM can be found in [10]. The influence of device fluctuations of the process to SNM was analyzed in [11]. 8 Clocked Nanometer CMOS Comparators 175 pdf P[Vref +ΔV0 ]·pn(ρ- ΔV0 ) P[Vref-ΔV0]·pn( ρ+ΔV0) ρ [V] ΔV0 ΔV0 Probability P[E] that Vref a false decision occurs Synchron data ΔV0 Vref CLK VSS Noise N(t) t ΔV0 CLK VDD Vref ± ΔV0 OUT Vref OUT VSS Comparator t Fig. 8.4 Occurrence of bit errors due to the influence of noise [12] The influence of noise to a decision of a clocked, regenerative comparator and hence the sensitivity of this comparator can be measured with the help of BER (bit- error-ratio) measurements. Figure 8.4 shows the principle model for calculating the BER. For calculation of the BER the whole input-referred combined noise N(t) of the comparator is assumed to be a stationary stochastic process [12], where the probability density function (pdf) pn0 (ζ ) is a Gaussian distribution (mean free µn , standard deviation σn ) doesn’t change at different time-points. The data stream is modelled by bits with logical voltage levels Vre f ± Δ V0 (high and low), where Vre f is the decision threshold. If the probability of appearance of a logical high is equal to that of a logical low (P[Vre f + Δ V0 ] “ P[Vre f − Δ V0 ] “ 0.5), then the probability P[E] that a bit error occurs can be calculated as shown in (8.3). α2 Q(ζ ) “ ?12π ζ∞ e− 2 d α " P[E] “ 0.5Q ΔσVN0 + 0.5 1 − Q −σΔNV0 “ Q ΔσVN0 (8.3) This BER can be measured with BER analyzer stations, where the data stream at the output of a comparator is compared with a reference data stream at the input (a pseudo-random bit-sequence) and where occurring bit errors are counted. If the noise is considered to be removed in a comparator, a metastability error might occur if a too low input-voltage difference is applied. Such an error occurs, because the amplification of a comparator is dependent on the decision time as illustrated in (8.2). So at a higher clock frequency a lower decision time is available 176 B. Goll and H. Zimmermann and a higher input voltage difference is necessary to reach the final output voltage difference. For a distinct small input-voltage difference range the comparator cannot decide, the comparator stays during the available time for decision near the metastability point (see Fig. 8.2 and a metastability error occurs. With noise, the outputs of a clocked comparator would deliver a random decision per clock cycle if the condition of metastability is given (BER→0.5). The offset VOS of a comparator is defined as the input voltage difference, which has to be applied to obtain the crossing point between logic level low and high. In Fig. 8.3 it can be seen, that the switching point of the comparator is shifted away from the cross-point of INP and INN by the offset VOS . In Fig. 8.3 the clock period of the comparator is small in comparison to the period of the triangle. The offset is caused by the following reasons: • The mismatch of different electronic parts, e.g. resistors, capacitances [13] and transistors in the circuit results as a consequence of a deviation from an ideal symmetrical circuit structure. The mismatch between two transistors [14, 15], which is for MOS transistors mainly the mismatch of their threshold voltages Vt and their transconductance parameter β , can be described with (8.4). These laws for the standard deviations for the transconductance parameters and threshold voltages are based on a Gaussian probability distribution. A σΔ β AΔ β σ (Δ Vt ) “ ? Δ Vt “? (8.4) W ·L β W ·L The parameters AΔ Vt and AΔ β are proportionality factors being characteristic for the technology used. W is the width and L is the length of the gate of the MOS transistor. The influence of process tolerances causes in principle random offset, where the mean value is zero. • Gradients of e.g. temperature or stress, which are introduced by neighboring circuit blocks have an influence to the symmetric functionality of the comparator and cause typically systematic offsets (the mean value is not zero). The offset caused by gradients can be minimized with an intelligent placement of compo- nents in the layout. • Systematic offsets are also introduced by asymmetry due to the used circuit structure. • The offset also may change in some cases between different clock frequencies (dynamic effects), e.g. if a mismatch in the reset switches or on coupling capacitors are present. When a comparator has a hysteresis [7], the comparison threshold for input signals is different in the case that the output changes from low to high and in the case of a change from high to low. The distance between these comparison thresholds is characterized in Fig. 8.3 by the hysteresis voltage Vhyst . In case of an hysteresis, the comparator is more immune against noise, because noise has to overcome the voltage Vhyst to flip back the decision of the comparator. A typical source of creating a hysteresis in a clocked regenerative comparator is, if the 8 Clocked Nanometer CMOS Comparators 177 reset switches are dimensioned too small. So at the end of the reset phase a considerable voltage difference exists still between the output nodes, which has to be overcome by the input voltage in the following comparison phase and a hysteresis is established. The delay time of a clocked regenerative comparator is the minimum time duration from beginning of the comparison phase (reset is released when the appropriate clock edge reaches typically 50% of VDD ) till a valid logical voltage level is available at the output. Another definition is the minimum time duration from beginning of the comparison phase (reset is released when the appropriate clock edge reaches typically 50% of VDD ) till one output node reaches the half supply voltage VDD /2. A further important parameter to characterize a clocked regenerative comparator is the power consumption. Typically it consists of a static and a dynamic part. The latter of depends on the clock frequency and the capacitances, which have to be charged and discharged. 8.3 CMOS Technology The cross section of a typical CMOS process is shown in Fig. 8.5. It is a twin well process on a non-epi p-substrate, where for isolation a shallow trench isolation (STI) is used. The p+ diffusion area of an n-MOS transistor is electrically connected polymide nitride LB VL ML VQ MQ V4 M4 V3 M3 V2 M2 V1 M1 salicide PC CA PC STI + n+ p p+ on non-epi p-substrate n-well Fig. 8.5 Cross section of a typical deep-sub-micron (DSM) CMOS process 178 B. Goll and H. Zimmermann to the p-substrate. More advanced technologies implement a triple well process, where the p-well for an n-MOS transistor is placed inside a deep n-well, which electrically isolates the n-MOS transistor. In opposite to that, the p-MOS transistors are placed in a n-well, which separates this transistor from the p-substrate. To lower the resistance mostly a CoSi2 salicided (self-aligned silicided) layer for n+ and p+ polysilicon and diffusion areas is added. A so called stud contact (tungsten plug) to connect the poly-silicon gate or diffusion region of transistors to metal level M1 is marked with CA and the wiring level contacts are named V1, V2, V3, VQ and VL. For the metal layers, copper is used. Layers M1 to M4 are thin and tighter-pitch copper levels and MQ and ML are thick copper levels with a relaxed pitch. The last metal level LB is also used for pads made of AlCu [16]. In ultra-deep-sub-micron (UDSM) CMOS technology, analog circuit design suffers from the low supply voltages, which are necessary to avoid too high electric fields in MOS transistors and to optimize power consumption of digital circuits. In common, having a small voltage headroom left, decreases the voltage gain at a given power consumption [20]. On the other hand the clock frequency of digital logic tends to become better in CMOS technologies due to lower parasitic capacitances. Also the bandwidth of analog circuits increases with shrinking transistors. However a problem is the increasing gate tunnel current, when the gate area is increased (optimal gm /ID ratio supposed) for e.g. reducing the input-referred offset. Lowering the influence of Vt and β mismatch by increasing gate area is limited by gate-leakage mismatch. It is now a challenge to develop new circuit structures, which either avoid a stack of too many transistors between the supply rails so that the technology- given better AC performance does not degrade, but otherwise keep the advantages of standard circuits, e.g. robustness against influence of noise and mismatch or lower power consumption. 8.4 Comparator Circuits In the literature, many types of comparator circuits can be found. In Fig. 8.6 two comparator circuits are shown, which can be often found in integrated circuits. Figure 8.6a shows a comparator, where the input transistor pair N2, N3 is placed below the latch N0, P0, N1, P1 [17, 18]. The operation of the comparator is divided into two clock phases. When CLK is at voltage level VSS , transistor N6 is cut off and transistors P2 and P3 pull both output nodes to supply-voltage level VComp to reset the comparator. If CLK changes to level VComp the initial condition is, that both output nodes are at level VComp , transistors P0, P1, P2 and P3 are off and transistors N0 and N1 are on. Transistors N2 and N3 a start to discharge both output nodes with a current difference Δ In6 “ gmn2 Δ Uin “ 2βn2In6 , where Δ Uin “ INP − INN is the constant assumed input voltage difference, gmn2 “ gmn3 are the equally assumed transconductances of transistors N2 and N3, βn2 “ βn3 are their transconductance parameters and In6 is the tail current through switch transistor N6. If one output 8 Clocked Nanometer CMOS Comparators 179 VComp a b CLK P4 P0 P1 VComp OUT OUT P0 P1 N4 N0 N1 N5 P2 P3 OUT VSS OUT DI VComp DI N0 N1 N2 N3 CINN CINP P2 P3 CLK N6 N2 N3 CINN CINP VSS N6 CLK VSS Fig. 8.6 Two comparators, which are often described in literature: latch-type voltage sense amplifier [17, 18] (a), double-tail latch-type voltage sense amplifier [19] (b) node reaches the voltage VComp − |VtP0 | after a time duration of t0 « (2CL |VtP0 |)/In6 , where VtP0 “ VtP1 are the equally assumed threshold voltages of transistors P0 and P1, then positive feedback of cross-coupled inverters N0, P0 and N1, P1 begins and the latch regenerates to OUT “ VComp and OUT “ VSS in the case INP > INN and vice versa. CL is the overall load capacitance of an output node. The output voltage difference Δ u(t “ t0 ) “ OUT (t “ t0 ) − OUT (t “ t0 ) « 2|VtP0 |gmn2 Δ Uin /In4 at this time t0 determines the initial voltage difference of the second phase, where positive feedback of the latch is turned on. With this initial voltage difference the latch regenerates similar as depicted in (8.2) (see (8.5), [18]). 1 gmn2 Δ Uin gmC− r t Δ u(t ≥ t0 ) “ 2|VtP0 | e L (8.5) In4 In (8.5) gm is the overall transconductance and r is the overall output resistance of the latch P0, P1, N0, N1. In principle the comparator structure of Fig. 8.6a has a rail-to-rail output voltage swing and consumes only dynamic power. The latch-type sense amplifier was produced in a 0.13 µm/1.5 V CMOS process and worked down to a supply voltage of 0.7 V [18]. The delay time was determined with electronic beam measurements and is e.g. 119ps for an input voltage difference of 100 mV. Disadvantageous is, that a sufficient supply voltage level is needed due to the stack of transistors (comparison time longer than 11 ns at 0.7 V). The comparator circuit in Fig. 8.6b is a further development of Fig. 8.6, which was first proposed in [19]. The amount of stacked transistors between the supply rails are reduced by adding an additional input amplifier (transistors N2, N3, N4, N5, P2, P3) instead of transistors N2 and N3 in Fig. 8.6a. In the reset phase (CLK “ VSS , CLK “ VComp ) transistors N6 and P4 are switched on and transistors P2 and P3 are turned on. So nodes DI 180 B. Goll and H. Zimmermann and DI are pulled to supply voltage level VComp thus both output nodes OUT and OUT are pulled to VSS . When CLK switches to VComp (CLK “ VSS ), transistors P2 and P3 are turned off, transistors N6 and P4 are switched on and the comparison phase starts. The internal nodes DI and DI are discharged by transistors N2 and N3 and corresponding to the input voltage difference CINP − CINN an amplified voltage difference DI − DI occur. This voltage difference is amplified again by transistors N4 and N5, which drives the latch. The latch pulls OUT to VComp and OUT to VSS in the case of CINP > CINN and vice versa. Because the input voltage difference is amplified two times with transistors (N2, N4 and N3, N5 respectively) a comparably large voltage drives the latch. Therefore and due to the fact that less transistors are stacked between the supply rails, this type of comparator circuit is capable for low-voltage operation. In [19] the circuit of Fig. 8.6b was fabricated in a 90 nm/1.2 V CMOS technology. Simulation results have shown, that this sense amplifier needs e.g. a delay time of «90ps for an input voltage difference of 10 mV at a low supply voltage of 1 V. In principle this circuit is faster than the circuit shown in Fig. 8.6a. Measurement results have shown that this sense amplifier has an offset voltage of σOS “ 8 mV. Furthermore a power consumption of 225 µW at a clock frequency of 2 GHz at 1.2 V supply voltage and 50 mV input voltage difference has been measured. 8.5 A Comparator in 0.12 µm CMOS Technology Requiring 0.5 V at 600 MHz This section describes a comparator, which is capable to work down to a supply voltage of 0.5 V with a maximum clock frequency of 600 MHz [21]. Figure 8.7 shows the schematic of the comparator. Like in many comparator circuits, here a clock cycle is divided into a reset and a comparison phase. During reset phase the voltage level at CLK is VSS thus turning off transisitors N0 and N1 and turning on transistors P0 and P1. In reset phase nodes CLK and CLKR have the same level of VSS because the gate-source voltage of N8 is larger than the threshold voltage VtN8 of this transistor. Both output nodes OUT and OUT are pulled to potential VComp thus creating an initial condition for the following comparison phase. Comparison of the input voltages CINP with CINN starts when CLK switches to voltage level VComp In opposite to a conventional comparator, transistors P0 and P1 are used to reset the comparator when CLK has the level of VSS and when CLK changes to level VComp the same transistors are biased as active load. So additional reset switches, which contribute parasitic capacitances to the output nodes and reduce speed are avoided. Because transistor N8, which is biased with an adjustable bias voltage T BIAS at its gate, has been added to the clock line, CLKR rises to T BIAS − VtN8 , if sub-threshold and leakage currents are neglected for simplicity and an ideal quadratic MOS-transistor characteristic is assumed. So P0 and P1 are biased to become active loads. At the beginning of the comparison phase the output nodes 8 Clocked Nanometer CMOS Comparators 181 1.5V TBIAS-VtN8 1.0V CLK 0.5V CLKR 0.0V 1.5V OUT VComp 0.0ns 0.1ns 0.2ns 1.0V OUT TBIAS N8 CLKR 0.5V 0.0V P0 P1 0.0ns 0.1ns 0.2ns NWELL OUT OUT CINP N4 N5 CINN N6 N7 CL CL N2 N3 VSS VSS N0 N1 VSS VSS CLK Fig. 8.7 Schematic of the comparator have been pre-charged initially to VComp from previous reset. Transistors N6 and N7 are on and each of the transistors N2 and N3 (latch) has initially a gate voltage near VComp . Therefore the tendency to speed up transistors N2 and N3 is given. This and the fact that N2 to N8 are transistors with a low threshold voltage of about 0.29 V, provided by this CMOS process, it is possible to drive the comparator even down to a supply voltage of VComp “ 0.5 V. Due to positive feedback of transistors N2 and N3 the latch regenerates depending on the input-voltage difference at transistors N4 and N5. Transistors N6 and N7 are added below the input transistors N4 and N5 to reduce static current flow after the decision of the comparator. This can be seen when the voltage level at e.g. OUT is below the threshold voltage of N7, the path via N5 and N0 to VSS is cut off. Also the path between OUT and OUT via transistors N4, N5, N6 and N7 is cut off. At pin NW ELL the separated n-well of P0 and P1 can be biased with a DC voltage to somewhat utilize the backgate effect to have an additional possibility to adjust the currents through transistors P0 and P1. Transient simulations of the comparator can be seen in Fig. 8.8 for a supply voltage of VComp “ 0.5 V. A test chip for the comparator has been designed, which is shown in Fig. 8.9. The chip is divided into two parts, one with a supply voltage of VDD “ 1.5 V for optimal functionality of CMOS logic needed for measurement purposes, and a second part with supply voltage VComp , where the comparator is placed. The clock is applied to pin CLKIN and processed by the clock driver to two complementary rectangular clock signals CLK and CLK with the logic levels VSS for low and VComp for high. RC low-passes (R1 , C1 and R2 , C2 ) are added for adjusting the clock duty cycle to about 50% by varying the bias voltage at CLKIN. The mean voltage at pins CLKAV P and 182 B. Goll and H. Zimmermann CLK 0.5 CLKR Voltage [V] CINN (a) CINP= (a) (b) =CINN±25m V 0.1 0.0 (b) CINP = -0.1 =CINN±100m V 0.5 CLK Voltage [V] OUT (a) (b) OUT 0.1 0.0 -0.1 3 4 5 6 Time [ns] Fig. 8.8 Transient simulation of the comparator at a supply voltage of VComp “ 0.5 V and 500 MHz clock frequency: T BIAS “ 0.4 V (a) CINP − CINN “ ±25 mV (b) CINP − CINN “ ±100 mV DIG1 R1 CREF CLKAVN CLKAVP C1 C2 R2 Switch Clock driver CLK TCLK CLKIN CLK TCLK 50 VSS DIG2 Output drivers Comparator CINP SOUT TOUT COUT OUT 50Ω VSS 50 SOUT OUT TOUT CINN COUT NWELL Adapters TBIAS VComp to VDD Transfer stages LREF Area: Supply voltage of comparator VComp Fig. 8.9 Block diagram of the test chip containing the comparator to be measured CLKAV N is a measure for the duty cycle. The adapters convert the logical levels VComp and VSS to levels VDD “ 1.5 V and VSS “ 0 V. During reset of the comparator the decision is held in the transfer stages. With a digital switch, controlled by pin DIG1, signals CLK or CLK can be checked at output CREF. The output drivers are in 8 Clocked Nanometer CMOS Comparators 183 TCLK Adapter Comparator LREF DIG2 VComp to VDD VDD V DD P5 BIAS VDD VDD VComp VDD VDD P2 VSS VDD VSS VDD P3 P4 P6 P7 VDD VDD P8 VDD N15 OUT SOUT TOUT N12 N13 VSS VSS VSS N9 N14 P9 VDD VDD N10 N11 VSS R0 VSS VSS VSS VSS V SS VSS Transfer stage TCLK Fig. 8.10 Schematic of the adapter and block diagram of the transfer stage principle a chain of inverters and are capable to drive a 50 Ω off-chip measurement system. The schematic of the adapter with the following block diagram of the transfer stage is depicted in Fig. 8.10. At the output of a buffer-inverter, which consists of transistors N9 and P2 and which is supplied by VComp , a differential amplifier (transistors P3, P4, P5, N10, N11 and resistor R0 ) compares the logic signal with a voltage LREF. The difference is amplified so that the resulting output voltages are compatible to the logic levels of the following inverter, consisting of transistors N12 and P6 and which is supplied by VDD . LREF is a DC bias voltage and is applied and adjusted from outside the chip. Resistor R0 enhances somewhat the bandwidth of the differential amplifier. During reset phase of the comparator the decision of the previous comparison phase is held dynamically in the transfer stage at the output of the first transmission gate (transistors N14 and P8) at the gates of the following buffer. With the digital pin DIG2 it can be chosen, whether the second transmission gate (transistors N15 and P9) is always switched on or connected to the clock, where it is only switched on, when the first transmission gate (transistors N14 and P8) is off. With this second possibility a constant overall delay time in relation to the clock is achieved to avoid adjusting the optimal delay time in the BER analyzer station for every measurement, because the comparator’s decision time depends on several parameters, e.g. the input voltage difference. In the last case, where both transmission gates are turned on and off inversely the output signal of the comparator is additionally delayed by half of the clock period in the transfer stage. Monte Carlo simulations of the standard deviation of the offset of the comparator have the results of σOS “ 22.1 mV for the case of VComp “ 1.5 V, T BIAS “ 1 V and 0.75 V input common-mode voltage and σOS “ 46 mV for the case of VComp “ 0.5 V, T BIAS “ 0.5 V and 0.4 V input common-mode voltage. 184 B. Goll and H. Zimmermann Clock input stage Adapters and switches Clock driver Comparator Output drivers Transfer stages Adapters Fig. 8.11 Layout plot and microphotograph of the test chip (1.38×1.39 mm2 ) with the comparator CLK: 3GHz TBIAS=0.69V CLK: 5GHz CLK: 4GHz CINP: Bias level TBIAS=1V TBIAS=1.14V Ampl. 9.9mV of 0.6V CINP: Bias level Ampl. 9.9mV NWELL=0.9V CINP: Bias level BER of 0.65V BER NWELL=1.5V VComp=1.5V of 0.65V 1E-01 1E-01 TBIAS=0.69V 1E-02 1E-02 CLK: 3GHz 1E-03 1E-03 CINP: PRBS 231-1 VComp =1.5V 1E-04 1E-04 NWELL=1.5V VComp =0.5V 1E-05 1E-05 NWELL=0.5V 1E-06 VComp =0.5V 1E-06 TBIAS=0.5V 1E-07 NWELL=0.5V 1E-07 CLK: 400MHz 1E-08 TBIAS=0.5V 1E-08 CINP: PRBS 231-1 CINP: Bias level Ampl.: 20.8mV 1E-09 of 0.36V 1E-09 CLK: 600MHz VComp=1.5V 1E-10 1E-10 Ampl. 11.2mV 1E-11 1E-11 NWELL=1.5V NWELL=1.5V CLK: 5.5GHz TBIAS=1.14V 1E-12 CLK: 500MHz TBIAS=0.9V 1E-12 CLK: 400MHz CLK: 5GHz 1E-13 CINP: Bias level 1E-13 CINP: PRBS 231-1 0 10 20 30 40 50 60 of 0.65V 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 31 Ampl.: 29mV Amplitude of PRBS 2 -1 (mV) at CINP Bias level of CINP (V) CINN: Bias level of CINP-offset CINN: Bias level of CINP-offset Fig. 8.12 BER measurements: On the right side the measured BER versus the bias level at CINP is shown and on the left side BER measurements versus the amplitude at the optimal operating point at different parameters are shown The test chip has been fabricated in a 0.12 µm CMOS technology with 1.5 V nominal supply voltage. A layout plot and a microphotograph of the test chip can be seen in Fig. 8.11. The area of the whole test chip amounts to 1.38×1.39 mm2 . Thereof 22×21 µm2 is dedicated to the comparator. BER measurements were done by applying a bias voltage at CINP, which was superimposed by a 231 -1 pseudo-random-bit-sequence (PRBS). In Fig. 8.12 on the right side the measured BER versus the bias level at CINP, which is similar to the input common-mode voltage, at different clock frequencies, supply voltages 8 Clocked Nanometer CMOS Comparators 185 CINN VComp =1.5V NWELL=1.5V CINP: Bias Level 0.8V 200mV/div CLKIN (6GHz) 500ps/div COUT Fig. 8.13 Measured transient behavior at 6 GHz and amplitudes of PRBS 231 − 1 are shown. The amplitude is defined here with CINP − (CINN + offset), because during measurements CINN and CINP were biased separately to compensate for the offset of the comparator. In Fig. 8.12 (right side) it can be seen, that every curve has a working point at a bias level of CINP, e.g. 0.6 V at 1.5 V supply and 3 GHz clock, where the BER is optimal. For fine- adjustment the bias voltage at NWELL can be lowered, which typically shifts this point to a higher input common mode level due to the back-gate effect. At the left side of Fig. 8.12 some BER measurements versus the amplitude of PRBS 231 − 1 at the optimal working point for different parameters are shown. To achieve a better BER the input amplitude has to be raised, e.g. more than 21.2 mV are needed for a BER better than 10−9 at 0.5 V/400 MHz. The measured comparator worked down to a supply voltage of VComp “ 0.5 V with a maximal clock frequency of 600 MHz consuming 18 µW. For a BER better than 10−9 a minimal amplitude of 60.5 mV at 600 MHz, 25.8 mV at 500 MHz and 21.2 mV at 400 MHz has to be applied to the comparator. At a supply voltage of VComp “ 1.5 V these values are 38 mV at 5.5 GHz, 29.4 mV at 5 GHz, 16.5 mV at 4 GHz and 11.2 mV at 3 GHz. At 6 GHz a BER of 10−6 is achieved at an amplitude of 150 mV. The comparator has a power consumption of 2.65 mW at VComp “ 1.5 V with an operating clock of 6 GHz and 2.17 mW at VComp “ 1.5 V with an operating clock of 4 GHz, which was measured at a separate pad to supply the comparator of the test chip. A measured oscilloscope picture can be seen in Fig. 8.13 at a clock frequency of the comparator of 6 GHz. 8.6 Delay Time Reduction for a Comparator in 65 nm CMOS Technology for Supply Voltages Down to 0.65 V The comparator circuit shown in Fig. 8.6a is a widely used standard circuit with rail- to-rail output swing, with high-impedance input and no static power consumption. Furthermore this circuit has the advantage of a good robustness against noise and mismatch, because among other reasons it can be also designed with large 186 B. Goll and H. Zimmermann input transistors N2, N3 e.g. to minimize the offset, where their larger parasitic capacitances do not directly affect switching speed, which depends primarily on the load capacitances at the output nodes OUT and OUT . Disadvantageous is the fact that due to the many stacked transistors a sufficient high supply voltage is needed for a proper delay time [19]. In low-voltage UDSM-CMOS technologies this may cause problems, where even a stand-alone latch (e.g. used in [19]) as shown in Fig. 8.2 with its two cross-coupled inverters, suffers on a higher delay-time, if the supply voltage is reduced or if a low-power process with higher transistor threshold- voltages is used. For the standard comparator in Fig. 8.6a, after the reset phase the initial condition of the comparison phase is OUT “ OUT “ VDD . So at the beginning of decision only transistors N0 and N1 of the latch contribute somewhat to positive feedback until the voltage level of one output node has dropped enough to turn on transistor P0 or P1 to start complete regeneration. To solve these problems a proposed comparator design with a modified latch is presented [22], where the latch of the conventional circuit in Fig. 8.6a has been replaced by a new latch for low supply-voltage operation, where the advantages of the resulting comparator circuit are again a high-impedance input, a rail-to-rail output swing, no static power consumption and non-direct influence of parasitic capacitances of the input transistors on the output nodes and therefore to switching speed have been kept. The circuit of a comparator with a modified new latch is shown in Fig. 8.14, where in opposite to the conventional latch used in Fig. 8.6a, where only N0 and N1 are initially on, the latch of the proposed comparator is expanded into two paths between the supply rails (transistors N0, N1, P0, P1, P4, P5). So at the beginning of the comparison phase, where both output nodes have the initial condition OUT “ OUT “ VComp , transistors N0, N1 are turned on. But also transistors P0, P1 are turned on and build together with the input transistors N2 and N3 an amplifier with a distinct operating point. Finally the complete positive feedback is done with N0, N1, P0, P1, where P4 and P5 help with additional amplification. The advantages of a high-impedance input, a rail-to-rail output swing, no static power consumption and no direct influence of parasitic capacitances of N2, N3 to the output nodes are kept. A clock period is divided into a reset phase and a comparison phase, where the voltage at CINP is compared with that at CINN. In the reset phase (CLK “ VSS ) an initial condition OUT “ OUT “ VComp for the following comparison phase (CLK “ VComp , VCoomp is the positive supply voltage of the comparator) is established. During reset, transistor N6 is switched off and transistors P2, P3, N4 and N5 are on. Consequently the output nodes OUT and OUT are pulled towards VComp by reset transistors P2 and P3. This causes transistors P4 and P5 to be switched off. Reset transistors N4 and N5 are switched on and pull both internal nodes FB and FB to VSS . As a consequence transistors P0 and P1 are turned on and help pulling OUT and OUT to the final voltage level VComp . Comparison of the input voltages CINP with CINN is started, when CLK switches to voltage level VComp (comparison phase) thus transistor N6 is turned on and P2, P3, N4 and N5 are turned off. At the very beginning, transistors P4, P5 are switched off, transistors P0 and P1 work in linear region and act as load for an amplifier 8 Clocked Nanometer CMOS Comparators 187 VComp 1.2 FB Voltage [V] 1.0 P4 P5 0.2 FB FB FB 0.0 N4 N5 CLK 0.0 0.1 0.2 0.3 0.4 CLK 1. 2 Time [ns] Voltage [V] 1.0 CINP VSS CLK 0.5 1.2 Voltage [V] CINN 1.0 0.0 VComp OUT 0.0 0.1 0.2 0.3 0.4 0.5 Time [ns] OUT 0.0 0.0 0.1 0.2 0.3 0.4 P0 P2 P3 P1 Time [ns] OUT OUT N0 N1 N2 N3 CINN CINP N6 CLK VSS Fig. 8.14 Circuit of the comparator with the modified latch with N2, N3. Transistors N0 and N1 are initially on (initially OUT “ OUT “ VComp and FB “ FB “ VSS ). Assuming that the voltage at CINP is larger than the voltage at CINN, then transistor N3 pulls the voltage level at output node OUT down faster than N2 does it at output node OUT . As a consequence transistor P4 begins to conduct when the potential at OUT becomes smaller than VComp − |VtP4 |, where VtP4 is the threshold voltage of P4. In this initial time period also a small amount of positive feedback is contributed by transistors N0 and N1. When P4 begins to conduct, node FB is charged towards VComp (N4, N5 are off) and finally complete positive feedback is started. Transistor P1 is turned off and P0 keeps conducting, because of node OUT is pulled to VComp thus P5 keeps off and remains near VSS (The input voltage difference CINP − CINN is assumed to be sufficient). When comparison has finished, transistors N1, P4 and P0 are switched on and N0, P1 and P5 are turned off. Output node OUT is at voltage level VComp and OUT at VSS . No static current can flow after decision. When considering the other case of CINP > CINN, OUT is pulled to VSS and OUT to VComp respectively. For comparison of the decision times at different supply voltages of the pro- posed comparator containing the modified latch of Fig. 8.14 with the conventional comparator of Fig. 8.6a have been simulated and are shown in Fig. 8.15. Both comparators were designed in a similar way so that the decision time (50% clock 188 B. Goll and H. Zimmermann Fig. 8.15 Comparison of the 3.0 decision time of the D e la y o f O U T - O U T [n s ] conventional comparator in 2.5 Comparator with modified latch Fig. 8.6a with the proposed Conventional comparator comparator containing the 2.0 modified latch in Fig. 8.14 versus their supply voltage. 1.5 The decision time is defined here as the time duration 1.0 between 50% of the rising clock edge and 50% of final 0.5 output voltage difference OUT − OUT “ VComp 0.0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2 Supply voltage (VComp ) of the comparator [V] Fig. 8.16 Block diagram of the test chip including the comparator edge to 50% of final output voltage difference OUT − OUT “ VComp ) is equal for VComp “ 1.2 V and same input conditions. For example at a supply voltage of VComp “ 0.6 V, the proposed comparator containing the modified latch needs only 650 ps instead of 2.95 ns of the conventional comparator. Therefore the comparator with the modified latch is capable of low-voltage operation. The block diagram of a test chip with the proposed comparator, which is designed in a 65 nm low-power CMOS technology with a nominal supply voltage of VDD “ 1.2 V is shown in Fig. 8.16. The dotted rectangle marks an area, which 8 Clocked Nanometer CMOS Comparators 189 is supplied separately with a voltage VComp to be able to investigate the behavior of the comparator when VComp is lowered. Outside of this area a supply voltage of the nominal VDD “ 1.2 V is applied to have always functionality of additional measurement circuitry for characterization of the implemented comparator. With the help of the clock driver a non-inverted digital clock CLK and the appropriate inverted clock CLK is generated, where the voltage levels change between VComp for logic high and VSS for a logic low. Generation of an on-chip clock signal is done by applying a sine-wave, where the frequency defines the on-chip clock frequency and the DC bias voltage level defines the duty cycle to pad CLKIN. For adjusting the duty cycle, the RC low-passes R2 , C2 and R3 , C3 are added to measure the mean voltage (corresponding to duty cycle) of the internal clock lines CLK and CLK at pads CLKAV P and CLKAV N, respectively. All high frequency inputs CLKIN, CINP and CINN are terminated with on-chip 50 Ω resistors to match the off-chip lines. The transfer stage is built in a similar way as described in Sect. 8.5, where DIG has the same function as DIG2 in Fig. 8.9. In the transfer stage adapter are added, which are a chain of two inverters, where each inverter is supplied separately for stepwise increasing the supply voltage from VComp to VDD “ 1.2 V. The output drivers consist of a chain of inverters and are able to drive off-chip 50 Ω measurement equipment. Additionally RC low-passes R0 , C0 and R1 , C1 have been added at the output driver with which in addition with the transfer stage the delay time td of the comparator can be measured [22]. The delay time td is here defined as the time duration, which begins at the time point, when the voltage level has reached 50% of VComp at the rising edge of CLK to the time point, when OUT has fallen to the switching threshold of the following inverter («50% of VComp ) in the case of CINP > CINN. For test purposes a chip with an area of 930 × 500 µm2 was fabricated in a low-power 65 nm/1.2 V CMOS technology. Thereof 28.4 × 49.1 µm2 is dedicated to the comparator. Due to Monte-Carlo simulations a run of 50 samples revealed, that the standard deviations of the offset are 1.9 mV @ CINN “ 0.6 V (VComp “ 1.2 V), 4 mV @ CINN “ 0.55 V (VComp “ 0.75 V) and 6.1 mV @ CINN “ 0.5 V (VComp “ 0.65 V). The influence of noise to the decision of the comparator and thus the sensitivity can be characterized with the help of statistical measurements by measuring the BER with an appropriate pattern generator and receiver. At CINN a reference voltage and at CINP a PRBS 231 − 1 were applied, which was superimposed to a bias voltage of CINN + offset to compensate the offset of the comparator. The amplitude of a bit-sequence is defined here, that the bit-sequence switches at CINP ± amplitude around voltage level CINN + offset, while at CINN the reference voltage is applied. Measured BER results of a typical test chip are shown in Fig. 8.17. To achieve a BER “ 10−9 at 1.2 V supply, an amplitude of 7.8 mV at 3 GHz, 16.5 mV at 4 GHz and 145 mV at 5 GHz had to be applied. If VComp is lowered, 7 mV at 1 GHz/0.75 V, 6.9 mV at 0.5 GHz/0.65 V and 12.1 mV at 0.6 GHz/0.65 V have been measured. The results of the mean delay time of the comparator, which has been determined by a measurement of ten chip samples, where an on-chip implementation for measuring of the delay time has been used [22], are shown in Fig. 8.18. For an amplitude of e.g. 15 mV at the input of the comparator the mean delay times (σ « 7 ps) were 93 ps at CINN “ 0.65 V, 190 B. Goll and H. Zimmermann VComp=0.65V V =0.65V CLK: 500MHz Comp VComp=0.65V CLK: 500MHz CINN: Bias level of 0.5V CLK: 600MHz BER CINP: Amplitude 5.8mV BER CINN: Bias level of 0.5V 1E-02 1E-02 VComp =1.2V 1E-03 1E-03 CLK: 4GHz 1E-04 1E-04 CINN: Bias level of 0.61V 1E-05 1E-05 1E-06 1E-06 1E-07 1E-07 1E-08 1E-08 1E-09 1E-09 V =1.2V 1E-10 Comp 1E-10 CLK: 4GHz VComp =0.75V 1E-11 CINP: Amplitude 14.7mV 1E-11 CLK: 1GHz VComp =1.2V 1E-12 Amplitude 16.1mV 1E-12 CINN: Bias level CLK: 3GHz Amplitude 17.4mV of 0.6V CINN: Bias level of 0.55V 1E-13 1E-13 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Bias level at CINN [V] Amplitude of PRBS 2 31 -1 [mV] at CINP 31 (CINP is biased with CINN+offset) (CINP: PRBS 2 -1, biased with CINN+offset) Fig. 8.17 BER measurements: On the left side the measured BER versus the bias level at CINP is shown and on the right side BER measurements versus the amplitude nearby the optimal operating point at different parameters are shown 150 CINN=0.6V measured CINN=0.55V Measured delay time [ps] 100 CINN=0.65V 50 VComp = VDD =1.2V 10 Measured @ CLK: 3GHz 0 0 1 5 10 15 Amplitude [mV] of rectangular signal at CINP (CINP is biased with CINN+offset for offset compensation) Fig. 8.18 Delay time measurements 104 ps at CINN “ 0.6 V and 115 ps at CINN “ 0.55 V at VComp “ 1.2 V. The measured power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V supply voltage), 295 µW at 1 GHz (0.75 V supply voltage), 128 µW at 0.6 GHz (0.65 V supply voltage). 8 Clocked Nanometer CMOS Comparators 191 8.7 Conclusion An important element in ADCs, but also in other applications, like e.g. in sense amplifiers in SRAMs or for data regeneration, is the comparator. It compares an input signal with a reference voltage and has as a result a logical stage, which indicates whether the potential is lower or higher than a reference potential. In fast ADCs, e.g. in a flash ADC or a folding converter system, mostly many parallel comparators of the clocked and regenerative type are implemented, which work in parallel. Modern UDSM CMOS processes are optimized for implementing as many logic gates as possible per area with a minimum of power consumption thus the structure sizes are small. Therefore the design of analog circuits has to deal with this circumstances, e.g. a low supply voltage, gate tunnel currents and nonideal transistor characteristics. Especially for e.g. mobile devices, circuits are demanded, which work even at a low supply voltage. In this chapter comparators for UDSM CMOS technologies have been described, e.g. a comparator in a 0.12 µm/1.5 V- low-Vt CMOS technology, which works down to a supply voltage of 0.5 V with 600 MHz clock frequency with 18 µW power consumption or a comparator in a 65 nm/1.2 V low-power CMOS-process, which is capable of operating down to 0.65 V at 600 MHz clock thus consuming 128 µW power. References 1. Sandner C, Clara M, Santner A, Hartnig T, Kuttner F (2005) A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µ m Digital CMOS, IEEE proceedings of design, automation and test in Europe conference and exhibition (DATE’05), vol 3, pp 223–226 2. Uyttenhove K, Steyaert M (2001) A CMOS 6-bit, 1 GHz ADC for IF Sampling Applications, IEEE MTT-S international microwave symposium digest, vol 3, pp 2131–2134, May 2001 3. Park S, Palaskas Y, Flynn MP (2006) A 4GS/s 4b Flash ADC in 0.18µ m CMOS, IEEE International Solid-State Circuits Conference, pp 570–571, Feb 2006 4. Paulus C, Bl¨uthgen H-M, L¨ow M, Sicheneder E, Br¨uls N, Courtois A, Tiebout M, Thewes R (2004) A 4GS/s 6b Flash ADC in 0.13µ m CMOS, Digest of symposium on VLSI circuits, pp 420–423, June 2004 5. Klar H (1996) Integrierte Digitale Schaltungen MOS/BICMOS. Springer, Berlin 6. Veendrick HJM (1980) The behaviour of flip-flops used as synchronizers and prediction of their failure rate. IEEE J Solid State Circ 15(2):169–176 7. Gregorian R (1999) Introduction to CMOS Op-amps and comparators. Wiley, New York 8. Figueiredo PM, Vital JC (2006) Kickback noise reduction techniques for CMOS latched comparators. IEEE Trans Circ Syst II 53(7):541–545 9. Lohstroh J (1983) Worst-case static noise margin criteria for logic circuits and their mathemat- ical equivalence. IEEE J Solid State Circ 18(6):803–807 10. Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid State Circ 22(5):748–754 11. Bhavnagarwala AJ, Tang X, Meindl JD (2001) The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J Solid State Circ 36(4):658–665 12. Weinrichter H, Hlawatsch F (1991) Stochastische Grundlagen nachrichtentechnischer Signale. Springer, New York 192 B. Goll and H. Zimmermann 13. Nikoozadeh A, Murmann B (2006) An analysis of latch comparator offset due to load capacitor mismatch. IEEE Trans Circ Syst II 53(12):1398–1402 14. Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J Solid State Circ 24(5):1433–1440 15. Lakshmikumar KR, Hadaway RA, Copeland MA (1986) Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J Solid State Circ sc- 21(6):1057–1066 16. Schneider K, Zimmermann H (2006) Highly sensitive optical receivers. Springer, Berlin 17. Kobayashi T, Nogami K, Shirotori T, Fujimoto Y (1993) A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J Solid State Circ 28(4):523–527 18. Wicht B, Nirschl T, Schmitt-Landsiedel D (2004) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid State Circ 39(7):1148–1158 19. Schinkel D, Mensink E, Klumpernik E, van Tuijl E , Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18ps setup + hold time. IEEE international solid-state circuits conference, pp 314–315, Feb 2007 20. Annema A-J, Nauta B, van Langevelde R, Tuinhout H (2005) Analog circuits in ultra-deep- submicron CMOS. IEEE J Solid State Circ 40(1):132–143 21. Goll B, Zimmermann H (2007) A 0.12µ m CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6GHz. IEEE international solid-state circuits conference, pp 316–317, Feb 2007 22. Goll B, Zimmermann H (2009) A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans Circ Syst II 56(11):810–814 Chapter 9 Low-Power Electronics for Biomedical Sensors Syed Kamrul Islam, Fahmida Shaheen Tulip, Kai Zhu, and Melika Roknsharifi 9.1 Introduction Long-term reliable detection of various biological signals in biomedical applications requires excellent signal sensitivity and adequate power savings. Integration of sensors and modern integrated circuit (IC) technology offers rapid and reliable identification and analysis of the biological signals. However, due to tremendous diversity of the biological samples and the complexity associated with the anal- ysis of these samples, implementation of a biomedical sensor system requires a highly challenging task of integration of sensor technology with sophisticated data analysis techniques. Accurate detection and classification of microanalytes or microorganisms using classical laboratory-based techniques is time consuming and cumbersome. Early detection and characterization of microanalytes not only help minimizing potential biohazards but also prevent spreading of life-threatening contagious diseases. Reliable identification and characterization of the biological samples thus require robust, low cost, rapid sensing, and high throughput capability of the sensor system along with portability of the devices for field applications. The evolution of sophisticated micro- and nano-fabrication processes have led to the development of various miniature, light-weight, cost-effective and energy- efficient sensors for biomedical applications such as monitoring of glucose [1–3], lactate [4], pH [5], carbon dioxide (CO2 ) [6], oxygen (O2 ), etc. The integration of the sensor technologies with low-power signal processing electronics resulted in the development of implantable sensors for various biomedical applications such as visual prosthesis for the blind [7], cochlear implant for the deaf [8], neuromuscular stimulator for the brain [9], capsule endoscopy [10], gastrointestinal microsystems [11] etc. Electronic circuits mimicking biological systems have also been reported [12]. Bio-inspired electronic systems such as bionic ear or RF cochlea which S.K. Islam () • F.S. Tulip • K. Zhu • M. Roknsharifi The University of Tennessee, Knoxville, TN e-mail: [email protected]; [email protected]; [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 193 DOI 10.1007/978-1-4614-1383-7 9, © Springer Science+Business Media New York 2013 194 S.K. Islam et al. Fig. 9.1 An overview of wireless body area network (WBAN) based patient monitoring system have computation capabilities equivalent of 1 GFLOPS of spectral-analysis and gain-control computations with 14 µW of power on a 150 mV battery have been reported [13]. Wee et al. reported a 275 µW silicon vocal tract designed to be used with auditory processors [14]. An energy efficient (0.12 pJ per quantization level) analog-to-digital converter (ADC) inspired by the performance of spiking neurons in pattern recognition with time rather than with voltage or current have been reported by Yang et al. [15]. In addition, micro electro mechanical systems (MEMS) have also been used for biological applications such as delivery of potent drugs or hormones in the area of nervous and endocrine system actuation and detection of anthrax simulants [16, 17]. Neural network based adaptive information processing has also been proposed [18]. Low power electronic devices are gaining increasing importance in biomedical applications. These devices are used for diagnostic as well as therapeutic applications. Due to recent development in data acquisition systems and novel sensing materials, use of smart sensors for point of care application has become a reality. Emerging sensor technologies combined with the tremendous development in IC process technologies and wireless networks have resulted in a low-power sensor platform known as wireless body area network (WBAN) [19]. This wireless based patient monitoring system for a comprehensive healthcare alternative provides early detection of abnormal conditions and prevention of serious consequences. This system employs a number of different sensors to monitor various physiological phenomena and the sensor data is wirelessly transmitted to a server computer which communicates with the central database via internet. The data is monitored and stored in the central database and based on the sensor data proactive measures could be initiated by healthcare providers. An overview of this system is illustrated in Fig. 9.1. 9 Low-Power Electronics for Biomedical Sensors 195 9.2 Classification of Biosensors Generally, all biosensors can be classified as either physical or chemical. Physical biosensors measure parameters such as muscle displacement, blood pressure, core body temperature, blood flow, cerebrospinal fluid pressure etc. Chemical biosensors are employed to identify and measure the quantity of specific chemical compounds, detect the concentrations of various chemical species and monitor chemical activities in the body. Examples of different types of chemical sensors include gas, electrochemical, photometric and bioanalytic sensors. However, the bioanalytic sensors are often classified as a separate sensor category due to their importance and diversity. Bioanalytic sensors incorporate biorecognition reactions such as enzyme-substrate, antigen-antibody or ligand-receptor to identify complex biochemical molecules [20]. Depending on sensor-substrate interface, biosensors can be classified as fol- lows: 1. Non-contacting (Non-invasive)—Sensor that does not contact the subject being measured. 2. Skin-surface (Contacting)—Sensor which comes in contact with the skin surface temporarily. 3. Indwelling (Minimally invasive)—Sensor which is permanently secured with the subject but not implanted. 4. Implantable (Invasive)—Sensor which is implanted in the body cavity or under- neath the skin. Biosensors are employed in biomedical systems for patient care in hospitals, home, and even in some workplaces. A brief description of applications for healthcare applications is provided below: 1. Wireless Hospital Network: Inside the hospital, biosensors are used to monitor inpatients such as bedside monitoring, triage etc. These types of sensors collect data 24/7 and are usually designed to notify the healthcare workers when certain set alarm levels are reached. 2. Home Care Monitoring: Besides monitoring critical patients inside the hospitals, biosensors are also used to measure various physiological parameters during personal exercise at home to ensure the best self-management and motivation. 3. Rehabilitation: Biosensors can go a long way to help patients with chronic health conditions such as heart disease, Alzheimer’s disease and diabetes to maintain active lifestyles. These patients need constant monitoring of their vital signs and immediate help in case of emergency. 4. High-Risk Workers: For high risk workers such as firemen, astronauts, or people working in any high risk environment such as extreme cold or hot climates, mine etc. The monitoring of vital signs is of utmost importance and could possibly be the difference between life and death. Top ten targets for wireless health, as was identified in TEDMED 2009, are listed in Table 9.1 [21]. 196 S.K. Islam et al. Table 9.1 Top ten targets for wireless medicine Affected US Disease population (millions) Wireless solutions Alzheimer’s 5 Vital signs, location, activity, balance Asthma 23 RR, FEV1, air quality, oximetry, pollen count Breast cancer 3 Ultrasound examination COPD 10 RR, FEV1, air quality, oximetry Depression 21 Med. compliance, activity, communication Diabetes 24 Glucose, Hemoglobin A1C, activity Heart failure 5 Cardiac pressures, weight, BP, fluid status Hypertension 74 Continuous BP, Med. compliance Obesity 80 Smart scales, glucose, calorie in/out, activity Sleep disorder 40 Sleep phases/quality, vital signs 9.3 Applications of Biomedical Sensors 9.3.1 BioChem Lab-On-A-Chip: Smart Sensor Combining sensing devices with integrated signal-processing and telemetry circuits develops smart sensors. In most cases, multiple sensors are placed on a single chip to monitor various physiological parameters which are controlled by employing control signal from the integrated sensor select circuits; thereby making possible the realization of a lab-on-a-chip scheme. These sensors take advantage of the existing sensor technology, microfluidics and inexpensive CMOS integrated circuits and thus allow large-scale deployment. Figure 9.2 shows a lab-on-a-chip prototype for detection of bacteria [22]. The chip incorporates various functionalities including in situ analysis, DNA isolation and polymerase chain reaction (PCR). 9.3.2 Artificial Retina A prosthetic retina prototype has been developed under the smart sensors and integrated microsystems (SSIM) project at Wayne State University and the Kresge Eye Institute to provide people without vision or with limited vision with sufficient visual functionality to allow them to “see” at an accepted level. 9 Low-Power Electronics for Biomedical Sensors 197 Fig. 9.2 A lab-on-a- chip for integrated detection of bacteria including analysis, DNA isolation and PCR [22] Fig. 9.3 Location of smart sensor within the eye [24] This therapeutic sensor has two components, an IC and an array of sensors which are placed upon the retina. The electrical signals generated by the sensors are converted into chemical signals mimicking the normal operating behavior of the retina from light stimulation. As shown by Fig. 9.3, the front side of the retina is in contact with a microsensor array. The backside of the retina is stimulated electrically via artificial retina prosthesis. The electrical signal is then converted to chemical signals by the underlying tissue structure and carried to the brain via optic nerve, thus providing signal transmission into the eye. Signal transmission from the eye works in a similar 198 S.K. Islam et al. Cameraimage Signal RFpower/ In-vivo processing Retina Neural processing data wireless unit chip interface unit transmission transceiver Glasseswith CCD camera Wireless interface Fig. 9.4 Processing steps for retina prosthesis project [25] manner, but only in the reverse direction, providing a feedback system within the eye. Figure 9.4 depicts the processing steps from external image reception to transmission to artificial retina prosthesis. A camera mounted on an eyeglass frame feeds its output to a DSP unit for data reduction and processing. The camera is combined with a laser pointer for automatic focusing. The DSP unit transmits the processed data via wireless transceiver system to the implanted chip in the eye for subsequent decoding. Figure 9.4 shows a wireless transceiver setup inside the human body, but not within retina. 9.3.3 Glucose Level Monitor According to US National Institute of Health (NIH), 8.3% of total US population is affected by diabetes in 2010 [26]. The percentage was 5.9% in 1999 [25]. Diabetes is also responsible for complications such as heart disease, stroke, high blood pressure, blindness, kidney disease, and amputations. Current monitoring of blood glucose level requires pricking the finger with a lancet to collect a drop of blood that is analyzed either manually or electronically. The constant pricking of the same area over a period of years can damage the underlying tissue and the blood vessels. A wireless sensor implanted underneath the skin of the patient can constantly monitor blood glucose level without the need to frequent finger pricking as mentioned above. These implantable sensors represent minimally invasive methods of detection of glucose and other metabolites in the human body. A non-invasive wearable device known as “GlucoWatch” based on the coupling of reverse iontophoretic collection of glucose and biosensor functions has been developed by Cyngus Inc. [23] as shown in Fig. 9.5. The device provides up to three glucose readings per hour for up to 12 hours. The system has demonstrated the capability of measuring the electro osmotically extracted glucose with a clinically acceptable level of accuracy. 9.3.4 Organ Monitor In 2011, more than 112,000 people were waiting for an organ donation in the US [27]. In 2001, this number was over 75,000 [25]. Unfortunately, a large number of 9 Low-Power Electronics for Biomedical Sensors 199 Fig. 9.5 Components of a watchlike glucose monitor being developed by Cygnus Inc [23] the donated organs go unused as there is a very short window of time in which to transplant the organ before it becomes no longer viable. A better understanding of the condition of the organ could lengthen this window. Moreover, organ rejection after transplant is also a serious issue. Continuous monitoring of the patient after the transplant for symptoms of rejection is crucial. Biosensors can be employed for the monitoring of the condition of the donated organs as well as the symptoms of the rejection of the transplanted organs. 9.3.5 Cancer Detector In 2011, 571,960 people are expected to die of cancer in the US, with 1,596,670 new cases diagnosed [28]. In 1999, the number of new diagnosed cases was 1,221,800 [25]. As of yet, there is no conclusive findings on the prevention of this disease. As such, early detection is the key to survival. Several unique cellular morphology and molecular signature events change during cancer development and progression processes. By discerning these changes accurately with the help of biomarkers early and accurate detection and diagnosis of the disease is possible. 9.3.6 General Health Monitor In general, biosensors can be employed to monitor health conditions of patients as well as healthy persons. NASA has been working on several different biotechnology 200 S.K. Islam et al. and bioinstrumentation sensor systems to support life sciences research during space flight and ground based studies [25].These smart sensors can provide vital information about digestive or cardiac system of the astronauts. 9.4 Challenges Associated with Biosensors Intelligent systems are required for the analysis of multi-parametric data. In addition, the multi-parametric data must be correlated with established biomedical knowledge to derive clinically relevant indicators. The challenges associated with biosensor applications are summarized below: 1. The sensors must provide accurate alerting and signaling of the risk to support healthcare professionals in their decision making. 2. New indicators should be identified for predicting or diagnosing of the worsening conditions at early stages and for prompting early intervention. 3. Absence of wires restricts the power requirements of wireless sensors. One way to supply the constant source of power is to use an integrated battery. But even with conservationist techniques, replacing battery as often as required might not be a suitable solution. Another way is to use passive power sources, such as solar and vibration, which provide insufficient power for constant operation. This leads to an external, wireless power source to be the only solution. 4. As the power becomes limited, the computation is also limited. The amount of computation possible with a low power biomedical sensor is significantly less than that of a generic sensor. One way to work around this problem is to transmit the data to an external data processing device. 5. Sensors implanted in the body will have shape, size and material constraints. Human immune system is designed to reject foreign substances. Therefore, the sensor must be encased in biocompatible materials which act as the barrier between the body fluids and the sensor components. The biocompatible material must not hinder the operation of the sensor. Moreover, if the body rejects the implant, the functionality of the sensor can be adversely affected, which must be taken into consideration. 6. Implantable sensors are expected to last a long time, usually in the range of decades. As such, the sensor must be extremely robust and fault tolerant. In particular, the failure of one node should not cause the entire circuit to cease operation. The best method to ensure this is to have a distributed network. 7. In order to ensure functionality with low-power and confined area constraints, several small sensors may need to be placed in close proximity and are required to work in conjunction with each other. With multiple sensors communicating among themselves and with the external device, efficient use of the wireless spectrum is required. 8. Although it is important that the physician and the patient have accesses to the data received from the sensors, the information must remain secured to ensure patient confidentiality. Strict security mechanisms must be put in place to prevent outside interference. 9 Low-Power Electronics for Biomedical Sensors 201 9. There must be some proof that these devices will not harm but potentially help the test subjects. The prototypes must maintain strict standards for human safety before any human testing is done. Their testing and use must be regulated by the Food and Drug Administration (FDA). 9.5 Low-Power Circuit Design Low-voltage (LV), low-power (LP) circuit design techniques require careful con- sideration of the device behavior and the circuit topologies in order to meet the associated design challenges. Wouter A. Serdijn et al. [29] have identified the following design aspects with significant influences on the overall transfer quality for low-power system design: 1. System requirements, 2. Signal processing, 3. Indirect feedback, 4. Choice of information-carrying signal, and 5. Parasitics. For the input and the output of the system, the best representative signal such as the voltage or the current or the flux of the external physical quantity must be chosen so that there is almost a linear relationship between the electrical signal and the physical quantities [30]. In general, current becomes more favorable than voltage as the information-carrying quantity in a low-voltage low-power environment [29]. However, as the voltage signals can be easily distributed among different blocks by simply connecting the input terminals of all the blocks in parallel, it is a better option if a signal needs to be transmitted to different circuit blocks within the system. Whenever the system handles the information coming from several sensors or transducers, the current is a better choice as the information-carrying quantity compared to the voltage. This is due to the fact that the information coming from various transducers in the form of current signals can be easily added by connecting the output terminals of all the transducers in parallel. In addition, for the design of a feedback system for low-voltage operation, indirect feedback is typically more suitable compared to the direct feedback approach. In low-power IC design, parasitic admittances (node capacitances) are often more influential on the signal behavior than the parasitic impedances. As a result by terminating the signal path with low-impedance circuit results in better minimization of the parasitic components of the circuit. “Current-mode”, “switched-current” and “switched transconductance” techniques [31–33] support this argument with their inherent capability to exhibit good high-frequency properties. The major challenge associated with the low-voltage analog designer is that the threshold voltage and the drain-source saturation voltage do not scale down at the same rate as the supply voltage. In a typical 5 V CMOS process, cascode and regulated cascode structures are used in analog circuit design because of their high 202 S.K. Islam et al. output impedance and hence high voltage gain [34]. However, due to their limited voltage headroom, the cascode structures are not suitable for CMOS processes involving supply voltage below 2 V. Therefore the general trend in low-power designs entails the development of the circuits in horizontal i.e., cascade fashion instead of vertical stacking of the transistors. However, the cascade structures do not completely resolve the design challenges of low-voltage and low-power circuit design. Each stage can be considered as a parallel block and there is a potential chance of increasing the power consumption even with the low supply voltage. Most importantly, each stage contributes one pole and there is a potential chance of system instability if frequency compensation techniques are not used [35–37]. In can be pointed out that the threshold voltage Vth of a MOSFET does not scale down at the same rate as scaling of power supply voltage because of the sub-threshold current consideration in mixed signal environment [38] and the wide spread of Vth value for sub-micron technologies [39]. In order to overcome this relatively high threshold voltage and to reduce the overall power consumption, the following low-power circuit design techniques have been reported [40, 41]: (1) Sub-threshold design (2) Supply voltage reduction (3) Bulk-driven MOSFETs (4) Self-cascode MOSFET (5) Floating gate MOSFETs 9.5.1 Sub-Threshold Design MOSFET operating in sub-threshold region offers extremely low-power operation. In sub-threshold region, the drain current (ID ) variation with the gate bias voltage of the MOSFET shows exponential behavior and offers higher transconductance efficiency (gm /ID ), which allows the circuit to achieve desired performance in low- power operation. If the applied gate-source voltage is hundreds of millivolts higher than the threshold voltage so that the transistor channel is completely inverted, the transistor is considered to be biased in strong inversion (S.I.). If the gate- source voltage biasing decreases approaching the threshold voltage (Vth ), then the transistor region of operation is called moderate inversion (M.I.), and if it goes below the threshold voltage then this transistor is considered to be biased in weak inversion (W.I.). Typically when a MOSFET is operating in weak inversion or in sub-threshold region its unity current gain cut-off frequency ( fT ) deteriorates, thus making the device unsuitable for high frequency applications. However, modern deep submicron CMOS devices have achieved fT values greater than 100 GHz by technology scaling which has made them suitable for analog/RF circuit design even in sub-threshold region. 9 Low-Power Electronics for Biomedical Sensors 203 C.C. Enz et al. [42] introduced the following equation for the drain current of a MOSFET that is valid in all levels of the transistor inversion: Vp −Vs 2 ! Vp−Vd 2 ID “ IS ln 1 + e 2UT − ln 1 + e 2UT (9.1) where, IS “ 2nβ UT2 (9.2) and Vs is the source voltage of the transistor, Vd is the drain voltage of the transistor and Vp is the pinch off voltage of the transistor which can be estimated to be: VG − VT0 Vp – (9.3) n where, n is a function of gate voltage and can be estimated to be 1. The transistor current in (9.1) is defined to be the subtraction of the forward current and the reverse current. Forward current is generated based on the difference between the gate and the source voltages, while the reverse current is generated based on the difference between the gate and the drain voltages. If the drain-source voltage of the transistor is large enough [VDS > (VGS − Vth )] then the transistor enters the saturation mode. In S.I. region of operation, saturation occurs when Vs ≤ Vp and Vd > Vp . In this case the (9.1) can be simplified as shown below: ! Vp −Vs 2 ID – IS ln e 2UT − (ln(1))2 2 ! nβ nβ Vp − Vs “ 2nβ UT2 “ (Vp − Vs )2 “ (VGS − VTh0 )2 (9.4) 2UT 2 2 For W.I. region of operation saturation occurs when Vs > Vp , Vd > Vp and (Vd −Vs ) ≫ Vp . In this case the (9.1) reduces in to: Vp −Vs VGS −VTh0 Vp −Vs ID – 2nβ UT2 e 2UT “ 2nβ UT2 e 2UT e 2UT (9.5) The other parameter that can be used as a reference for defining the transistor level of inversion is known as inversion coefficient which can be calculated from (ID /IS ) ratio. According to [43], if the inversion coefficient be greater than 10 the transistor is biased in S.I. and if it be less than 0.1 the transistor is biased in W.I. Using (9.1) and (9.5) one can compare the difference between the behavior of the transistors biased in S.I. and the one that is biased in W.I. Based on (9.5) in W.I. region, the current is a strong function of the temperature. In addition, because 204 S.K. Islam et al. of the exponential relationship between the drain current and the threshold voltage, any small variation in the threshold voltage can cause a large variation in the drain current. Therefore providing a good matching is extremely hard in W.I. reign. In circuits containing current mirrors biasing the transistors in S.I. helps decrease the sensitivity to the threshold voltage mismatch. However, the exponential relationship between the drain current and the gate voltage in W.I. can help achieve higher transconductance efficiency at this level of inversion. Thus the voltage matching can be achieved more precisely by using the transistors biased in W.I. In this mode of operation a small change in VGS can cause a large change in the drain current and therefore for the same drain current, the VGS values of the transistors cannot differ by much. As discussed above, the transistors biased in W.I. can achieve the maximum transconductance efficiency (gm /ID ). The EKV model provides an equation for the transconductance of the transistor that is valid in all levels of inversion [42]. Equation (9.6) below represents this equation for the transconductance as a function of the inversion coefficient, ID ∂ ID I (2nβ UT ) gm “ –c S b (9.6) ∂ VGS ID 1 ID IS + 2 . IS + 1 Based on (9.6), gm for the conditions of S.I. and W.I. can be simplified as shown below: #a 2nβ ID IIDS > 10(S.I.) gm “ ID ID (9.7) nUT IS < 0.1(W.I.) From (9.7) in S.I. gm is proportional to square root of ID , while in W.I. it is proportional to ID . Binkley et al. [43] provides the plot shown in Fig. 9.6 that demonstrates the change of gm /ID based on the transistor level of inversion. From this figure gm /ID is maximized in W.I. that can help reduce the power consumption of the circuit. Therefore for the same current, the transistor biased in W.I. can achieve higher gm than the transistor biased in S.I. In this case the transistor which is biased in W.I. needs to be much wider than the other that is biased in S.I. This is because the gate-source bias applied in W.I. is much smaller than the one biased in S.I. Therefore biasing the transistors in W.I. usually asks for wider transistors. In addition, as discussed above, the biasing of the transistors in W.I. make them very sensitive to Vth variation and therefore can also be affected more by drain induced barrier lowering (DIBL). To decrease the sensitivity of the current to the drain voltage through DIBL, it is required to increase the length of the transistors. Therefore biasing the transistors in W.I. asks for a large sizing which generates a high parasitic input capacitance. However, it is not recommended in cases where the high parasitic capacitance cannot be tolerated. Therefore the best condition for biasing the transistors in week inversion is the first stage input pair transistors of the amplifier, where the maximum gm is required and the parasitic capacitance cannot 9 Low-Power Electronics for Biomedical Sensors 205 Fig. 9.6 Relationship between gm and the drain current in different regions of operation [43] affect the internal components of the circuit. Another advantage of biasing the input pair transistors in W.I. is the reduction of the total noise of the system. In low frequency circuit design flicker-noise has a huge impact on circuit quality. In these circuits the flicker noise can be derived from the equation below [44]: Kf v2i “ Δf (9.8) W LCox f Based on this equation the flicker noise can be reduced by increasing the size of the transistors. The use of the large transistors in the input pair of the first stage can be very helpful in reducing the flicker noise. The thermal noise of the differential amplifier can be calculated to be the ratio of the gm of the current mirrors to that of the first stage input pair. For a conventional amplifier shown in Fig. 9.7, the thermal noise density can be calculated to be [45]: 16kT gm3 gm7 v2 in,thermal “ 3gm1 1+2 + Δf (9.9) gm1 gm1 where, Δ f is the system frequency bandwidth and gm3 “ gm5 “ gm4 “ gm6 , gm7 “ gm8 and gm1 “ gm2 . Having the first stage transistors biased in W.I. and the current mirror transistors in S.I. can help decrease the ratios of gm3 /gm1 and gm7 /gm1 which leads to lower thermal noise. While having the current mirror transistors biased in S.I. can also help improve the current matching. 206 S.K. Islam et al. Fig. 9.7 Schematic of a VDD VDD conventional amplifier [45] M7 M8 VCP M9 VDD Vout IB M1 M2 VCN M10 V- V+ M5 M6 M3 M4 9.5.2 Supply Voltage Reduction In analog/RF circuit the power consumption is proportional to the supply voltage and thus reducing the power supply can reduce the power consumption of the circuit. Lower supply voltage also reduces the electric field and improves the long term device reliability. However, lower supply voltage limits the dynamic range in analog circuit and offers reduced voltage headroom for the cascode structures. Therefore it is necessary to develop new techniques to obtain the same performance while using a nominal power supply voltage. 9.5.3 Bulk-Driven Technique The bulk-driven MOS transistor concept was introduced by A. Guzinski et al. in 1987 [46], where the bulk terminals of the MOSFETs were used in the design of the differential input stage of an operational transconductance amplifier (OTA). The technique allows a designer to remove the voltage overhead associated with Vth from the signal path [47, 48]. The main idea to achieve the low supply voltage therefore is the reduction of the threshold voltages of MOSFETs. For a typical NMOS, the threshold voltage can be expressed as: a a Vt “ Vt0 + γ ( 2ϕF − VBS − 2ϕF ) (9.10) where, the parameters in (9.10) are identical to the standard SPICE parameters for MOSFETs. The second term in (9.10) will be negative if VBS is positive; thereby 9 Low-Power Electronics for Biomedical Sensors 207 Fig. 9.8 (a) a conventional a b gate-driven NMOS transistor, VDD VDD (b) a bulk-driven NMOS transistor Vin V SS Vin V SS V SS Fig. 9.9 Cross section of an V DD N-channel MOSFET bulk source drain N-channel depletion P-Substrate region a b Iin Iout IDSS IDSS Iin Iout VB VB Fig. 9.10 Typical configurations of a current mirror with (a) gate-driven NMOS and (b) bulk- driven NMOS reducing the Vth below Vt0 . Figure 9.8 shows a basic configuration of a conventional gate-driven NMOS transistor (a) and bulk-driven NMOStransistor (b).The cross section of an N-channel MOSFET (P-substrate technology) is shown in Fig. 9.9. Unlike the conventional gate-driven MOSFETs, the bulk-driven ones operate very similar to JFETs [47]. Besides, the channel width is constant as long as the gate bias does not change. Therefore, the bulk-driven MOSFETs can operate as a depletion- mode device Figure 9.10 shows the schematics of typical analog units such as current mirror and differential pairs with bulk-driven inputs; while the Fig. 9.11 shows the comparison between the differential pairs with gate-driven and bulk-driven NMOS transistors. The most prominent advantage of the bulk driven technique is the reduced voltage supply. Besides, the depletion characteristic allows zero, negative and even small positive values of bias voltage to achieve the desired DC currents [47], which provides a large input common mode range for the input signal. In addition, since 208 S.K. Islam et al. a b VDD VDD - RL RL RL RL vout + vout - vout + vout v+ v- v+ in in in v-in Itail Itail Fig. 9.11 Typical configurations of a differential pair with (a) gate-driven NMOS and (b) bulk- driven NMOS the poly-Si gate can totally turn the channel off, the turn-on/off ratio of the bulk- driven MOSFET is very large, which makes it good candidate for application in modulation circuits. There are also several limitations of the bulk-driven MOSFET which limit its wide acceptance. The first one is the lack of the availability of the isolated bulk terminals. For example, in P-substrate process, only PMOS (which is planted in N-well) can be used as bulk-driven MOSFET, since the bulk terminal of the NMOS is usually fixed to the most negative supply and cannot be fed with different voltages. Therefore, unless a deep N-well or a triple well process is available, the bulk-driven MOSFETs cannot be used in CMOS structures where both N and P type MOSFETs are required. According to [47], the transconductance of a bulk-driven MOSFET can be expressed as, diD γ gm gmb “ “ ? (9.11) dvBS 2 2ϕF − VBS which can be designed to be either larger or smaller than the transconductance of a gate-driven MOSFET. However, the input capacitance can largely limit the speed of operation of these devices. The unity gain cut-off frequency of a bulk-driven MOSFET can be expressed as: gmb η gm fT, bulk−driven « “ (9.12) 2π (Cbs + Cbsub) 2π (Cbs + Cbsub ) Where η is the ratio of gmb to gm with typical value of 0.2 to 0.4.The other parameters in (9.12) are identical to the standard SPICE parameters for MOSFETs. 9 Low-Power Electronics for Biomedical Sensors 209 a b I in I out I in I in I out W W W W L L L L W L W W W W W 3L L L L L Fig. 9.12 (a) Conventional NMOS cascode structure, (b) improved NMOS cascode with high output voltage swing indicating the aspect ratios of the MOSFETs. An additional current branch is needed in (b) to properly set the bias Thus the unity gain cut-off frequencies of the gate- and the bulk-driven MOSFETs can be related by the following expression, η fT, bulk−driven « fT, gate−driven (9.13) 3.8 Equation (9.13) indicates that the maximum operating frequency of the bulk-driven MOSFET is about one decade less than that of gate-driven MOSFET. Another disadvantage of the bulk-driven MOSFETs is larger mismatch of these devices. In addition, their noise performance is also inferior to their gate-driven counterparts, primarily due to the following reasons: (a) the channel noise current to the input of the bulk-driven device has a larger gain factor compared to the gate-driven one and (b) the bulk sheet resistance of the bulk-driven MOSFET can generate additional thermal noise. 9.5.4 Self-Cascode Technique To some extent, the self-cascode technique can be considered another low voltage supply technique, similar to the bulk-driven technique. As the feature size shrinks, the output impedance of the MOSFET is also becoming smaller because of channel length modulation [49]. Cascode structure is usually employed to enhance the output impedance to achieve higher gain. However, the conventional cascode structure is not suitable for low voltage/power application due to either the reduced output swing or the need for additional biasing current. Figure 9.12 shows two commonly used cascode structures. 210 S.K. Islam et al. Fig. 9.13 (a) Self cascode a b structure and (b) its D equivalent composite transistor M2 W D m L G G M3 W L M1 S S Self-cascode technique shown in Fig. 9.13a is developed to maintain a good output swing without requiring any additional biasing there by making this scheme a potentially good candidate for low voltage design. In this configuration, usually M2 has an aspect ratio of m times of that of M1 i.e., (W/L)2 “ m (W/L)1 (usually for optimal operation, m is set much larger than 1). Under this scenario, these two transistors can be considered as a composite transistor M3 as shown in Fig. 9.13b. This new transistor has much larger effective channel length while having a much lower effective output conductance (which results in much higher output resistance) [50]. Then, the effective transconductance of M3 can be expressed as: 1 gm3, effective “ gm2 “ gm1 (9.14) m The current flowing through M1, M2 or M3 can be expressed as, IDM1, M2, M3 “ βM3 (Vin − Vth )2 /2 (9.15) where, βM3 “ βM1 βM2 /(βM1 + βM2 ) and β is the transconductance parameter of a MOSFET. Besides the high output resistance, another good characteristic of the self-cascode structure is that there is very little VDSsat change of M3 compared with typical transistors due to the small VDS of M1. In other words, the output swing is as high as that with a single NMOS transistor. Therefore, the self-cascode structure has potential for use in low-voltage design. Besides the applications in current mirrors and amplifiers, the self-cascode technique can also be used in high frequency circuits. A low voltage self-cascode voltage controlled oscillator (VCO) as shown in Fig. 9.14 has been reported by Haider et al. [51]. Note that bulk terminals of the P-MOSFETs M1 and M2 are connected to another voltage bias Vsub to reduce the threshold voltages. 9 Low-Power Electronics for Biomedical Sensors 211 VSUB VDD VSUB Self-cascode cross-coupled structure C2 R R C2 M1 M1 C1 M2 M2 C1 Vc Cv Cv L L Fig. 9.14 A self-cascode differential VCO for high frequency application [51] 9.5.5 Floating Gate Technique Floating gate MOSFETs have been typically used for digital memory circuits such as EPROM or EEPROM for several years. This technique has been widely used in a number of low-power analog circuit applications such as CMOS analog trimming circuit [52], multipliers in neural network [53], digital-to-analog converters [54] and amplifiers [55–57]. Unlike conventional MOSFETs, the floating gate voltage VFG in a floating gate MOSFET is controlled by the control gates through capacitive coupling. Figure 9.15 shows a simple layout and circuit symbol of a multi-input floating gate MOSFET. The gate of the device (Poly I) is normally floating with an electrical charge residing on it. The discharging rate of the gate is very slow due to the good insulation properties of SiO2 . Usually the charge can stay for several years with less than 2% variation at room temperature [58]. From (c), the floating-gate voltage can be expressed as: n VFG “ (QFG + CFG,DVD + CFG,SVS + CFG,BVB + ∑ CGiVGi )/CΣ (9.16) i“1 where, QFG is the static charge on the floating-gate, and CΣ “ (CFG,D + CFG,S + n CFG,B + ∑ CGi ) is the total capacitance seen at the floating gate. CFG,D ,CFG,S and i“1 CFG,B are the capacitances between drain, source and bulk, respectively; while CGi is the capacitance between floating gate and control gates. 212 S.K. Islam et al. a b c metal poly II CFGD C G1 poly I D VG1 VG1 VG2 CG2 VG2 VG1 B VG2 CGn VGn VGn VGn CFGS S S D CFGB N diffusion Fig. 9.15 A typical floating gate N-MOSFET (a) layout, (b) schematic symbol, and (c) equivalent circuit with parasitic capacitance noted [58] For a two-input gate-floating MOSFET, when the signal voltage Vs is applied to gate #1, another bias voltage VB is applied to gate #2. Usually VB is higher than Vs , therefore, the threshold of the floating gate MOSFET will adjust to a new threshold voltage Vth as follows: Vth “ (Vthi − VBk2 )/k1 (9.17) where k1 “ CG1 /CΣ ,k2 “ CG2 /CΣ and Vthi is the initial value of the threshold voltage. Therefore, one can achieve lower value of Vth than Vthi by appropriate selection of VB , k1 , and k2 values. Lower threshold voltage makes the circuit feasible for oper- ating with lower supply voltage. However, the technique has several disadvantages. If the transconductance seen from the floating gate is gm,FG , then the equivalent transconductance of this 2-gate MOSFET will be gm,equivalent “ k1 gm,FG , which is degraded by a factor of k1 . Besides, the floating gate voltage VFG is dependent on the drain voltage due to the parasicitic CGD and as a result the output impedance is also less than that of a normal MOSFET operating under the same biasing condition. The small-signal output resistance can be expressed by: CΣ ro,FG “ ro // (9.18) CGD gm where, ro ,CGD and gm are the small-signal output resistance, gate-drain capacitance and transconductance of the MOSFET. Figure 9.16 shows the typical configurations for current mirror and differential pair with floating-gate devices. One of the excellent properties of floating gate MOSFET is that the electric charge in the floating gate terminal can stay for several years with a variation of less than 2% at room temperature. As a result this type of device has been widely used for EPROM applications. The static charge in the floating gate terminal can be changed by: (a) illumination under ultra-violet light, (b) hot electron injection, or (b) Fowler-Nordheim (FN) tunneling. 9 Low-Power Electronics for Biomedical Sensors 213 a b Iin Iout IDSS IDSS Vi+ Vb Vi- Vb Itail Fig. 9.16 Typical configurations of (a) current mirror, (b) differential pair with two-input gate- floating N-MOSFETs 9.6 Signal Processing The signal generated from sensors needs to be processed and the information generated from the measured quantities must be transformed to the format that can be easily read or transmitted out wirelessly. The sensors output signal can be in the format of current or voltage. In the former case an array of sensors can help generate higher current. In the latter case when the voltage amplitude of the generated signal is low then it is required to have a low noise amplifier in the first stage of amplifier to amplify the signal and then convert it to other formats. In this section a nerve signal amplifier is introduced as an example of low level voltage signal processing. An example of current signal processing using a three electrode potentiostat is also introduced. 9.6.1 Neural Systems Signal Processing Development of new methods to understand human brain has been of great interest for a long time. Neuroscientists and IC designers are collaborating to understand human brains using brain-computer interface (BCI). These studies have led to the development of low-power, light-weight implantable wireless sensors which can transfer information to the external devices. This technology can help people with severe motor disability (e.g., due to cerebral palsy) by using their brain data and sending them to the relevant muscle. Designing neural interfaces is a very challenging task. The first gain amplifier has to provide low-noise amplification for the very small nerve signals (up to 500 µV [59]) while keeping the power consumption as low as possible. The system also needs to process the data fast enough for real time analysis and monitoring [60]. 214 S.K. Islam et al. Fig. 9.17 Schematic of a C2 neural amplifier M3 M4 C1 C1 gm C2 M2 CL M1 R.R. Harrison et al. proposed a neural amplifier [59] as shown in Fig. 9.17. The OTA used in this structure is the same as the one shown in Fig. 9.7. The midband gain (Am ) of this system is set by C1/C2 and for OTA transconductance of gm the bandwidth is gm /AmCL . In order to achieve the lowest input noise while providing the minimum of power for the OTA, this circuit is using the sub-threshold technique described earlier. As discussed before in (9.9), the thermal noise of this amplifier can be minimized by choosing the gm of M3 , M5 and M7 much lower than the gm of M1 and M2 , which means: (W/L)3 , (W/L)5 , (W/L)7 ≪ (W/L)1 and (W/L)2 . The transistors M1 and M2 are biased in sub-threshold regime, while M3 , M5 and M7 are biased in strong inversion. Based on (9.8) the large sizing of the transistors M1 and M2 which are biased in W.I. also helps decreasing the flicker noise. The total input noise of the structure shown in Fig. 9.17 is defined to be [59]: 2 C1 + C2 + Cin v2ni,amp “ v2ni (9.19) C1 In this structure the noised efficiency factor (NEF) is calculated to be [59]: c 2Itot NEF “ Vni,rms (9.20) π .UT .4kT.BW That can be reduced to [59]: d 4 ID1 NEF “ (9.21) κ UT gm1 By biasing the transistors in sub-threshold regime, the NEF can be derived to be [59]: c 4 NEF “ – 2.9 (9.22) κ2 9 Low-Power Electronics for Biomedical Sensors 215 Fig. 9.18 A conceptual drawing of a three-electrode Vref potentiostat IF M1 IF Solution WE RE CE Fig. 9.19 A potentiostat with a current mirror to convert the WE current in to the voltage RE CE R Vout V ref M1 M2 M3 9.6.2 Current Signal Processing in Potentiostats An example of current signal processing using a three-electrode potentiostat is shown in Fig. 9.18 [61]. This potentiostat consists of three electrodes: working electrode (WE), counter electrode (CE) and reference electrode (RE). To measure the physical parameters such as glucose, lactate, CO2 and pH, a constant difference potential should be provided across RE and WE. Based on the concentration of the analyte solution, the applied voltage across these electrodes can initiate chemical reaction which generates electrons that can be collected in CE. The collected current from this electrode needs to be processed using a signal processing unit. A current mirror is used to generate a copy of the current collected by CE. The mirrored current generates a voltage across the resistor R which is proportional to the generated current [60]. This is shown schematically in Fig. 9.19. Another type of signal processing unit implemented using a capacitor for the mirrored current as shown in Fig. 9.20 [62, 63]. In this case the generated voltage across the capacitor is the integral of the current that passes through this capacitor. In this structure a switch is used in parallel with the capacitor to discharge the capacitor when the capacitor voltage reaches the reference voltage of the comparator. A comparator is employed to compare the capacitor voltage with the reference voltage and if it exceeds the reference voltage the comparator output generates a signal that can turn this switch on and discharge the capacitor. Higher values of current 216 S.K. Islam et al. Fig. 9.20 Using capacitor in the pass of sensor current for M2 Vref generating pulses with frequency proportional to the CF sensor current Vref IF M1 IF Solution WE RE CE can charge the capacitor faster resulting is higher frequencies of pulse signal generated at the output of the comparator. Similarly, for lower level of current this frequency decreases. Therefore the frequency of comparator output signal contains the information on the magnitude of the sensor current. 9.7 Power-Conditioning Modules in Sensor Electronics Battery is usually used in portable electronics for power supply. But it is not very convenient to replace it frequently, particularly for applications in health monitoring involving implanted sensors. Therefore, some other alternative power supplies are studies and developed recently [64, 65]. For example, photovoltaic cells are frequently used for applications with access to the light source. Typical photovoltaic cell can provide up to several to tens of milli-watts (mW) of power. The embedded electronics in RFID tags use the electromagnetic fields as its energy source, which can provide on the order of mW of power. Other sources include piezoelectric, thermal or other forms of harvested energy [66]. These sources usually cannot be directly used for electronic circuits. For example, the electromagnetic waves usually represent low-amplitude time-varying signals which may not be sufficient to power the electronic circuits. Even the battery voltage which is usually a relatively stable DC signal degrades with long term use. Therefore, an additional power-conditioning module is usually needed between these power sources and the electronic circuits. Figure 9.21 shows a typical power-conditioning module for integrated system with power source consisting of an inductive link [64]. Rectifier is used to convert the time-varying signal to a stabile DC signal. For some applications, additional blocks such as the voltage multiplier may be needed as well. To regulate this DC signal furthermore and provide desired DC voltage level, a voltage regulator is also needed. A low drop-out (LDO) voltage regulator is usually employed more frequently than the other regulator structures in integrated circuits as it usually requires a much lower minimum drop-out voltage than the others. The voltage difference, so called drop-out voltage, defines the efficiency of the voltage regulator. Figure 9.22 shows the typical schematic of a LDO regulator. 9 Low-Power Electronics for Biomedical Sensors 217 Inductive Voltage Power Rectifier Load Regulator Link Power Conditioning Module Fig. 9.21 Typical power-conditioning module for systems with inductive link power Vinfrom the power source or the rectifier Vref Bandgap Pass A1 Element Vout Error Amplifier R1 CL Load R2 Fig. 9.22 Schematic of a LDO regulator The circuit consists of: (1) a bandgap voltage reference, (2) an error amplifier, (3) a pass element, and (4) a voltage divider. The bandgap outputs a very stable DC voltage, Vref , which is immune to supply and temperature variation, but it cannot directly drive the load. The error amplifier A1 is used to monitor the changes in the output voltage and to generate a drive voltage for the pass element to adjust the current with a negative feedback scheme to stabilize the output voltage. A conventional operational amplifier can be employed as the error amplifier. The pass element typically employs a MOSFET or a composite structure to provide the output stage for the load. Usually the transistor size is large to handle the required output current. Besides, it is also very important in terms of frequency compensation for the entire negative feedback loop. A voltage divider can be designed to obtain the desired output voltage. From the schematic, one can easily derive the output voltage expression: R1 Vout “ Vref 1 + (9.23) R2 218 S.K. Islam et al. 9.8 Summary The advancements in IC processing and sensing techniques in the last few decades have made the widespread use of sensor techniques possible in modern biomedical applications. The high degree of miniaturization now possible for the classical measurement techniques has led to the realization of complex analytical systems, including sensors that are known as “BioChem Lab-on-a-Chip”. The latest devel- opments in micro/nano-technology have contributed to a wider range of medical applications. This chapter has been particularly focused on biomedical applications that can be benefited from the use of sensor techniques. Low-power circuit design, low-power signal-processing schemes and power-conditioning circuits for imple- mentation of implantable biosensors have also been presented in this chapter. It is expected that this chapter will give the reader at least a fundamental understanding of the challenge associated with the design of biomedical sensors and of low-voltage low-power sensor electronics in this deep sub-micron CMOS era. References 1. Wang J (2008) Electrochemical glucose biosensors. Chem Rev 108:814–825 2. Islam AB, Islam SK, Rahman T (Dec. 2009) A Vertically Aligned Carbon Nanofiber (VACNF) based amperometric glucose sensor, Proceedings of the International Semiconductor Device Research Symposium (ISDRS 2009),College Park, MD, USA 3. Zhang M, Haider MR, Huque MA, Adeeb MA, Rahman S, Islam SK (Mar. 2007) A low- power sensor signal processing circuit for implantable biosensor applications. Smart Mater Struct 16:525–530 4. Baker DA, Gough DA (1995) A continuous, implantable lactate sensor. Anal Chem 67(9):1536–1540 5. Jeevarajan AS, Vani S, Taylor TD, Anderson MM (2002) Continuous pH monitoring in a perfused bioreactor system using an optical pH sensor. Biotechnol Bioeng 78(4):467–472 6. Star A, Han T-R, Joshi V, Gabriel J-C, Gruner G (Nov. 2004) Nanoelectronics carbon dioxide sensors. Adv Mater 16(22):2049–2052 7. Liu W, Vichienchom K, Clements M, DeMarco S, Hughes C, McGucken E, Humayun MS, Juan E, Weiland JD, Greenberg R (2000) A neuro-stimulus chip with telemetry unit for retinal prosthetic device. IEEE J Solid State Circ 35:1487–1497 8. Zierhofer CM, Hochmair-Desoyer IJ, Hochmair ES (1995) Electronic design of a cochlear implant for multichannel high-rate pulsatile stimulation strategies. IEEE Trans Rehabil Eng 3:112–116 9. Heetderks WJ (1988) RF powering of millimiter- and submillimeter-sized neural prosthetic implants. IEEE Trans Biomed Eng 35:323–327 10. Lenaerts B, Puers R (2007) An inductive power link for a wireless endoscope. Biosens Bioelectron 22:1390–1395 11. Guanying M, Guozheng Y, Xiu H (2007) Power transmission for gastrointestinal microsystems using inductive coupling. Physiol Meas 28:N9-N18 12. Sarpeshkar R (2010) Ultra low power bioelectronics: fundamentals, biomedical applications, and bio-inspired systems Cambridge University Press edition 1 Feb 22 13. Mandal S, Zhak S, Sarpeshkar R (2009) A bio-inspired active radio-frequency silicon cochlea. IEEE J Solid State Circ 44(6):1814–1828 9 Low-Power Electronics for Biomedical Sensors 219 14. Wee KH Turicchia L, Sarpeshkar R (2008) An analog integrated-circuit vocal tract. IEEE Transactions on Biomedical Circuits and Systems 2(4):316–327 15. Yang H, Sarpeshkar R (2006) A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications. IEEE Trans Circ Syst I 53(11):2349–2356 16. Grayson ACR, Shawgo RS, Johnson AM, Flynn NT, Yawen LI, Cima MJ, Langer R (Jan. 2004) A BioMEMS review: MEMS technology for physiologically integrated devices. Proceedings of the IEEE 92(1):6–21 17. Salwa Mostafa, Ida Lee, Syed K. Islam, Sazia A. Eliza, Gajendra Shekhawat, Vinayak P. Dravid, Fahmida S. (2011) Tulip, integrated MOSFET-embedded cantilever based biosensor characteristic for detection of anthrax simulant. IEEE Electron Dev Lett 32(2):408–410 18. Abdel-Aty-Zohdy HS (2008) Bio-inspired adaptive integrated information processing, IEEE National Aerospace and Electronics Conference (NAECON) 114–122 19. Milenkovic A, Otto C, Jovanov E (2006) Wireless sensor networks for personal health monitoring: issues and an implementation. Comput Comm 29:2521–2533 20. Joseph D (ed) (2000) In: handbook The biomedical engineering. CRC Press, Bronzino 21. Top targets for wireless health and mhealth. available online at https://www. wirelesshealthstrategies.com/targets.html 22. Daniel Mark, Stefan Haeberle, G¨unter Roth, Felix von Stetten, Roland Zengerle (2010) Microfluidic lab-on-a-chip platforms: requirements, characteristics and applications Chem Soc Rev 39:1153–1182 23. Wang J (2001) Glucose biosensors: 40 years of advances and challenges Electroanalysis 13:983–988 24. Elliot McGucken (1998) Multiple unit artificial retina chipset to aid the visually impaired and enhanced holed-emitter CMOS phototransistors. Ph. D. Dissertation, University of North Carolina at Chapel Hill 25. Schwiebert L, Gupta SKS and Weinmann J (2001) Research challenges in wireless networks of biomedical sensors, ACM, New York, USA 26. National diabetes statistics available online at http://diabetes.niddk.nih.gov/dm/pubs/statistics/ index.aspx#Diagnosed20 27. Organ procurement and transplantation network available online at http://optn.transplant.hrsa. gov/latestData/rptData.asp 28. Cancer facts and figures (2011) available online at http://www.cancer.org/acs/groups/content/ @epidemiologysurveilance/documents/document/acspc-029771.pdf 29. Serdijn WA, Van Der Woerd AC, Roermund AHM, Davidse J (1995) Design principles for low- voltage low-power analog integrated circuits. Analog Integrated Circuits and Signal Processing 8:115–120 30. Nordholt EH (1983) Design of high-performance negative-feedback amplifier. Elsevier, Ams- terdam 31. Toumazou C, Lidgey FJ, Haigh DW (1990) Analogue IC design: the current-mode approach, Peter Peregrinus, London 32. Toumazou C, Hughes JB, Banersby NC (1993) Switched currents. An analogue technique for digital technology, Peter Peregrinus, London 33. Toumazou C, Battersby NC (May 1993) Switched-transcondcutance techniques: a new approach for tunable precision analogue sample-data signal processing. Proc IEEE ISCAS, Chicago 34. Bult K, Geelen GJGM (Dec. 1990) A fast-settling CMOS Opamp for SC circuits with 90- dB DC gain. IEEE J Solid State Circ 25(6):1379–1384 35. You F (1996) Low voltage analog circuit design. Ph. D. thesis, Texas A&M University, College Station, TX 77843, USA 36. Laker KR, Sansen WMC (1994) Design of analog integrated circuits and systems, McGraw- Hill. Inc., New York 37. Eschauzier RGH and Huijsing JH (1995) Frequency compensation techniques for low-power operational amplifiers,Kluwer MA, Boston 220 S.K. Islam et al. 38. Iwai H (March 1999) CMOS technology - year 2010 and beyond, IEEE J Solid State Circ 34(3):357–366 39. Li EH and Ng HC (Nov. 1991) Parameter sensitivity of narrow channel MOSFET’s, IEEE Electron Dev Lett 12(11):608–610 40. Yan S, Sanchez-Sinencio E (Feb. 2000) Low voltage analog circuit design techniques: a tutorial, invited paper in IEICE Trans Analog Integr Circ and Syst E00-A(2):1–17 41. Chee YH (2006) Ultra low power transmitter for wireless sensor networks. Ph. D. Dissertation, Dept of Electrical Engineering and Computer Science, University of California, Berkeley, Spring 42. Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr Circ Sig Process 8:83–114 43. Binkley DM, Blalock BJ, Rochelle JM (2006) Optimizing drain current, inversion level, and channel length in analog CMOS design. Analog Integr Circ Sig Process 47:137–163 44. Holleman J, Zhang F, Otis B (2011) Ultra low power circuit design for wireless neural interfaces Springer, New York 45. Harrison RR, Charles C (Jun 2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid State Circ 38(6):8 46. Guzinski A, Bialko M, Matheau JC (Sep 1987) Body driven differential amplifier for application in continuous time active-C filter. Proceedings of the European Conference on Circuit Theory and Design (ECCTD’87) 315–320 Paris, France 47. Blalock BJ, Allen PE, Rincon-Mora GAR (July 1998) Designing 1-V Op amps using standard digital CMOS technology IEEE Trans Circ Syst II 45:769–780 48. Chatterjee S, Tsividis Y, Kinget P (Sep 2004) A 0.5-V bulk-input fully differential operational transconductance amplifier Proceedings of the 30th European Solid-State Circuits Conference 147–150 Leuven, Belgium 49. Gray PR and Meyer RG (1984) Analysis and design of analog integratedcircuits. EWiley, New York 50. Rodr’iguez-V’azquez A and S’anchez-Sinencio E (eds) (Nov 1995) Special issue on low- voltage and low power analog and mixed-signal circuits and systems. IEEE Trans Circ Syst 42(11):825 51. Haider MR, Zhu K, Islam SK, Yuan S and Mahfouz M (2011) Phase noise optimization of a selfcascode VCO by changing the capacitor ratio and substrate bias. IEEE Radio and Wireless Symposium, Jan 52. Sackinger E, Guggenbuhl W (Dec. 1988) An analog trimming circuit based on a floating-gate device. IEEE J Solid State Circ 23(6):1437–1440 53. Mehrvarz HR, Kwok CY (Aug. 1996) A novel multi-input floating-gate MOS four-quadrant analog multiplier, IEEE J Solid State Circ 31(8):1123–1131 54. Yin L, Embabi SHK, S’anchez-Sinencio E (1997) A floating gate MOSFET D/A converter IEEE Proc ISCAS’97 1:409–412 55. Thomsen A and Brooke MA (Jan. 1993) A programmable piecewise linear large-signal CMOS amplifier, IEEE J Solid State Circ 28(1):84–89 56. Yu C-G and Geiger RL (1993) Very low voltage operational amplifier using floating gate MOSFETs, IEEE Proc ISCAS’93 2:1152–1155 57. Ramirez-Angulo J, Choi SC, Gonzalez-Altamirano G (Nov. 1995) Low-voltage circuits build- ing blocks using multiple-input floating-gate transistors. IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications 42(11):971–974 58. Yan S and Sanchez-Sinencio E (Feb. 2000) Low voltage analog circuit design techniques: a tutorial, IEICE Transactions on Analog Integrated Circuits and Systems E00-A (2): 1–17 59. Harrison RR, Charles C (Jun 2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid State Circ 38(6):958–965 60. Holleman J, Zhang F, Otis B (2011) Ultra low power circuit design for wireless neural interfaces. Springer, New York 9 Low-Power Electronics for Biomedical Sensors 221 61. Ahmadi MM, Jullien GA (July 2009) Current-mirror-based potentiostats for three-electrode amperometric electrochemical sensors. IEEE Trans Circ Syst 56(7):1339–1348 62. Hasan SMR (May 2007) Stability analysis and novel compensation of CMOS current-feedback potentiostat circuit for electrochemical sensors. IEEE Sensors Journal 7(5):814–824 63. Narula HS, Harris JG (April 2006) A time-based VLSI potentiostat for ion current measure- ments. IEEE Sensors Journal 6(2):239–247 64. Islam SK and Haider MR (2010) Sensors and low power signal processing. Springer, New York 65. Williams CB and R.B. Yates (June 1995) Analysis of a micro-electric generator for microsys- tems The 8th international conference on solid-state sensors and actuators. Stockholm, Sweden 66. Wu GH, Datar RH, Hansen KM, Thundat T, Cote RJ, Majumdar A (2001) Bioassay of prostate- specific antigen (PSA) using microcantilever Nat Biotechnol 19:856–60 Chapter 10 Sensor Conditioning Circuits∗ Julia Hsin-Lin Lu and Byunghoo Jung 10.1 Introduction Analog sensors produces a variation in an electrical property to show a change in the environment. The analog variation in electrical property needs a conditioning circuit to indicate the change before conversion into digital signal. The electrical properties most commonly detected by analog sensors are voltage, current, capacitance, resistance, and charge. Real-time capacitive and resistive sensors are used in a wide range of physical measurement systems. Detection of a small capacitance or resistance change is widely demanded in industrial process control systems and medical instrumentations [2]. Currently, there is an increasing demand for a compact mobile system that can be equipped with various types of sensors. As shown in Fig. 10.1, a cellular handset that is compatible with different types of health monitoring or environment sensors, combining with the wireless connectivity of the cellular system, the real-time collected data through the sensors can be maximally exploited. Since every sensor has its own requirements for readout and every user has their own applications that require different types of sensors, a reconfigurable low-power universal sensor interface is crucial for successful implementation. The compatibility with various disposable health monitoring sensors is particularly important since the cost of the disposable unit can be reduced by simplifying interconnect requirements between the readout and sensors. In most of these ∗ Portions of this manuscript and material referred in this manuscript have appeared in [1]. J.H.-L. Lu () Purdue University, West Lafayette, IN 47907, USA e-mail: [email protected] B. Jung Purdue University, West Lafayette, IN 47907, USA e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 223 DOI 10.1007/978-1-4614-1383-7 10, © Springer Science+Business Media New York 2013 224 J.H.-L. Lu and B. Jung Fig. 10.1 Application example of universal sensor interface Fig. 10.2 Traditional method to obtain digital output Fig. 10.3 Alternative method to obtain digital output applications, a physical quantity is converted into a capacitance or resistance change, and a readout circuit converts various capacitance or resistance changes into digital or analog electrical signals. 10.2 Analog and Semi-digital Sensor Conditioning Circuits The available types of sensor readouts can be broadly classified into analog and semi-digital. Traditionally, the digitized outputs were obtained by employing analog sensor readout signals followed by analog-to-digital converters (ADC), as shown in Fig. 10.2. This topology, which uses an ADC, not only increases the complexity and power consumption but also introduces extra noise. In order to address these issues, semi-digital solutions such as pulse-frequency modulation (PFM) [3] or pulse-width modulation (PWM) [4] have been investigated. These kind of readouts represent analog quantities using only digitized signal levels. This is achieved by encoding the information in the time or frequency domain, rather than the analog voltage or current domain as in analog readouts. This topology is shown in Fig. 10.3. Its rail- to-rail voltage swing also provide the advantage of robustness against environment noise. This alternative method eliminates the traditional ADC and reduces the power consumption significantly. In addition, the dynamic range in semi-digital readouts 10 Sensor Conditioning Circuits 225 is not limited by the supply voltage or current. This is in sharp contrast to the analog readout. Furthermore, the semi-digital output provides robustness against environmental noise due to its digital two-level nature. 10.3 Capacitive Sensor Conditioning Circuits Detecting physical variation through capacitance sensing is one of the most common approach in a wide variety of physical measurement systems, such as liquid- level gauges, pressure meters, rotor displacement in integrated accelerometers, and MEMS-based sensors, etc. MEMS has favored the development of capacitive sensors for their compatibility to be integrated on silicon substrates, using slightly modified standard microelectronic processes [5]. In these systems a physical quantity is converted into a capacitance change. Next, the capacitance change is converted into a digital signal using a sensor interface. To minimize the parasitic capacitance of packaging, the readout conditioning circuits have to be integrated with the sensors, either on the same integrated circuit chip or inside the same package. Some integrated capacitance sensors produce analog output for imple- menting simple functions such as producing an alarming signal when the sensing capacitance is higher than a threshold or be included in part of an all-analog systems. Capacitance-to-voltage conversion can be performed using impedance metering circuits or switched capacitor charge amplifiers [4]. A capacitive Wheatstone-bridge can also be used to convert its impedance, at a specific frequency, to a voltage for conditioning a capacitive sensor. A digital output is desirable when the sensors have to be connected to a low- cost microcontroller with only digital inputs or when the sensor is placed in a remote position in the harsh environment with high electromagnetic noise. The digital output is generally obtained by first producing an analog output and then converting it to digital. Existing semi-digital readouts can be classified into several categories. For a capacitive sensor readout, the first is the capacitance-to-frequency (PFM) [6–8] or capacitance-to-phase [9]. Oscillator-based circuits can be used to produce a variation in oscillating frequency as a function of capacitance. The second type of semi-digital readout, called capacitance-to-time or pulse-width modulation (PWM), provides smaller measurement time compared to PFM. In addition, in contrast to PFM, PWM designs have higher bandwidth and can facilitate the reading procedure by purposely adopting synchronization to the microcontroller [10]. PWM signals can be easily digitized using a digital decimating filter. A current-mode, dual-slope, capacitance-to-pulse duration converter that shows low sensitivity to parasitic capacitance and temperature has been proposed [4]. RC decay could be utilized for conditioning a capacitive sensor. The charging or discharging time it takes for the voltage to reach a threshold is a measure of the capacitance. Single or dual slope integrating detector can also be implemented to integrate a current and measure the elapsed time to reach a voltage threshold. 226 J.H.-L. Lu and B. Jung 10.4 Resistive Sensor Conditioning Circuits Resistive gas sensors and metal-oxide (MOX) sensors show a high baseline resistance on the order of giga-Ohms and a wide dynamic range. Electronic noses often use different gas sensors, and a conditioning readout circuit working for a very wide range is compatible to guarantee enough resolution [11]. Resistance-to-voltage conversion strategy can be used for conditioning the resistive sensor. With a simple voltage divider or a resistive Wheatstone bridge, the change in resistance can be converted to a change in voltage. For a resistive sensor readout, there are also two popular semi-digital con- ditioning methods which are resistance-to-frequency [12] and resistance-to-time conversions. Oscillating circuits that perform resistance-to-time conversion are considered to be one of the best solutions since high resistive changes can be measured without using picoammeters or scaling factors [11]. Resistive-to- frequency conditioning readout with frequency output offers several advantages compared to resistive-to-voltage or resistive-to-current with voltage or current output conditioners such as robustness against environment noise and ease of multiplexing and signal processing. RC decay could be utilized for conditioning a resistive sensor. The charging or discharging time it takes for the voltage to reach a threshold measures the resistance change. The design in [4] uses analog amplifiers including integrators and OTA to integrate a current. This wide-range timing measurements such as in frequency, period, duty cycles are compatible to several low-cost microcontroller which support a timing processing unit for input capture. 10.5 Design of an Universal Sensor Readout Circuit In this chapter, a low-power, low complexity, and wide-dynamic-range universal sensor readout circuit that converts the sensing capacitance or resistance changes to digital duty cycles based on pulse-width modulation (PWM) is introduced [1]. The functionality of the full circuit, including circuit analysis, and noise analysis are discussed. 10.5.1 Principle of Operation The block diagram of the basic sensor readout circuit and two sensor configuration examples are shown in Fig. 10.4. In this universal design, a capacitive sensor uses a resistive reference, and a resistive sensor uses a capacitive reference. The circuit operates as follows. First, most of the electronic contains an oscillator, for example a crystal oscillator, providing a clock signal of frequency fcrys . 10 Sensor Conditioning Circuits 227 Fig. 10.4 The block diagram of resistive and capacitive sensor readout configurations Fig. 10.5 Ideal response of the basic sensor readout Assuming the input impedance of the comparators is large and the input clock transits quickly, a simple capacitance charging and discharging model can be utilized to analyze the behavior of the circuit during the low and high portion of the input clock. The ideal response of the circuit without a reset block is shown in Fig. 10.5. Neglecting the delay of the comparators, which does not impact the circuit response assuming both comparators have identical delay, we observe that the waveform on O1 is equal to V 1 and depending on the excitation signal transition, node V 2 either charges or discharges with an RC time constant. In this design, the switching threshold of the comparator is set to 0.5VDD . The outputs of the 228 J.H.-L. Lu and B. Jung comparators are fed into an XOR gate, which operates as a phase detector. The output pulse width is linearly proportional to the charging time constant at node V 2. A digital decimation filter can be used to finally measure the pulse width of the output signal from the phase detector. To understand the ideal sensing range of the basic readout design, we first illustrate the exponential charging and discharging behavior of the capacitor. Defining τ “ RC, Vi the initial voltage and V f the final voltage, we can express the voltage of the capacitor at any time t as: Vcharge “ V f · (1 − e−t/τ ) (10.1) Vdischarge “ Vi · e−t/τ . (10.2) If we set the comparator threshold voltage Vcomp to a percentage of the supply voltage, say α VDD where α is a constant smaller than 1, substituting Vcharge “ α VDD and V f “ VDD into (10.1) and solving for t, we obtain the pulse width Tpw : 1 Tpw “ t “ RC · ln . (10.3) 1−α Equation (10.3) shows that the output pulse width is linearly proportional to the sensing capacitance or resistance value. Contrary to other designs that use analog integrators to achieve the linearity between input and output [4], we use a purely CMOS circuit. The maximum detectable capacitance and resistance, Cmax and Rmax , correspond to the maximum producible pulse width. To fully utilize the excitation signal period, we can employ an uneven duty cycle, D. Taking into account the pulse produced by the “on” duration of the excitation signal, we can obtain D · Tcrys Cmax “ (10.4) R · ln 1−1α D · Tcrys Rmax “ (10.5) C · ln 1−1α where Tcrys is the period of the excitation signal. The sensing range linearly increases with duty cycle, D, as shown in (10.4) and (10.5). Note that the illustration in Fig. 10.5 assumes that the duty cycle is 50% which allows an equal amount of time to charge and discharge the capacitor. If, for example, we were to increase D to 95%, one can observe that a DC offset is introduced due to the inadequate discharging time. In order to resolve this issue we connect a fast reset switch at node V 2, as illustrated in Fig. 10.4. As shown in Fig. 10.4, the reset block consists of an inverter and a pull-down NMOS transistor. When the reset transistor is triggered by a low excitation signal, it quickly discharges node V 2. Depending on how much time is required to reset the circuit, one can optimize the duty cycle of the excitation signal to achieve the maximum sensing 10 Sensor Conditioning Circuits 229 Fig. 10.6 Ideal response of readout circuit with reset block range. An additional buffer is used to match the delay time of the reset signal. This allows the charging to begin as soon as the reset operation is complete. The response of the readout circuit with the reset block is demonstrated in Fig. 10.6. 10.5.2 Circuit Analysis and Optimization In this section we explore the limitations in sensing range and the performance of the proposed readout circuit. This proposed readout circuit converts the capacitance or resistance into a pulse duration, herein we refer to it as pulse-width modulator (PWM). In the following analysis, we use only the capacitive-sensing configuration for simplicity. The analysis for resistive sensor readout is dual. 10.5.2.1 Maximum Sensing Capacitance According to the operation described in Sect. 10.5.1, we can divide the sensing range limitations into two conditions: one imposed by the “on” duration of the crystal oscillator, which is the charging time, f1 (D); the other imposed by the “off” duration, which is the reset time, f2 (D). Both operations require an adequate amount of time. The first criteria, which is the maximum detectable capacitance limited by the “on” duration of the clock is given by (10.4). On the other hand, the reset criteria is given by Tdis < (1 − D) ·Tcrys , (10.6) 230 J.H.-L. Lu and B. Jung Fig. 10.7 Conceptual behavior of Cmax when we sweep D where Tdis is the time required to discharge node V 2 to ground. As described in Sect. 10.5.1, during the reset operation the discharging time constant at node V 2 can be expressed as τdis “ (ron R) ·C, (10.7) where ron is the on-resistance of the reset transistor. A reasonable assumption for the time for V 2 to discharge to GND is 5τdis . This translates to the following equations: 5(ron R) ·C < (1 − D) ·Tcrys (10.8) (1 − D) ·Tcrys Cmax “ . (10.9) 5 · (ron R) Equation (10.9) shows the limit on the maximum detectable capacitance imposed by the reset operation. Together with (10.4), we can summarize the maximum detectable capacitance as D · Tcrys (1 − D) ·Tcrys Cmax “ min , R · ln2 5 · (ron R) “ min{ f1 (D), f2 (D)}. (10.10) This behavior is conceptually illustrated in Fig. 10.7. Intuitively, the available charging time, f1 (D), increases as D increases, while the available reset time, f2 (D), decreases and vice versa. Dopt can be determined from the intersection of the two functions and represents an optimal duty cycle for Cmax . 10.5.2.2 Effect of Parasitic Capacitance The effective sensing capacitance, Ceff , is dependent on the parasitic capacitance seen by the sensing node V 2. As shown in Sect. 10.5.1, the comparators are implemented with digital inverter circuits. Assuming the channel resistances of M1 and M2 in the comparators, which are biased in deep triode region, are small, we can express Ceff as follows: Ceff « (CPCB + CMOS ) + Cx (10.11) “ C par + Cx . (10.12) 10 Sensor Conditioning Circuits 231 Fig. 10.8 Capacitance dynamic range with different reference resistors where CMOS is the capacitance from MOS devices (CMOS), Cx is the sensing capacitance, and CPCB is the off-chip PCB parasitic capacitance seen by the sensing node V 2. The linearity between the pulse width and sensing capacitance is not affected by the parasitic capacitance. It only introduces a fixed offset proportional to the C par in the pulse width which can be easily calibrated. 10.5.2.3 Reconfigurable Readout Dynamic Range and Sensitivity As a reconfigurable system, for variable capacitance or resistance readout, the sensor interface can perform different dynamic ranges. The factors that limit the minimum sensing values are (a) the comparator slew rate and (b) the dead zone of the phase detector (XOR gate). The comparators implemented by digital inverters have relatively high slew rate, so we focus on (b). The phase detector enters the dead zone when the rising edge of the output pulse is not allowed sufficient time to charge to VDD . If we denote the resistance and capacitance at the XOR output as RXOR and CXOR , respectively, the minimum detectable pulse width Tpw,min is approximately 5RXORCXOR . Thus the minimum sensing resistance and capacitance can be obtained as 5RXORCXOR Rmin – , (10.13) C · ln 1−1 α 5RXORCXOR Cmin – . (10.14) R · ln 1−1 α For the maximum sensing resistance and capacitance, as derived in (10.4) and (10.5), the Rmax and Cmax are inversely proportional to the reference capacitance and resistance. Hence, the readout dynamic ranges defined as Rmax -Rmin and Cmax - Cmin are inversely proportional to the reference values. Figures 10.8 and 10.9 shows the simulated sensing ranges in the face of different reference values. As discussed, 232 J.H.-L. Lu and B. Jung Fig. 10.9 Resistance dynamic range with different reference resistors the sensing range increases with decreasing reference value. The Cmin value does not change because the relatively large parasitic capacitance at the sensing node V 2 generates a detectable pulse even with zero sensor capacitance (Cx “ 0). We define the readout sensitivity as the rate of change of the pulse width versus sensing value. Using (10.3), for α “ 0.5, we can obtain the sensitivities as ∂ Tpw Sens(R) “ “ Cln2 (10.15) ∂ Rx ∂ Tpw Sens(C) “ “ Rln2, (10.16) ∂ Cx The sensitivities are linearly proportional to the reference values. The analysis clearly shows the trade-off between the sensing range and the sensitivity. 10.5.2.4 Circuit Noise and Readout Resolution Noises injected into or generated by the readout circuit limits the sensing resolution. One of the most critical noise sources is flicker noise because most sensor signals occupy frequency bands below the flicker noise corner frequency ( fknee ), which is typically 500-kHz–1-MHz for sub-micron transistors [13]. To mitigate the effect of flicker noise, the proposed readout circuit up-converts the sensor signal to a high sampling frequency, fcrys , using AC excitation in the very beginning before entering the main circuit blocks as shown in Fig. 10.10. The flicker noise issue can be mitigated by properly choosing the excitation frequency ( fcrys ), and we ignore it in the following analysis. The noise generated by the PWM circuit stems from the thermal noises of the resistors and transistors, flicker noise, crystal oscillator jitter and supply noise. Noise introduces jitters in the pulse trailing edge and needs to be modeled in terms of its probability density function. However, we first consider an additive noise voltage, 10 Sensor Conditioning Circuits 233 Fig. 10.10 Conceptual diagram of signal up-conversion operation Fig. 10.11 Conceptual diagram of the additive noise voltage uN , superimposed on the charging curve. Figure 10.11 shows the effect of the noise voltage converted to a pulse width, then converted to a digital number by counting the number of counter clock cycles. As can be seen from Fig. 10.11, the noise can be either constructive (+ uN ) or destructive (−uN ) for simplification. In a noiseless circuit, we can express the time it takes to charge node V 2 to 0.5VDD by visiting the familiar formula: Tpw “ RC · ln2. (10.17) Now suppose we have a destructive noise −uN superimposed on the charging curve. In such a noisy environment, this translates to the original capacitor having to charge to 0.5VDD + uN . We can obtain 0.5VDD + uN “ VDD 1 − e−t/RC . (10.18) Solving for t we can obtain the time it takes to charge to Tpw + δ TN : VDD Tpw + δ TN “ RC · ln . (10.19) 0.5VDD − uN 234 J.H.-L. Lu and B. Jung The step capacitance Δ C that corresponds to the step pulse width from noise, δ TN , is equal to the maximum sensitivity of the circuit to noise with single shot measurement. We therefore determine the Δ C by using the following formulas: Tpw + δ TN “ R(C + Δ C)ln2. (10.20) Equations (10.17) and (10.19) allow us to find δ TN as follows: 0.5VDD δ TN “ RC · ln . (10.21) 0.5VDD − uN Using (10.20) and (10.21) and solving for Δ C we can obtain: VDD Δ C “ C · log2 . (10.22) VDD − 2uN Similarly, a constructive noise would correspond to the noiseless capacitor charging to V − uN . Note that the maximum sensitivity to an injected noise is dependent on the base sensing capacitance. Larger sensing capacitance has degraded readout resolution because of the high sensitivity to the noise. In the following noise analysis, we assume that the additive noise is a stationary white Gaussian random variable with standard deviation σV . If we denote the noise as un , then it can be expressed as un „ N(0, σV2 ). Thus, the output pulse width Tpw can be expressed as discrete time random processes that depend on noise un . By using (10.17) and (10.19), assuming y “ ln(0.5VDD − uN ), the variance of jitter, σT2 , can be derived according to the variance of noise voltage, σV2 , as: σT2 “ Var{δ TN } “ R2C2 ·Var {ln(0.5VDD − uN )} ⎧ ⎨ ∞ −(0.5VDD −ey )2 2 2 2 b 1 y 2σV2 “RC · y · ·e ·e dy ⎩ −∞ 2πσ 2 V ⎡ ⎤2 ⎫ ∞ −(0.5−ey )2 ⎪ 1 2σV2 ⎬ −⎣ y· b · ey · e dy ⎦ . (10.23) −∞ 2πσV 2 ⎪ ⎭ A less accurate, but more intuitive equation for the variance of jitter can be derived using the equation derived in [14, 15], σV σT “ , (10.24) S 10 Sensor Conditioning Circuits 235 where S is the slew rate of the signal. Since the charging curve is not linear, the slope is not constant along the curve. Using (10.1), we can derive the slope at the moment when node V 2 reaches α VDD as: dV 2 VDD − t |V 2@αVDD “ e RC |t “RCln( 1 ) dt RC 1−α VDD − RCln( 1−α ) 1 “ e RC RC VDD “ (1 − α ), (10.25) RC so the relationship between the σT and σV can be obtained as RC σT « · σV , (10.26) VDD (1 − α ) which shows the same trend as the result derived in (10.23). The standard deviation of jitter is linearly proportional to the sensing capacitance and resistance values. Assuming Gaussian distribution, the root mean square (RMS) jitter, Jitter rms , can be obtained directly by Jitterrms “ σT . (10.27) In this design, we choose Vcomp “ 0.5VDD (α “ 0.5) for the comparator. Since the pulse width is determined by the time when RC charging curve reaches Vcharge “ α VDD , we can find out the relationship between the jitter and α from (10.26). Since the slope of the RC charging curve decreases with increasing α , smaller α provides better sensing resolution at the cost of sensing range. Assuming there is no jitter from the external crystal oscillator clock source, then the rising edge is only affected by the noise from the comparator and XOR circuit. Since the comparator and XOR are implemented using CMOS logic, which has high slew-rate digital signal, the jitter at the rising edge of output pulse signal is less significant. The falling edge becomes jittery due to the noise from the power supply, the noise from the external resistor, and the noise from the comparator and XOR. Assuming jitter generation refers to the jitter produced by the sensor readout circuit itself when the input clock signal contains no jitter, as shown in Fig. 10.12, the main sources of jitter are as follows: (a) Jitter due to additive noise on the amplitude of the power supply VDD , uN−V DD „ N(0, σN−V 2 DD ). (b) Jitter due to additive noise on the amplitude at the RC charging node from the thermal noise of the external resistor, uN−Rx „ N(0, σN−Rx2 ). (c) Jitter from the electronic noises of its constituent devices in the circuit, uN1 „ N(0, σN1 2 ), uN2 „ N(0, σN2 2 ), and uN3 „ N(0, σN3 ). 2 As shown in Fig. 10.13, each noise source generates σT which contributes to the jitter at the output pulse width. Using (10.26), the jitter, σT −1st , on the output 236 J.H.-L. Lu and B. Jung Fig. 10.12 Conceptual diagram of the noise sources in readout system a b c b Fig. 10.13 Effect of jitter at different stages. (a) Clock signal after the comparator. (b) Signal at the RC charging node. (c) Signal after the comparator. (d) Output signal of the phase detector (XOR) pulse width generated by the additive noise voltages uN−V DD and uN−Rx can be obtained as: b RC σT −1st “ · σN−V 2 DD + σN−Rx 2 VDD (1 − α ) “ (δ TN−V DD + δ TN−Rx )rms . (10.28) 10 Sensor Conditioning Circuits 237 Because of the slowly changing RC charging curves, the σT −1st becomes the dominant jitter which is proportional to the sensing values. For noise sources uN1 , uN2 , and uN3 , we include the transistor channel thermal noise, but neglect the transistor induced gate noise since it is a blue noise and the sensor readout circuit operates at a comparably low frequency band. The jitter added by the comparator and the XOR are uN1 (δ TN1 )rms “ (δ TN2 )rms “ , (10.29) Scomp where Scomp is the slew rate at the output of the comparator. uN3, r uN3, f (δ TN3,r )rms “ ; (δ TN3, f )rms “ , (10.30) SXOR SXOR where SXOR is the slew rate at the output of the XOR. Equations (10.29) and (10.30) show the importance of a high bandwidth com- parator and XOR designs for high resolution because Scomp and SXOR are linearly ? proportional to the circuit bandwidth and uN1 , uN2 , and uN3 are proportional to Δ f . It is also important to note that the falling edge jitter is bigger than the rising edge jitter by δ TN−V DD + δ TN−Rx , and the falling edge jitter is linearly proportional to the sensing and reference values as described by (10.28). Obtaining the jitter, σT,total , generated from the noises, we can estimate the resolution of capacitance and resistance measurements, Cres and Rres , using (10.17) and (10.20) as σT,total Cres “ (10.31) Rln2 σT,total Rres “ . (10.32) Cln2 As described in (10.17) and Sect. 10.5.2.3, the detection range of the universal sensor interface can be reconfigured by changing the reference resistor or capacitor. The PWM output pulse width can be digitized using a digital decimator, such as a counter, to support a fine resolution yet accommodate a wide detection range at the same time. 10.5.2.5 Oversampling The proposed readout is in effect a oversampling system with the crystal oscillator frequency fcrys being the sampling frequency and fsens being the sampled signal frequency. Since the RC charging node is properly reset every clock cycle and the rising edge is defined by the external clock signal from a stable crystal oscillator, there is no cycle-to-cycle jitter propagation problem which is in sharp contrast to the dual-slope integrator based PWM structure[15]. Because of the independent sampling, the measurement accuracy can be improved by taking the sampled 238 J.H.-L. Lu and B. Jung mean of a set of consecutive measurement data. Averaging K samples while their uncorrelated random noises are folded to each sample reduces the noise variance by a factor of K, and hence the signal-to-noise-ratio (SNR) can be improved by a factor of K. This can be described through the following relationship: σX2 σpX2 “ , (10.33) K where K is the number of averaged samples and σ pX2 is the new variation after averaging. In this case, every time we increase the number of samples by a factor of 4, the resolution increases by two times. The maximum number of consecutive data to be averaged is determined by the following relationship fcrys “ Kmax · (2 fsens ), (10.34) where 2 fsens indicates the Nyquist bandwidth of sensing signal. Hence, high fcrys can provide better resolution through averaging a large amount of samples at the cost of increased computational complexity and reduced readout dynamic range as described in (10.4) and (10.5). 10.5.3 Implementation and Measurement Results for the Universal Sensor Readout Circuit The measurement results for the circuit implemented in a 0.13-µm CMOS technol- ogy show a capacitance readout range of 13-aF–10.7-nF and a resistance readout range of 5-Ω–11.5-MΩ with high sensitivity and resolution while drawing only 60-µA from 1-V supply. To check the sensing signal up-conversion operation described in Fig. 10.10, the power spectrum density and phase noise of the output signal is measured with test condition, R “ 3.3-kΩ, C “ 1-pF, fcrys “ 1.5-MHz, and D “ 80%. Figure 10.14 shows the up-converted sensing signal and flicker noise corner frequency around 600-kHz. Figure 10.15 shows the measured jitter on the rising and falling edges of the output pulse signal in the presence of different sensing capacitance values when Rre f “ 2.7-MΩ, fcrys “ 32.768-kHz, and D “ 50%. As described by (10.28), (10.29), and (10.30), the falling edge jitter is bigger than the rising edge jitter and the falling edge jitter is linearly proportional to the sensing capacitance while the rising edge jitter remains constant. Table 10.1 shows performance summary and comparison with previous works. The readout circuit utilizes a RC-controlled pulse generator and produces pulse signals whose duration width is proportional to the charging time. The circuit is comprised of complementary CMOS circuit that enables the proposed design to consume significantly less power, high linearity, and low complexity compared to analog integrator based designs. This significantly low-power design is attractive for 10 Sensor Conditioning Circuits 239 Fig. 10.14 Frequency spectrum measurement Fig. 10.15 RMS jitter on rising and falling edges of the PWM output signal versus sensing capacitance implantable and mobile applications [19–21]. A low-complexity up-conversion process is utilized in order to address flicker noise. Sensor signal is up-converted utilizing AC excitation before it is contaminated by flicker noise. In addition, the example makes an effective use of the pulse period to provide an improvement to 240 Table 10.1 Performance comparison Reference [4] [16] [17] [11] [18] This work[1] Application type Cap Cap Cap Res ,Cap Cap ,Res Cap ,Res Power & VDD 16.5 mW, 3.3V 1.1 mW, 5V 7 mW, 5V 3.5 mW, ±1V 21 mW, 5V 0.06 mW, 1.0V Sensitivity 15 µs/pF @ f ck “ 50 kHz 1.25 mV/fF N/A N/A N/A 7 µs/ pF(R:10 MΩ) 0.5 ns/Ω(C:800 pF) C dynamic range 0.8 pF-1.2 pF 16 fF-40 pF 1 pF-300 pF N/A-47 pF N/A-300 pF 13 aF–10.7 nFb R dynamic range – – – 10 Ω-100 GΩ 25 Ω-10 KΩa 5 Ω-11.5M Ω b Topology PWM Analog PWM R-to-T PWM PWM Area (mm2 ) 0.2 20 2.66 0.845 N/A 0.011 (0.08 with MIMcap) Technology 0.35 µmCMOS 1 µmBiCMOS 0.7 µmCMOS 0.35 µmCMOS N/A 0.13 µmCMOS a Commercial universal transducer interface for resistive bridges 25- Ω–10-kΩ with maximum imbalance ±4% or ±0.25% b The maximum resistance and capacitance are calculated using (10.3) and the measured output pulse widths, likewise the minimum resistance and capacitance are calculated using (10.3) and the measured jitters J.H.-L. Lu and B. Jung 10 Sensor Conditioning Circuits 241 the dynamic range of the sensor readout which makes it applicable to a wide range of resistive and capacitive sensors. It also allows the user to optimize the interface for either wide sensing range or high resolution. 10.5.4 Conclusion In this chapter, the basic concept of analog and semi-digital sensor conditioning circuits, including capacitive and resistive sensor readout, has been introduced. Sensor conditioning circuits has been widely used to condition the output of common analog sensors. Several principles can be exploited to measure the sensor capacitance, depending on requirements of resolution, type of output signal, dynamic range, power and area budget. Since every sensor has its own requirements for readout and every user has their own applications that require different types of sensors and readouts, a reconfigurable low-power universal sensor interface is crucial for successful implementation. The exploratory of an integrated universal sensor readout circuit in this chapter satisfies the requirements of the demanding compact low-power system with a power consumption of about 60-µW. It offers compatibility with a wide range of resistive and capacitive sensors while still maintaining reconfigurable functionality. References 1. Lu JH-L, Inerowicz M, Joo S, Kwon J-K, Jung B (2011) A low-power, wide-dynamic-range semi-digital universal sensor readout circuit using pulsewidth modulation. IEEE Sensors J doi: 10.1109/JSEN.2010.2085430 2. Stangel K, Kohnsberg S, Hammerschmidt D el al (2001) A programmable intraocular CMOS pressure sensor system implant. IEEE J Solid State Circ, soi:10.1109/4.933466 3. Chiang CT, Wang CS, Huang YC (2007) A CMOS integrated capacitance-to-frequency converter with digital compensation circuit designed for sensor interface applications. Proc IEEE Sensors, doi:10.1109/ICSENS.2007.4388561 4. Bruschi P, Navamini D. (2007) A current-mode, dual slope, integrated capacitance-to-pulse duration converter. IEEE J Solid State Circ, doi:10.1109/JSSC.2007.903102 5. Bruschi P, Navarrini D, Barillaro G et al (2004) A precise capacitance-to-pulse width converter for integrated sensors. Analog Integrated Circuits and Signal Processing, doi:10.1023/B: ALOG.0000038288.41566.0f 6. Toth FN, Meiyer GCM, Kerkvliet HMM (1995) Ultra-linear, low-cost measurement system for multi-electrode pF-range capacitors. Proc IMTC ’95, doi:10.1109/IMTC.1995.515370 7. Goes FMLV, Meijer MGC (1996) A novel low-cost capacitive sensor interface. IEEE Trans Instrum Meas, doi:10.1109/19.492782 8. Krummenacher F (1985) A high-resolution capacitance-to-frequency converter. IEEE J Solid State Circ, doi:10.1109/JSSC.1985.1052366 9. Wolffenbuttel R, Regtien P (1987) Capacitance-to-phase angle conversion for the detection of extremely small capacities. IEEE Trans Instrum Meas, IM-36:868–872 242 J.H.-L. Lu and B. Jung 10. Ignjatovic Z, Bocko MF (2005) An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter. IEEE Sensors J, doi:10.1109/JSEN.2004. 841453 11. De Marcellis A, Depari A, Ferri G et al (2008) A CMOS integrable oscillator-based front end for high-dynamic-range resistive sensors. IEEE Trans Instrum Meas, doi:10.1109/TIM.2008. 922075 12. Grassi M, Malcovati P, Baschirotto A (2007) A 141-dB dynamic range CMOS gas-sensor interface circuit without calibration with 16-bit digital output word. IEEE J Solid State Circ, doi:10.1109/JSSC.2007.899087 13. Razavi B (2001) Design of analog CMOS integrated circuits, 1st edn. McGraw-Hill, New York 14. Razavi B (2001) Design of integrated circuits for optical communications. McGraw-Hill, New York 15. Horak G, Bilas V, Vasi D (2008) Noise analysis of the pulse-width modulator for quasi-digital sensors. Proc IMTC ’08, doi:10.1109/IMTC.2008.4547124 16. Mason A, Chavan AV, Wise KD (2007) A mixed-voltage sensor readout circuit with on-chip calibration and built-in self-test. IEEE Sensors J, doi:10.1109/JSEN.2007.897957 17. Heidary A, Meijer GCM (2008) Features and design constraints for an optimized SC front-end circuit for capacitive sensors with a wide dynamic range. IEEE J Solid State Circ, doi:10.1109/ JSSC.2008.922390 18. (2008) Data Sheet, Universal Transducer Interface UTI. Smartec, http://www.smartec-sensors. com/en/products/uti-interface-en.html 19. Katuri KC, Asrani S, Ramasubramanian MK (2008) Intraocular pressure monitoring sensors. IEEE Sensors J, doi:10.1109/JSEN.2007.912539 20. Mason A, Yazdi N, Chavan AV et al (1998) A generic multielement microsystem for portable wireless applications. IEEE Proceedings, doi:10.1109/5.704279 21. Lemmerhirt DF, Wise KD (2006) Chip-scale integration of data-gathering microsystems. IEEE Proceedings, doi:10.1109/JPROC.2006.873619 Chapter 11 Steady State Simulation of Mixed Analog/Digital Circuits Federico Bizzarri, Angelo Brambilla, Giambattista Gruosso, and Giancarlo Storti Gajani 11.1 Introduction Signal processing applications often deal with periodic or almost periodic phenomena. Efficient methods to find steady state solutions in circuits implementing these applications are thus very useful and allow the computation of relevant derived quantities such as noise. Unfortunately, steady state methods are available only for “analog” circuits and not for mixed “analog/digital” ones. For these cases, a precise definition of the concept of “analog” vs. “digital” and refined numerical methods are needed. Defining a circuit as being digital or analog, often implying antithetic meanings to the two terms, has become in most cases useless if not even misleading. In most current system on chip (SOC) implementations, circuits are composed of cooperating subsystems that are implemented using the same silicon technology but are modelled using different approaches and different “abstraction” and detail levels. Each subsystem is responsible of a specific task and their joint operation implements the desired system function. In this context, the terms “digital” and “analog” are standard ways to identify subsystems that are naturally modeled and designed using, respectively, discrete or continuous variable representations. During the design phase it is also quite common to initially model single parts through a very simple and high level behavioural representation that is progressively refined and detailed in a low level model as the design evolves [1]. Behavioural models can be written quickly and allow short simulation times at the cost of an often imprecise description of the real circuit. F. Bizzarri • A. Brambilla • G. Gruosso () • G. Storti Gajani Politecnico di Milano, Dipartimento di Elettronica e Informazione, pza. Leonardo da Vinci, 32, I20122, Milano, Italy e-mail: [email protected]; [email protected]; [email protected]; [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 243 DOI 10.1007/978-1-4614-1383-7 11, © Springer Science+Business Media New York 2013 244 F. Bizzarri et al. As an example, if we consider a phase locked loop (PLL), its voltage con- trolled oscillator (VCO) and phase-frequency detector can be initially modelled as behavioural blocks. When a first assessment of the PLL performance is complete, the behavioural VCO model can be substituted by a more detailed transistor level description, and the phase-frequency detector by a gate level model. The digital parts of the circuit are almost always automatically synthesised starting from a high level formal description, given, for example, using the VERILOG or VHDL languages. The same approach can be applied to the design of digital to analog converters (D2As), analog to digital converters (A2Ds), switched capacitor filters, sigma delta modulators, CLASS-D amplifiers, etc. [2–4]. In a SOC each subsystem can be analyzed using the simulation tool that is most appropriate for the chosen description detail level. Digital subsystems could in principle be simulated using conventional analog tools such as SPICE-like simulators, but this is very inefficient, since the digital parts of a SOC are often composed of a huge number of components. It is much more efficient to use analog simulators to characterize and collect timing properties of simple digital cells, each composed by few tens of components, and check the functionality of the digital subsystems, that are composed by a very large number of these cells, using event- driven simulators [5–7]. After the initial design phases, where the digital and analog blocks of the circuit are simulated using different approaches and numerical algorithms, a general system simulation strategy is needed. A common approach is to perform an analog mixed signal (AMS) simulation where the digital and the analog simulators cooperate and synchronise the progress of system simulation time. In this case, pseudo-a2d (PA2D) and pseudo-d2a (PD2A) converters are inserted in the circuit netlist to adapt signal representation between the digital and the analog parts of the circuit. We defined these converters as “pseudo” since they are not part of the circuit in practice. To the authors’ knowledge, AMS simulators implement the direct current (DC) analysis, which determines at least one equilibrium point of the circuit, and the time domain (TRAN) analysis that, starting from a well defined initial condition, possibly determined by DC, computes the dynamic behaviour of the circuit [8]. Several analyses implemented in commonly used analog simulators are not available in AMS environments. Among these, those that allow to determine a periodic steady state solution, such as shooting (SH) and harmonic balance (HB); and derived ones, such as periodic small signal (PAC) and periodic noise (PNOISE), that allow to efficiently determine the small signal behaviour due to a small signal perturbation or noise that is superimposed to the circuit limit cycle in the phase space [9–12]. These analyses are largely used and useful for the design of periodic circuits such as, for example, those used for RF applications, PLLs, switched capacitor filters, etc. The unavailability of these analyses can be a serious problem, whose only solution is to find an approach that adds mixed analog/digital circuits to the class to which SH, PAC and PNOISE can be applied. This is possible if the concept of variational model is extended to dynamic systems that are not Lipschitz continuous. In the sequel, a general presentation of AMS simulation methods is given, the extension of these methods to allow periodic steady state simulations is then 11 Steady State Simulation of Mixed Analog/Digital Circuits 245 presented. The approach here shown has been developed starting from previous works in the field of mechanics based on the use of “saltation” matrices. Some pioneering work in the circuit analysis field and based on a similar approach can be found in [13]. A recent application of saltation matrices to the specific case of power conversion circuits can be found in [14, 15]. In these pages a unified and general framework for the use of saltation matrices in circuit simulation is presented, so to finally extend to mixed analog/digital circuits (i.e. circuits that are not Lipschitz continuous) variational model based analysis methods. A general presentation of saltation matrices from a systems theory point of view can be found in [16]. 11.2 The AMS Simulation Framework The definition of a unified modeling framework [17] allowing the computation of the variational model of an AMS circuit, which is the core of the steady state analyses mentioned in the Introduction, can be given following a step-by-step approach. Smooth non-autonomous analog circuits are first considered, then switching non- autonomous analog circuits and, finally, AMS circuits. 11.2.1 Smooth Non-autonomous Analog Circuits When one aims to formulate a compact and reliable model able to describe the dynamics of a well-posed smooth non-autonomous analog circuit, he can resort to the following semi-explicit index-1 differential algebraic equation (DAE) ⎧ ⎪ ⎪ x˙ “ f (x, y,t) g(x, y,t) “ 0 ⎨ , (11.1) x(t ) “ x0 ⎩ 0 ⎪ ⎪ g(x0 , y0 ,t0 ) “ 0 where the differential state variables and algebraic variables of the circuit are x(t) ∈ U ⊂ RNa and y(t) ∈ V ⊂ RMa , respectively, f : RNa +Ma +1 → RNa , and g : RNa +Ma +1 → RMa . In the case of smooth circuits, f and g are assumed to be continuously differentiable in their definition domain and their partial derivatives matrices are referred to as fx , fy , ft , gx , gy , and gt . As an example, fx jk “ ∂ f j /∂ xk , for j, k “ 1, . . . , Na . In (11.1), x0 is the initial condition of the circuit state variables at time t “ t0 , whereas the initial condition y0 of the algebraic variables must be chosen in order to satisfy the constraint g(x0 , y0 ,t0 ) “ 0. Under the aforementioned differentiability hypotheses for g, y0 can be evaluated through the implicit function theorem provided that gy (x0 , y0 ,t0 ) is not singular and a unique and smooth function 246 F. Bizzarri et al. γ : RNa +1 → RMa exists so that y0 “ γ (x0 ,t0 ). In general, this is possible for any (x∗ , y∗ ,t ∗ ) such that gy (x∗ , y∗ ,t ∗ ) is invertible, thus allowing to obtain the sensitivity of y with respect to a parameter p from the sensitivity of x with respect to the same parameter. In fact, assuming that (xs (t), ys (t)) is the solution of (11.1) for t ∈ [t0 ,t1 ], the sensitivity of this solution with respect to a system parameter p ∈ R can be computed from (11.1) as d dx dy ⎧ ⎪ ⎪ ˙ x“xs “ fx |x“xs x| + fy y“ys ⎪ ⎪ ⎪ ⎪ d p d p d p ⎪ ⎪ ⎨ dx dy gx |x“xs + gy y“ys “0 . (11.2) ⎪ ⎪ d p d p ⎪ ⎪ dx ⎪ ⎩ 0 “ u0 ⎪ ⎪ ⎪ dp Setting u ” dx/d p and w ” dy/d p and interchanging the order of derivatives, we obtain ⎧ ⎪ ⎪ u˙ “ fx |x“xs u + fy y“ys w ⎪ ⎨ gx |x“xs u + gy y“ys w “ 0 . (11.3) ⎪ ⎪ ⎪ u(t0 ) “ u0 ⎩ Equation (11.3) represents a “new” linear and time varying DAE and, since we have assumed that gy is non singular, we have w “ − g−1 y gx u (11.4) that, backsubstituted in (11.3), yields ⎧ −1 ⎨ u˙ “ fx |x“x − fy g g | u s x“xs y x“x x x“xs s . (11.5) u(t0 ) “ u0 ⎩ The u(t) solution of the linear time-varying differential equation (11.5) leads to the sensitivity of xs (t) with respect to parameter p; the w(t) sensitivity of ys (t) can be subsequently derived from (11.4). If one is interested in evaluating the sensitivity of the solution with respects to the initial conditions, it is sufficient to introduce matrices Φ (t,t0 ) ∈ RNa ×Na and Ψ (t,t0 ) ∈ RMa ×Na and solve ⎧ ⎨ Φ˙ (t,t0 ) “ fx | − fy x“xs g−1 y x“x gx |x“xs Φ (t,t0 ) x“xs s , (11.6) Φ (t0 ,t0 ) “ INa ⎩ 11 Steady State Simulation of Mixed Analog/Digital Circuits 247 where INa is the Na × Na identity matrix, and then evaluate Ψ (t,t0 ) “ y x“xs gx |x“xs Φ (t,t0 ). From a numerical point of view, since the partial − g−1 derivatives matrices in (11.6) are to be evaluated along the solution of (11.1), those differential equations are solved in parallel. The sensitivity matrix of y with respect to x0 is then given by Ψ (t,t0 ) “ −g−1 y gx Φ (t,t0 ). (11.7) If (xs (t), ys (t)) is a stable T -periodic solution of (11.1), the Φ (t0 + T,t0 ) monodromy matrix, solution of (11.6) at t “ t0 + T , exhibits Na eigenvalues laying on and within the unit circle in the complex plane. If the circuit is autonomous, i.e. (11.1) does not depend explicitly on time, at least one of these eigenvalues is fixed to 1. It is worth noting that the sensitivity of y with respect to y0 is always zero, since the algebraic variables of the circuit must satisfy, at each time instant, the constraint g(x, y,t) “ 0 given the specific dynamics of the circuit state variables. Correspondingly, if (11.1) is written as the equivalent ordinary differential equation (ODE) x˙ f (x, y,t) “ , (11.8) y˙ G(x, y,t) where G(x, y,t) “ −g−1y (gx f + gt ). If it admits a T -periodic solution, its sensitivity matrix evaluated over one period is characterized by Na + Ma eigenvalues; Na (exactly the same of Φ (t0 + T,t0 )) laying on and within the unit circle in the complex plane, and Ma identically null. 11.2.2 Saltation Matrices in Brief Before dealing with modelling of switching non-autonomous analog circuits, we first recall here the saltation matrix formulation, one of the basic mathematical tools that is extensively exploited in the sequel. The reader can find for instance in [16] all the details concerning the analytical derivation of this formulation. In Sect. 11.4.2 an approach analogous to the one in [16] is used to obtain the saltation matrix expression in a specific application case. Without lack of generality we focus our attention on a basic hybrid system described by the set of ODEs ⎧ f1 (x(t)), x(t) ∈ R1 (t) ˙ “ f (x(t)) “ ⎨ x(t) f2 (x(t)), x(t) ∈ R2 (t), (11.9) x(t0 ) “ x0 ⎩ where x ∈ RNa , f1 and f2 are assumed to be smooth in RNa , and subregions R1 and R2 are not fixed but can vary at different time instants since they are separated by a surface Σ (t) so that, for every t ≥ t0 , RNa “ R1 (t) ∪ Σ (t) ∪ R2 (t). An event manifold 248 F. Bizzarri et al. Fig. 11.1 An example of impact/switch phenomenon in R2 “ R1 ∪ Σ ∪ R2 h(x,t) is adopted to verify whether or not a generic point x(t) belongs to either Σ , R1 or R2 . More specifically R1 (t) “ +x ∈ RNa |h(x,t) < 0, + , Σ (t) “ +x ∈ RNa |h(x,t) “ 0, . (11.10) R2 (t) “ x ∈ RNa |h(x,t) > 0 The manifold h(x,t) is assumed to admit η “ [∇Tx h(x,t), ∂∂t h(x,t)]T as normal vector for all x(t) ∈ Σ (t), moreover, for all t ≥ t0 , η (x,t) f − (x(t)) · η T (x,t) f + (x(t)) > 0, - T . - . (11.11) which means that every trajectory reaches the surface Σ transversally so that sliding motion [16] is not allowed. As a further hypothesis, a mapping function M(x) : RNa → RNa is considered such that, whenever a trajectory crosses the surface Σ , for instance from R1 to R2 at x(t1 ) “ x− (t1 ), the variable x is instantaneously mapped into x+ (t1 ) “ M(x− (t1 )) in R2 . The dynamics of the system undergoes an impact at t1 (i.e. x+ (t1 ) ‰ x− (t1 )) and a switch (since x+ (t1 ) ∈ R2 implies f “ f2 for t > t1 ). The Jacobian matrix of M(x) will be referred to as Mx (x). With reference to Fig. 11.1, assuming that x0 ∈ R1 , Φ (t1 ,t0 ) can be obtained using the composition property of the sensitivity matrix, in this case as Φ (t2 ,t1 )SΦ (t1 ,t0 ), being f2 (M(x− (t1 )))−Mx (x− (t1 )) f1 (x− (t1 )) T S “ Mx (x− (t1 )) + ∇ h (x− (t1 ),t1 ) . (11.12) ∇T h (x− (t ),t ) f1 (x− (t1 )) + ∂ h (x− (t ),t ) 1 1 ∂t 1 1 11 Steady State Simulation of Mixed Analog/Digital Circuits 249 a b Fig. 11.2 Two different examples of two-dimensional “jumping” trajectories. In Fig. 11.2a both the differential variables x and the algebraic ones y are continuous since g undergoes no switch in correspondence with hSW (x, y,t1 ). On the contrary, in Fig. 11.2b, y− ‰ y+ since the algebraic constraint changes across hSW (x, y,t1 ) If M(x) “ x (i.e. no impact occurs), (11.12) reduces to f2 (x− (t1 )) − f1 (x− (t1 )) ∇T h (x− (t1 ),t1 ) . S “ INa + (11.13) ∇ h (x− (t1 ),t1 ) f1 (x− (t1 )) + ∂∂ ht (x− (t1 ),t1 ) T 11.2.3 Switching Non-autonomous Analog Circuits A switching non-autonomous analog circuit can be basically modeled by a piece- wise smooth DAE, i.e. considering f and g in (11.1) as piecewise smooth functions and introducing properly defined KSW manifolds partitioning the circuit state space in non-overlapping regions where f and g are continuously differentiable. These manifolds can be written as hSW,k (x, y,t) “ 0, for k “ 1, . . . , KSW , and it must be assumed that, for each of these manifolds, the normal vector exists and is expressed as ⎡ ⎤ ⎡ ηxSW,k (x, y,t) ∇x hSW,k (x, y,t) ⎤ ⎣ ηySW,k (x, y,t) ⎦ “ ⎣ ∇y hSW,k (x, y,t) ⎦ . (11.14) ⎢ ⎥ ∂ ηtSW,k (x, y,t) h ∂ t SW,k (x, y,t) When a trajectory “hits” one of these manifolds, say for instance at t “ t1 , either f or g, or both, undergo a switching event which is responsible of discontinuities in x˙ and/or y. The differential variables x in (11.1) are the circuit state variables and thus exhibit no discontinuous change, whereas the algebraic variables y can, possibly, undergo an impact event as shown in Fig. 11.2. This happens since, if the algebraic constraint changes when a given manifold is reached by a trajectory, intrinsic continuity of the differential state variables implies a “jump” in the algebraic ones (see Fig. 11.2b). In other words, adopting the superscript − and + to identify variable values immediately before and after t “ t1 respectively, one always has x+ “ x− and either y+ ‰ y− , if g switches, or y+ “ y− otherwise. In these cases, as introduced 250 F. Bizzarri et al. in Sect. 11.2.2 in the ODE case, it is still possible to define the matrices Φ (t,t0 ) and Ψ (t,t0 ) introduced in Sect. 11.2.1 by resorting to saltation matrices and the composition property of the sensitivity matrix. Saltation matrices can be viewed as “correction factors” to be introduced whenever a trajectory of the system hits one of the aforementioned manifolds. Consider now the more general case shown in Fig. 11.2b, in which both f and g exhibit a switch in correspondence with a generic manifold hSW (x, y,t) “ 0. It can be assumed that, starting from the initial condition (x0 , y0 ) at t “ t0 , we have ⎧ ⎨ hSW (x(t), y(t),t) < 0 t ∈ [t0 ,t1 ) h (x(t), y(t),t) “ 0 t “ t1 . (11.15) ⎩ SW hSW (x(t), y(t),t) > 0 t ∈ (t1 ,t2 ] In the following, making reference to Fig. 11.2b, functions f and g will be referred to as f1 and g1 , or f2 and g2 , if hSW (x(t), y(t),t) < 0 or if hSW (x(t), y(t),t) > 0, respectively. A further non restrictive basic assumption (already introduced in Sect. 11.2.2), is that fk and gk (for k “ 1, 2) are continuous and differentiable in U and V (see (11.1)). Under these assumptions, being (11.1) a semi-explicit index-1 DAE, we write (for k “ 1, 2) gkx (x, y,t)x˙ + gky (x, y,t)y˙ + gkt (x, y,t) “ 0. (11.16) By defining Gk (x, y,t) “ −g−1 ky (gkx f k + gkt ) (for k “ 1, 2), as it has been done in (11.8) for the smooth case, the piecewise smooth DAE modeling the switching circuit can be reformulated with the equivalent ODE x˙ fk (x, y,t) “ . (11.17) y˙ Gk (x, y,t) To keep notation terse, in the following all the expressions evaluated at t “ t1 in (x− , y− ) will be underlined whereas those evaluated in (x+ , y+ ) will be overlined. To obtain all the terms needed to evaluate the saltation matrix expression given in (11.12) for this extended ODE, the implicit function theorem is applied to g2 to identify the mapping function M (see Fig. 11.2b) relating (x− , y− ) to (x+ , y+ ), (x+ , y+ ) “ M(x− , y− ) “ (x− , γ2 (x+ ,t1 )) “ (x− , γ2 (x− ,t1 )) “ M . (11.18) As a further consequence of the implicit function theorem, the Jacobian matrix of M evaluated at (x− , y− ) is ! INa 0Na ×Ma M x,y “ , (11.19) −g−1 g 0 2y 2x Ma ×Ma 11 Steady State Simulation of Mixed Analog/Digital Circuits 251 where 0Na ×Ma is a Na × Ma matrix whose entries are zero. The saltation matrix expression is / 0 f2 f1 − M x,y G2 G1 S “ M x,y + / 0 η Tx , η Ty . (11.20) f SW SW ηx ,ηy T T 1 + ηt SW SW G1 SW Notice that the denominator of the second term in the r.h.s of (11.20) does not depend on the expression g2 assumed by g after the switching event. This term is related only to the system characteristics for t < t1 . The last and fundamental step is now to derive the saltation matrices SΦ and SΨ to be used directly in the DAE (and not in the extended ODE of (11.17)) to properly evaluate, also in the piecewise smooth case, Φ and Ψ , respectively. The basic idea is to keep in mind the very definition of saltation matrix and thus describe how a pertur- bation (Δ T x− , Δ T y− )T , applied immediately before the switching event at t “ t1 , is propagated and mapped in the perturbation (Δ T x+ , Δ T y+ )T observed immediately after the switching. Since, owing to the algebraic constraints in (11.1), a Δ x− perturbation of x− results in a corresponding perturbation Δ y− “ −g−1 − 1y g1x Δ x , by applying (11.20) one can write / 0 Δ x+ Δ x− Δ x− “S “S −1 . (11.21) Δ y+ Δ y− −g1y g1x Δ x− By substituting the expression of S from (11.20) in (11.21) one can write ⎛ ⎞ −1 η T η T ⎜ ⎟ ⎜ f 2 − f 1 x − y g 1y g 1x ⎟ + − ⎟ − Δ x “ SΦ Δ x “ ⎜INa + SW SW ⎟Δx ⎜ −1 ⎜ η x f 1 − η y g1y g1x f 1 + g1t + η t ⎟ T T ⎝loooooooooooooooooooooooooooomoooooooooooooooooooooooooooon SW SW SW ⎠ SΦ (11.22) and Δ y+ “ SΨ Δ x− ⎛ ⎞ ⎜ T ⎟ g−1 g2x f 1 − g−1 η x − η Ty g−1 2y g2x f 2 + g2t g1x ⎟ ⎜ ⎜ −1 2y SW 1y ⎟ − ⎟Δx . ⎜−g2y g2x + “⎜ SW η x f 1 − η y g1y g1x f 1 + g1t + η t T T −1 ⎟ ⎜ ⎟ ⎝looooooooooooooooooooooooooooooooooooooooomooooooooooooooooooooooooooooooooooooooooon SW SW SW ⎠ SΨ (11.23) 252 F. Bizzarri et al. If just f is involved in the switching event (i.e., g1 “ g2 as in Fig. 11.2a) no impact is observed on y (i.e., y+ “ y− ). As a consequence, mapping M reduces to (x+ , y+ ) “ (x− , y− ) and M x,y “ INa +Ma , in this case it is easy to verify that SΨ = SΦ . The last step is to apply the composition property of the sensitivity matrix as in Sect. 11.2.2. With reference to Fig. 11.2, consider a trajectory originated from the initial condition (x0 , y0 ) at t “ t0 belonging to the state-space region in which fk “ f1 and Gk “ G1 and reaching the manifold hSW (x, y,t) at t “ t1 . Then, for t “ t1 , the switching event described above takes place and for t ∈ (t1 ,t2 ] fk “ f2 and Gk “ G2 . In this case, owing to the composition property, the sensitivity matrix Φ (t2 ,t0 ) is given by Φ (t2 ,t1 )SΦ Φ (t1 ,t0 ) where Φ (t2 ,t1 ) and Φ (t1 ,t0 ) are “conventional” sensitivity matrices. Mutatis mutandis according to (11.7), Ψ (t2 ,t0 ) “ Ψ (t2 ,t1 )SΨ Ψ (t1 ,t0 ). If a generic piecewise smooth dynamical system admits a T -period solution, by properly introducing saltation matrices the same considerations done in Sect. 11.2.1 concerning the eigenvalues of the system monodromy matrix hold. 11.2.4 AMS Circuits As a first step one can think of an AMS circuit as the composition of an “analog” part and a “digital/behavioral” part (see Fig. 11.3). Actually, from a purely physical point of view, the analog vs. digital distinction is in many ways artificial. When simulations of these circuits are performed, the distinction is often ruled by practical limitations (in terms of simulation times) and detail level required by the designer. For large circuits, it is common practice to represent parts of the circuit with very detailed analog models, and other parts with simplified behavioral (digital) models. The same circuit can be thus modeled in many different ways, the main goal of the mixed mode simulation is to obtain sufficiently accurate results in a reasonable simulation time. In the analog part of the circuit all variables and time will assume real values and dynamical behaviour is modeled by a DAE (as described in Sects. 11.2.1 and 11.2.3). At the digital side all variables, except, possibly, time, are assumed as being quantized; this second part of the circuit is described by a discrete map (function s( · ) in Fig. 11.3, representing the sequential parts of the circuit) plus, if it is necessary, some additional algebraic equations, modeling eventual pure combinatorial parts (function c( · ) in Fig. 11.3). The counterparts at the digital side of the differential and algebraic variables of the analog part are, respectively, the sequential variables w ∈ RNd and the combinatorial ones v ∈ RMd . Since the digital and the analog domains have, in general, a different scale of values, each of these variables is remapped in the digital and analog parts, thus obtaining xd , yd and wa , va , respectively. To do this a set of mapping functions is needed 11 Steady State Simulation of Mixed Analog/Digital Circuits 253 Fig. 11.3 The generic architecture of an AMS circuit. The time variable t is assumed, at least in principle, to be available at both sides of the circuit. In particular, in the digital part, both a clock signal td and the continuous variable t are available. Clock-time can trigger sequential events and the continuous variable can be used to store the value of t at specific events if one is interested, for instance, in producing delayed digital outputs xd “ µa2d (x) ⎧ ⎪ ⎪ ⎨ y “ µ (y) ⎪ d a2d (11.24) ⎪ ⎪ ⎪ wa “ µd2a (w) va “ µd2a (v) ⎩ that, in the simplest case, are PA2D and PD2A converters. Using this notation, as shown in Fig. 11.3, variables xd and yd have the role of “input” to the digital part, while variables wa and va can be considered as input to the analog part. To take into account the influence of these new variables, (11.1) can be rewritten as ⎪ x˙ “ f (x, y,t; µd2a (w), µd2a (v)) ⎧ ⎪ ⎨ g(x, y,t; µ (w), µ (v)) “ 0 ⎪ d2a d2a . (11.25) ⎪ ⎪ ⎪ x(t0 ; µ d2a (w 0 ), µ d2a (v0 )) “ x0 g(x0 , y0 ,t0 ; µd2a (w0 ), µd2a (v0 )) “ 0 ⎩ From the notation used in (11.25), it can be thought that the digital variables mapped in the analog domain act as parameters. It is crucial to highlight that these parameters are time-varying and their evolution is governed by w(tn+1 ) “ s(w(tn ), v(tn ),tn ; µa2d (x(tn )), µa2d (y(tn ))) ⎧ ⎪ ⎪ ⎨ c(w(t ), v(t ),t ; µ (x(t )), µ (y(t ))) “ 0 ⎪ n+1 n+1 n+1 a2d n+1 a2d n+1 . (11.26) ⎪ ⎪ ⎪ w(t ; µ 0 a2d 0 (x ), µ (y a2d 0 )) “ w 0 c(w0 , v0 ,t0 ; µa2d (x0 ), µa2d (y0 )) “ 0 ⎩ 254 F. Bizzarri et al. Evaluation of (11.26) is performed at time instant tn+1 in correspondence to the occurrence of external or internal events, e.g. transition of a clock signal, change of value of one or more input signal, etc. The values used in the r.h.s. of map s are evaluated at a previous time instant tn . The time step tn+1 − tn can have a fixed value in clocked digital systems or any value (and even tend to zero) if the digital part is event driven. Functions f and g in (11.25), as it has been done in Sect. 11.2.3 to deal with hybrid non autonomous analog circuits, are assumed to be continuously differentiable in a set of regions of the state space delimited by a proper set of switching manifolds. Note that switching phenomena are now ruled also by w and v. As matter of fact, even under the simplest assumption that both f and g are continuously differentiable in all their definition domain, a discontinuity in the digital variables can be interpreted as a switching event for those functions. To summarize, at the analog side one can observe the phenomena described in Sect. 11.2.3 owing to both the nature of functions f and g themselves, and the influence of variations of w and v. As a consequence the switching manifolds must be re-written as hSW,k (x, y,t; µd2a (w), µd2a (v)) “ 0, for k “ 1, . . . , KSW . At this point it is essential to focus on the dynamics of the digital part of the circuit and variables w will be first considered. These variables, if analyzed from the continuous time domain point of view, are characterized by an always null time derivative but in correspondence with those events that are responsible of their discontinuous variation, where their derivative is not defined. These (impact) events take place in correspondence to the occurrence of external or internal events and can thus be associated to impact manifolds. In the simplest case, w variables undergo impact events because the outputs of µa2d converters, that are stored in w-type variables, change. This kind of situation induces a subset of manifolds depending on x and y. A further cause of change of variables w is due to the evolution of map s. This may occur because of (1) a clock signal (in this case simple manifolds depending only on t are to be considered), (2) a variation of variables w depending on the µa2d converters outputs, or (3) a variation of variables v. In the last case, some of the variables v must change so that the (algebraic) combinatorial constraints c still hold when any of the variables w, storing the output xd and yd of µa2d converters, are changed. To summarize, discontinuous variations of w may occur when proper impact manifolds hIM, j (w, v,t; x, y) “ 0, for j “ 1, . . . , JIM , are reached by the system trajectory. The only difference between the manifolds hSW,k and hIM, j is that the former depend on the digital to analog conversion of w and v whereas the latter directly depend on x and y. This discrepancy is due to the fact that the µa2d converters are directly involved into the formulation of hIM, j and can be viewed as belonging to the digital side. For the sake of symmetry, the µd2a converters can be included in the analog part and, more specifically, in the very formulation of functions f , g, and hSW,k . This is represented by the darker gray regions in Fig. 11.3. As a last preliminary step, the reset functions ruling the variations of w and v must be analyzed. As far as w is concerned, the µa2d converters and the map s are directly responsible of assigning to w+ proper values whenever an impact manifold 11 Steady State Simulation of Mixed Analog/Digital Circuits 255 is reached at a given time instant t “ t1 . The value v+ of the algebraic variables is in turn computed by resorting to function c. In the most general situation both w+ and v+ are evaluated through a map M depending on x− , y− , w− , and v− as discussed in Sect. 11.2.3 in relation to y+ . Since (1) w and v can assume only discrete values and (2) the analytic expressions of s, c, and µa2d are not in general differentiable (for instance think of a combinatorial function c made up of logical operators), the reset functions acting on w− and v− will be treated as simple assignments M(x− , y− , w− , v− ) “ constant. The above assumption is crucial and its effects must be highlighted. A direct consequence is that the Jacobian matrix Mw,v of the reset function M is a diagonal matrix Λ whose entries Λq,q (for q “ 1, . . . , Nd + Md ) are 1, if the corresponding digital variable w or v is unchanged by M, and 0 otherwise. Moreover, from a more conceptual point of view, a constant M means that no direct perturbations are allowed at the digital side; its time evolution can be only indirectly perturbed by the analog part of the circuit. The effect of this perturbation can be interpreted as jitter at the digital side, since it simply affects the time instant at which impact events may occur but does not modify the values assumed by w+ and w− . Finally, by introducing a new differential variable z “ (xT , wT , vT )T , the whole AMS circuit is described as follows ⎧ ⎛ ⎞ ⎪ ⎪ f (x, w, v, y,t) ⎪ ⎪ ⎪ ⎪ z˙ “ ⎝ 0 ⎠ “ F(z, y,t) ⎪ ⎪ ⎪ ⎪ ⎨ 0 g(z, y,t) “ 0 , (11.27) T T T T ⎪ ⎪ ⎪ ⎪ z(t 0 ) “ (x 0 , w 0 , v 0 ) ⎪ g(z0 , y0 ,t0 ) “ 0 ⎪ ⎪ ⎪ ⎪ ⎪ c(z0 , y0 ,t0 ) “ 0 ⎩ together with the manifolds hSW,k (z, y,t) “ 0, k “ 1, . . . , KSW , (11.28) hIM, j (z, y,t) “ 0, j “ 1, . . . , JIM and their normal vectors ηzΘ ∇z hΘ ⎡ ⎤ ⎡ ⎤ ⎣ ηy ⎦ “ ⎣ ∇y hΘ ⎦ , (11.29) Θ ∂ ηtΘ ∂ t hΘ where Θ is either {SW, k} or {IM, j}. For the sake of simplicity, in the following, whenever possible, symbol Θ will be omitted. The sensitivity matrix of system (11.27) can be computed as introduced in Sect. 11.2.3 by assuming that (1) both functions F and g in (11.27) are piecewise 256 F. Bizzarri et al. continuously differentiable and (2) the implicit function theorem can still be applied to g. Matrices Φ and Ψ are now RNa +Nd +Md × RNa +Nd +Md and RMa × RNa +Nd +Md , respectively. Saltation matrix SΦ can be evaluated as in Sect. 11.2.3, and DAE (11.27) can be written as an equivalent ODE as it has been done for (11.1) in (11.17). Then the analogous of (11.20) can be derived and matrix Mz,y is obtained. In this case this matrix exhibits the following structure ! Γ 0(Na +Nd +Md )×Ma Mz,y “ , (11.30) −g−1 y gz 0Ma ×Ma where ! INa 0Na ×(Nd +Md ) Γ“ . (11.31) 0(Nd +Md )×Na Λ Saltation matrix SΦ can then be written as F 2 − Γ F 1 η Tz − η Ty g−1 g 1y 1z SΦ “ Γ + . (11.32) η Tx f 1 − η Ty g−1 1y g f 1x 1 + g1t + η t As in the analog case, if g is continuously differentiable in all its definition domain, (11.30) becomes ! Γ 0(Na +Nd +Md )×Ma Mz,y “ . (11.33) 0Ma ×(Na +Nd +Md ) IMa It is easy to show that, in both this last case and the previous one, the saltation matrix SΨ is exactly the same as in the analog case. 11.3 Time Domain Periodic Steady State Algorithms The basic time domain periodic steady state simulation method is the well known SH which allows to efficiently obtain (if it exists) a limit cycle corresponding to a periodic steady-state solution of the circuit being analysed or designed. Once this limit cycle has been obtained, two other time domain periodic steady state simulation methods are typically adopted, PAC and PNOISE (see for instance [9–11, 18–20]), which are used to determine, with an acceptable computational effort, the small signal behaviour due to a small signal perturbation or noise, respectively, that is superimposed to the available limit cycle. We limit here our discussion to SH since, once it is shown how it can be extended to the proposed AMS simulation framework, it will be worth extending also the 11 Steady State Simulation of Mixed Analog/Digital Circuits 257 other two simulation methods. SH can be formulated in different ways, here a simple presentation of one of these is briefly given, a more thorough analysis can be found in [21, 22]. The first important assumption that must be made is that system (11.27) admits a limit cycle as a steady-state solution and that an initial condition x0 sufficiently close to the cycle is known. In this case, if a smooth ODE is considered (i.e. there are no algebraic equations, no digital parts, and no vector field switchings) the solution is relatively simple and well known. Denote with xs (t) “ xs (t + Ts ) the expected periodic solution of unknown period Ts and augment the original ODE with equation dT /d τ “ 0, where T is the unknown period of solution xs (t) and, having adopted the transformation τ “ t/T is such that the period of the transformed problem is equal to 1. The boundary conditions that must be specified for the transformed problem must force the trajectory that is found to be closed and, for autonomous systems, must specify a phase condition s that ensures that the boundary-value problem (BVP) has a unique solution # x(1) − x(0) “ 0 , (11.34) s(x(0), T ) “ 0 The nonlinear equation solved by SH for this BVP is # r(x(0), T ) “ ϕ (x(0), T ) − x(0) “ 0 , (11.35) s(x(0), T ) “ 0 where ϕ (x(0), T ) is the solution of the initial-value problem at t “ T , from initial condition x(0). Equation (11.35) can be solved using a Newton method, solving at each step a linear equation whose coefficients matrix is ϕx − INa ϕT (11.36) sx sT where, at the i-th iteration, the entries of (11.36) are evaluated at the current approximation (x(i) (0), T (i) ). When the Newton iterative method converges, an initial condition x∗ (0) on the limit cycle and the cycle period T ∗ are found, moreover, Φ “ ϕx |(x∗ (0),T ∗ ) (11.37) is the correct sensitivity matrix. If switching events are present, SH can be easily generalized by introducing saltation matrices, in the following we will call this method including all related auxiliary algorithms discontinuous shooting (DSH). The Newton method yields at 258 F. Bizzarri et al. each time step tn the sensitivity matrix Φ (tn ,tn−1 ) and Φ (1, 0) can be derived as the left product [23] Ns Φ (1, 0) “ ∏ Φ (tn ,tn−1). (11.38) n “1 If switching events are located at known time instants, it is sufficient to insert in the above left product a saltation matrix SΦ at each event. If, as an example, there are two discontinuities in the vector field at time samples n “ N1 and n “ N2 (N1 < N2 ), (11.38) becomes / 0 NS Φ (1, 0) “ ∏ Φ (tn ,tn−1 ) SΦN2 · n“N2 +1 / 0 / 0 N2 N1 · ∏ Φ (tn ,tn−1 ) SΦN1 · ∏ Φ (tn ,tn−1 ) . (11.39) n“N1 +1 n “1 Extension to the DAE case is rather straightforward and is detailed in [17]. In the general case, the AMS circuit is modelled by (11.27) and, since w and v can assume only discrete values, at each Newton iteration i providing the next z(i+1) (0), only x(i+1) (0) are to be directly considered as the initial condition for the next step of the time domain analysis, whereas w(i+1) (0) and v(i+1) (0) are to be evaluated according to the relations enforced by the digital part of the circuit. 11.4 Localization of the Switching and Impacting Manifolds A main ingredient for the computation of the correct fundamental matrix for generic AMS circuits are the saltation matrices introduced in (11.20) and (11.32). These formulas require knowledge of the hSW,IM (z, y,t) manifolds and of their normal vector, and this can in some cases require some further analysis. In the AMS circuit simulation context it is possible to distinguish between two different types of manifolds, the extrinsic ones and the intrinsic ones. Manifolds of the former type are known a priori and can be easily formalised, as, for example, the PA2D pseudo-converters: in this case the thresholds that define the corresponding digital code are known a priori. Manifolds of the latter type are not known a priori and must be determined run-time during the circuit simulation. In the next two sections we present, respectively, an approach to automatically locate intrinsic manifolds and an algorithm to efficiently manage extrinsic ones. 11.4.1 Automatic Location of Intrinsic Manifolds Consider the DAE described in (11.27) and perform one integration step of the time domain analysis, which is at the base of SH. Assume to know the x(tn ) and y(tn ) components of the solution at the tn time instant and to compute the 11 Steady State Simulation of Mixed Analog/Digital Circuits 259 same components at tn+1 “ tn + hn , where hn is the integration time step. The ˙ n+1 ) and y(t x(t ˙ n+1 ) derivatives are directly available from the evaluation of the f (x(tn+1 ), w(tn+1 ), v(tn+1 ), y(tn+1 ),tn+1 ) vector field and g(x(tn+1 ), y(tn+1 ),tn+1 ) in (11.27). The r˙(tn+1 ) and s(t˙ n+1 ) estimates of x(t ˙ n+1 ) and y(t ˙ n+1 ), can be computed, respectively, through the sensitivity matrices Φ (tn+1 ,tn ) and Ψ (tn+1 ,tn ) as ˙ n+1 ) r˙(tn+1 ) ⎡ ⎤ ⎡ ⎤ x(t ⎢ ˙ n+1 ) ⎥ » ⎢ . . . ⎥ ⎢ w(t ⎥ ⎢ ⎥ ˙ n+1 ) ⎣ v(t ⎦ ⎣ ... ⎦ ˙ n+1 ) y(t ˙ n+1 ) s(t Φ (tn+1 ,tn ) 0Na +Nd +Md ×Ma z˙(tn ) F (z(t ), y(tn ),tn) “ + t n , (11.40) 0Ma ×Na +Nd +Md Ψ (tn+1 ,tn ) ˙ n) y(t gt (z(tn ), y(tn ),tn) where the known term is different from zero only in non-autonomous circuits. If f and g are smooth functions we have χr(tn+1 ) hkkkkkikkkkkj χp (tn+1 ) hkkkkkikkkkkj r˙(tn+1 ) ˙ x(t n+1 ) “ ζn+1 “ 0. lim − (11.41) ˙ n+1 ) hn →0 s(t ˙ n+1 ) y(t Consider now inequality ζn+1, j ≤ ψn+1, j “ αrel min χr j (tn+1 ) , χp j (tn+1 ) + αabs (11.42) where subscript j identifies the j-th component, 0 < αrel < 1 represents a relative tolerance threshold and αabs ∈ R+ represents the absolute one. Along the time domain integration of (11.27), (11.42) is used as a monitor function to locate jumps in the vector field. Any time (11.42) is not satisfied the integration time step hn is shortened and the integration procedure is repeated. If the value of hn becomes smaller than the minimum allowed step hmin determined by the relative precision ε of the ALU and inequality (11.42) is still unsatisfied, then it is possible to conclude that f and/or g are not “sufficiently” smooth or, equivalently, that there is a “jump” and thus introduce a saltation matrix. This “cut and try” mechanism ensures that the manifold is located in time with an accuracy limited by ε , i.e. the best possible one. In case of a “false alarm”, since f and g are smooth, the SΦ and SΨ saltation matrices in (11.22) and (11.23) simply reduce to the identity matrix. False jumps can be due to modeling functions such as a(t) “ tanh(kb(t)) that are C∞ , but that can be seen as discontinuous during their numerical evaluation if the |kb(t)| argument undergoes large variations. In this case the h(z, y,t) equation of the manifold does not exist, but, during simulations, “numerical manifolds” have to be anyway located and saltation matrix exploited to accurately compute the fundamental matrix. 260 F. Bizzarri et al. When a jump has been located in time, its normal vector must be computed. We assume that, locally, the manifold is modeled with sufficient accuracy by the linear equation - T T . ηz ⎡ ⎤ z y t ⎣ ηy ⎦ − b “ 0 (11.43) ηt where b can assume only the 0 and 1 values. The number of unknowns in (11.43) is (Na + Ma + Nd + Md + 1), therefore, the same number of independent scalar equations is needed to determine the entries of the ηz , ηy and ηt unknown vectors. We “explore” F and g in a neighborhood of the manifold by starting from the (z− − δz ,t − − δt ) solution (see Fig. 11.2), y is derived using g. Increments δz and δt are chosen so that we remain in the portion of the vector field laying before the manifold traversal point but sufficiently far to ensure an acceptable condition number of the matrix related to the linear problem in (11.43). We explore F and g by linearly varying one by one each of the analog state variable components of z j ( j “ 1, . . . , Na ). Specifically, the value of δz, j is increased until the maximum allowed value δz,max j while checking if there is a sharp variation of a component of F and g. The value of z + δz, j and y at which there is the jump is substituted in scalar equation (11.43) and we set b “ 1. This procedure is repeated for each component of z and for t. Note that each sweep exclusively requires evaluations of F and g and is thus very efficient. If a sweep till δz,max j does not show any sharp variation of F or g, then the manifold does not depend on this specific z j component; in this case we set z j “ 1, all the other entries of z and y equal to 0 and b “ 0. The same mechanism is applied to time t. At the end of this process the set of scalar equations (11.43) forms a linear problem that can be solved for ηz , ηy and ηt . 11.4.2 An Algorithm to Efficiently Manage Extrinsic Manifolds As a first assumption we will consider an AMS circuit modeled by (11.27)–(11.29) in the special case in which its analog part is described by an ODE (i.e., no algebraic variables y are present at the analog side) and the switching manifolds hSW,k (z) (for k “ 1, . . . , KSW ) depend on w and v only. The first assumption can subsequently be removed thus generalizing the method also to DAEs. The second assumption means that switching phenomena at the analog side of the circuit are driven just by digital events transferred to the analog side by PD2As. These events will be identified in the following by generic manifolds hPD2A (z). The digital part of the circuit, in turn, is driven by the evolution of an external time signal triggering digital events and by the outputs of PA2Ds providing it with evolving values xd to be processed. The latter events will be associated with the hPA2D (z) manifolds. 11 Steady State Simulation of Mixed Analog/Digital Circuits 261 Fig. 11.4 A simple example ξ of AMS circuit. The AND x 1d PA2D − + logic gate is assumed to be x1 characterized by a delay Δ t in Analog x 2d its elaboration time. ξ is a PA2D noise voltage source x2 − + v1a v1 PD2A All the aforementioned manifolds are extrinsic since their analytical expressions are provided by PA2Ds and PD2As, whose “mapping functions” are assigned when the AMS circuit is designed. One can now ask himself how a perturbation applied to the analog part of the circuit propagates its effect through the digital one and then how it comes back. This is interesting since, if we assume to have noise at the analog part of the circuit, it affects the analog variables x causing uncertainty at the input of PA2Ds and, consequently, affecting the time instants at which the xd variables change. This, in turn, causes a variation in the time instant at which PD2As “communicate” at the analog side, through wa and va , the output of the digital elaboration driven by the evolution of xd and, consequently, its effect on the dynamics of x. If we stop at this level of analysis, one might be convinced that each event modeled by a hPA2D (z) manifold always has repercussions on the effects, at the analog side, of a related hPD2A (z)-manifold modeled event. In fact this is not the case. A simple example is given in Fig. 11.4 where the digital (combinatorial) part of the circuit is simply made up of a logic AND gate characterized by a delay Δ t in its elaboration time. The v1 output of such a gate is passed to the analog part of the circuit to drive, for instance, an ideal switch. The inputs of the gate are two properly digitally converted analog variables x1 and x2 , the former being perturbed by a noise source ξ . We can imagine to choose an initial condition for the circuit at t “ t0 so that x1d (t0 ) “ x2d (t0 ) “ 0 (in the following 0 and 1 stand for the logical values false and true, respectively). Assume now ξ to be null and the evolution of the analog part of the circuit to be such that x1d “ 1 and x2d “ 1 in t1 and t2 , respectively, with t1 < t2 . It is evident that v1a (t2 + Δ t) “ 1. Assume now ξ ‰ 0, in this case x1d “ 1 at t “ t1 + Δ t1 but, if t1 + Δ t1 < t2 , one will always observe v1a (t2 + Δ t) “ 1. This means that the effect of perturbing x1 is not propagated back from the digital part of the circuit to the analog one. Exactly the opposite behaviour would be obtained by perturbing x2 instead of x1 . Through this simple example it should be clear that, in general, when analyzing the dynamics of an AMS circuit, all the events at the digital side driven by PA2Ds should be tracked in order to identify which one is the last responsible of a subsequent PD2A event. Each event can be tagged at the analog/digital interface and these tags are propagated in the digital elaboration and finally used, if necessary, at 262 F. Bizzarri et al. Fig. 11.5 Nominal (starting from initial condition z0 ) and perturbed (from z0 + Δ z0 ) trajectories. Manifolds hPA2D (z) and hPD2A (z) represent, respectively, switching of a PA2D and of a PD2A, only the latter represents a change of vector field and, hence, a switching condition. This sketch represents the projection of the system trajectory on the analog state variables subspace the digital/analog interface. The algorithm we show in the following exploits exactly this idea properly “composing” saltation matrices during the analysis of the circuit dynamics. Before proceeding, another important consideration must be done concerning the digital elaboration time. In general, it makes sense assuming that the effects of an event driven by a PA2D can be always observed at the analog side after an even brief time interval. This time interval can depend on either the intrinsic delays of the digital part, or the digital part elaboration time, or a fixed time chosen by the circuit designer as it happens, for instance, in pulsed energy restored oscillators [24]. In general, when a given hPA2D is reached, the derivative of the continuous trajectory of the x-variables exhibits no discontinuity. Keeping this concept in mind, let’s consider Fig. 11.5 in which previous assumptions have been graphically summarized. By referring to this figure, we imagine to compute the system sensitivity matrix along a trajectory starting from z0 and evolving in the region where f1 is the active vector field. At z1 the hPA2D (z) boundary introduced by a PA2D is traversed and its digital output code changes; however, there is no jump in the vector field at the analog side. At z2 there is a “jump” in the vector field caused by the switching of a PD2A; this is formalised by traversal of the hPD2A (z) “ 0 manifold. The trajectory then evolves from z2 to z3 showing a cusp in z2 . In this specific case we want to derive the expression of the Sp saltation matrix finding out (at first order) how the Δ z0 perturbation of the state z0 at t0 affects the deviation of the trajectory from z3 to z3 + Δ z3 at t “ t0 + tPA2D (z0 + Δ z0 ) + Δxt being • tPA2D (z(t0 )) the time needed to reach the hPA2D (z) manifold (i.e. switching of a PA2D) from z(t0 ). • Δxt the fixed time interval that must elapse after the switching of the PA2D before observing a switch in the vector field of the analog part of the circuit; this happens x when the trajectory reaches the manifold hPD2A (z) “ z−ϕ t0 +tPA2D (z(t0 ))+Δ t (z(t0 )). 11 Steady State Simulation of Mixed Analog/Digital Circuits 263 • ϕ t (z(t0 )) the system trajectory evaluated at t and originated in z(t0 ). Furthermore, without losing generality, it is assumed that tPA2D (z0 + Δ z0 ) “ Ăt with Δ tPA2D (z0 ) + Δ Ăt > 0. In particular, we are interested in deriving Sp such that Δ z3 “ SpΔ z1 . (11.44) To obtain a simpler notation we define (see Fig. 11.5) z1 “ ϕ t0 +tPA2D (z0 ) (z0 ) z1 + Δ z1 “ ϕ t0 +tPA2D (z0 ) (z0 + Δ z0 ) x z2 “ ϕ t0 +tPA2D (z0 )+Δ t (z0 ) x z3 “ ϕ t0 +tPA2D (z0 +Δ z0 )+Δ t (z0 ) . (11.45) Δ x Δ z3 + Δ z3 “ ϕ 0 PA2D 0 0 t +t (z + z )+ t (z0 + Δ z0 ) z4 “ ϕ t0 +tPA2D (z0 +Δ z0 ) (z0 + Δ z0 ) x z5 “ ϕ t0 +tPA2D (z0 )+Δ t (z0 + Δ z0 ) As a first step it is possible to write Ăt z3 « z2 + f2 (z2 )Δ Ă Ăt , z3 + Δ z3 « z5 + f1 (z5 )Δ t « z5 + f1 (z2 )Δ (11.46) and then 0 “ hPA2D (z4 ) « « hPA2D (z1 + Δ z1 + f1 (z1 + Δ z1 )ΔĂt) « Ăt « (11.47) « hPA2D (z1 + Δ z1 ) + ηPA2D (z) z +Δ z f1 (z1 + Δ z1 )Δ T 1 1 « η T (z) Δ z1 + η T (z) f1 (z1 )Δ Ăt. PA2D z1 PA2D z1 From (11.47) and (11.46) we have ηPA2D T (z)z Δ z1 Ăt “ − Δ 1 , ηPA2D T (z)z f1 (z1 ) 1 Ăt , respectively. By defining Φik the system and Δ z3 “ z2 − z5 + ( f2 (z2 ) − f1 (z2 )) Δ sensitivity matrix evaluated on the trajectory originated from zk and ending in zi , since z2 − z5 “ Φ21 Δ z1 , we finally obtain ( f2 (z2 ) − f1 (z2 )) T Sp “ Φ21 + T η PA2D (z) , (11.48) ηPA2D (z)z f1 (z1 ) z1 1 264 F. Bizzarri et al. and thus ⎡ ⎤ T ⎢ η PA2D (z)z Φ 10 ⎥ Φ 30 “ Φ 32 ⎢Φ 20 + ( f2 (z2 ) − f1 (z2 )) T ⎢ 1 ⎥ η PA2D (z)z f1 (z1 ) ⎦ , ⎥ ⎣ loooooooooomoooooooooon 1 (11.49) loooooooooooooooooooooooooooomoooooooooooooooooooooooooooon α β If switching of PA2D and PD2A is simultaneous, Δ xt → 0 and, consequently, Sp reduces to the standard saltation matrix formulation given in (11.13). At this point it is possible to delineate an algorithm to deal with the extrinsic manifolds to be included in the DSH analysis (see Sect. 11.3). • At each integration time step it is checked if at least one PA2D or PD2A has switched. In the following we consider first a commutation of a PA2D since PD2As switches are a consequence of PA2Ds commutations. • If there is a switch of a PA2D, the corresponding hPA2D (z) “ 0 manifold is known since it is defined by the voltage threshold at which there is a change in the digital coding at the PA2D output. The manifold equation is added as an extra equation to those of SH and the integration time step is added among the unknowns to have a well posed problem. The solution of this enlarged problem gives the “exact” time instant at which the manifold is hit. The term exact is quoted since we use the Newton method to solve this problem and the iterative method stops when the estimated accuracy of the found time step satisfies a given value. • Vector α of (11.49) is computed. The ηPA2D T (z)z normal to the manifold is 1 known together with both the f1 (z1 ) vector field and the Φ10 transition matrix at the switching time instant. The vector is attached as a property of the digital network connected to the output of the switching PA2D. • These α properties are handled and inherited consistently with the elaboration of the digital signals in the digital portion of the circuit. The elaboration depends on the implementation of the digital model of the circuit through, for example, the VERILOG or the VHDL languages. At the end of the digital elaboration (that can involve also delays) there can be a switching of a PD2A due to a change of the digital code at its input. In Fig. 11.5 this is formalised by manifold hPD2A (z) “ 0. The specific α property attached to the digital net that is causing the commutation is assigned to the PD2A. • When a PD2A commutes it can generate a jump in the vector field; product β in (11.49) is computed by exploiting the propagated α property. This implementation is highly efficient since the memory required to compute the saltation matrices depends only on the number of PA2Ds, being the number of α variables equal to the number of PA2Ds, and not on the complexity of the analog and digital parts of the circuit. 11 Steady State Simulation of Mixed Analog/Digital Circuits 265 11.5 Numerical Results To show the effectiveness of the approach discussed in the previous sections, in the sequel we consider two circuits that implement signal processing functions and that can be modeled by DAEs characterised by a switching vector field. We simulate them with DSH in the version implemented in our simulator PAN1 and discuss the obtained numerical results. Before proceeding, we underline that the emphasis in proposing these circuits is not on the circuits themselves but on the application of the DSH approach. The first circuit here considered is shown in Fig. 11.6; it implements a simple sample & hold (S&H) that drives an analog to digital converter (ADC). The ADC is directly connected to a digital to analog converter (DAC) that drives a low pass RC filter. We intentionally omitted the digital circuit that eventually does the elaboration of the signal before its conversion by the DAC since it is irrelevant in this context. The circuit is driven by a “large” 1 V at 10 kHz sinusoidal input signal, we are interested in the small signal behaviour of this circuit, namely, the In to Out periodic small signal transfer function. It is assumed that the effects of the small signal perturbation can be considered as additive with respect to the large signal ones. This small signal is applied at the In terminal and it is S&H by commuting S1 at 100 kHz. This switch is “ideal” but for its on and off resistance. The sampled version of the analog signal is amplified 10 times and applied to the ADC that codes the signal on the digital bus. The ADC is activated when the input signal has been sampled by the S&H. The digital signal is converted back by the DAC and then low pass filtered by R3 and C2. From the standpoint of the fundamental-matrix numerical computation, this circuit has the peculiarity of being characterised by several kinds of switching manifolds. If we assume an ideal S&H driving signal that is not affected by any jitter, the manifold related to S1 of S&H depends only on time (switching time instants) R2 R1 − R3 Out ADC DAC − S1 + In + C2 C1 − + s&h Fig. 11.6 The schematic of the analog to digital converter 1 Simulator PAN is available at the URL: http://brambilla.ws.dei.polimi.it. 266 F. Bizzarri et al. a b Fig. 11.7 The modulus of the spectra computed by the DSH based PAC analysis related to the analog conversion of one bit of the ADC (across the C2 capacitor) in Fig. 11.7a and to S&H (across the C1 capacitor) in Fig. 11.7b. x-axis: frequency of the small signal applied to In; y-axis: magnitude of the components of the spectra in dB and not on the electrical circuit variables. In this case there is no need to insert a saltation matrix. If the S&H driving signal depends on the electrical variables in some way, saltation matrices are needed. The second kind of manifold is related to the ADC, its digital output depends on the analog input, therefore saltation matrices must be introduced and contribution to the fundamental matrix must be handled in the digital portion of the circuit to allow the “reconstruction” of the small signal transfer function when the digitally elaborated signal is converted back as an analog signal. This is exactly what is done by the DAC; if conventional approaches are used, the incorrect variational model and fundamental matrix lead to the “isolation” of the small signal output at the Out node with respect to the driving small signal at In. Furthermore, the number of bits or levels used in the analog to digital conversion, as shown in the previous sections, determines the number of manifolds and how manifold traversal effects are handled by the digital portion of the circuit. We have simulated this circuit with DSH; after a steady state solution has been determined we applied the extended version of PAC [11, 20]. In Fig. 11.7 we show the modulus of the spectrum of the small signal voltage across the C2 capacitor (upper panel) and across the C1 one (lower panel). Being the variational model of the circuit time varying the spectra computed by the PAC are composed of the beats among the frequency of the small signal perturbation and the fundamental and harmonics of periodic functions contributing the entries of the Φ (1, 0) sensitivity matrix as shown in (11.38). The result shown in Fig. 11.7 refers to the beat between the DC components of Φ (1, 0) and the frequency of the small signal perturbation. The frequency of the small signal applied to In has been swept in the [10 Hz, 1 MHz] frequency interval. The S&H shapes the transfer function related to C1 that is largely influenced by the opening and closing of S1 at 100 kHz. The shape 11 Steady State Simulation of Mixed Analog/Digital Circuits 267 −40 −60 −80 −100 −120 −127:11 −137:11 −140 f 100 101 102 103 104 105 Fig. 11.8 The power spectral density of total noise at the Out node. The only considered sources of noise are the R1 and R2 resistors Rb Vdd In C1 Mp − + − Ra Op − Lo Out + Cmp + + Pwm − Mn C2 Co Vss R2 t Fig. 11.9 The schematic of the CLASS-D audio amplifier of the Out voltage spectrum is determined by the square pulses at the output of the DAC, whose time durations depend on α in (11.49), found in the solution of the variational model when the circuit is driven by the small signal. These pulses can have a very short duration with respect to the working period of the circuit. A correct determination of the periodic small signal transfer functions is an important aspect in the periodic noise analysis [10, 18–20]. To this end, assume to be interested in how noise generated for example by the R1 and R2 resistors affects the signal at pin Out. In our analysis, these resistors generate thermal and flicker noise; all the other elements of the circuit are assumed noiseless. We performed a periodic noise analysis based on DSH, the total noise power spectral density obtained at Out is shown in Fig. 11.8; we can appreciate the almost constant slope of −10 dB/dec due to flicker noise and the up conversion of noise near the fundamental and harmonics of the large signal input. The second considered circuit is shown in Fig. 11.9; it implements a CLASS-D audio amplifier. The input signal at node In is conditioned by the feed-back loop constituted by the Op operational amplifier, the Ra, Rb resistors and the C1 capacitor. The signal at the output of Op is compared by Cmp to the sawtooth waveform at the Pwm node. The model of the comparator is ideal, i.e. its output instantaneously switches between its upper and lower values. The output of Cmp drives the voltage 268 F. Bizzarri et al. a 1.5 0 −1.5 t[ms] 10 10.2 10.4 10.6 10.8 11 b 15 0 −15 t[ms] 10 10.2 10.4 10.6 10.8 11 c 1 0 −1 t[ms 10 10.2 10.4 10.6 10.8 11 Fig. 11.10 The waveform at the In node (Panel 11.10a), at the Out node (Panel 11.10b) and at the output of the Op operational amplifier (Panel 11.10c) controlled switches Mp and Mn. The models of these switches are such that Mn closes (its on resistance becomes equal to Ron ) when the driving signal is larger than a given threshold while Mp closes when the driving signal is less than this threshold. The sawtooth waveform at node Pwm has a period of 1 µs. The pulsed width modulated large signal (and power) is filtered by the LC filter composed of Lo and Co. The values of these elements have been chosen considering the impedance of the load (loudspeaker). The value of Rb has been chosen equal to 10 Ra in order to have an input/output gain of the CLASS-D amplifier equal to +20 dB. The amplifier has been driven at the In node by the Vin “ 2 sin(2π 103t) waveform (large signal). This circuit leads to a DAE model with a discontinuous vector field. In fact, by circuit inspection, we can see that the instantaneous switching of Cmp and of the driven Mp and Mn switches lead to a discontinuous voltage across Lo and to a discontinuous current through C1. Furthermore, the manifold characterising Cmp is voltage dependent, i.e. the time instant at which there is a commutation of Cmp depends on the instantaneous value assumed by the voltages at the output of Op and at the Pwn node. The steady state working condition has been computed once more with the DSH method. In Fig. 11.10 we report the driving waveform at In (upper panel), the output waveform at Out (center panel) and that at the output of the Op operational amplifier (lower panel). The apparent thick waveform at the output of Op is a graphical artifact due to the fact that the feedback signal is taken at the output of the Cmp comparator. As for the previous circuit we assume to be interested in the input/output small signal periodic transfer function of this CLASS-D amplifier when it is driven by a small signal that superimposes to the large signal. We thus performed once more an 11 Steady State Simulation of Mixed Analog/Digital Circuits 269 a 24 20 16 12 8 f 1 2 3 4 10 10 10 10 b 0 −40 −80 −120 f −160 101 102 10 3 104 Fig. 11.11 CLASS-D amplifier: the modulus of the input/output transfer function in Fig. 11.11a and its phase in Fig. 11.11b extended PAC analysis; Fig. 11.11 shows the obtained modulus (upper panel) and phase (lower panel) of the input/output periodic transfer function. As it can be seen from Fig. 11.11 the modulus is “almost flat” till about 10 kHz then it exhibits a peak determined by the resonance of Lo and Co with the loading resistor (not shown in Fig. 11.11) and finally drops with a slope of −40 dB/dec due to the output filter. The values assumed by the phase is coherent with that of the modulus. References 1. Gielen G, Rutenbar R (2000) Computer-aided design of analog and mixed-signal integrated circuits. Proc IEEE 88(12):1825–1854 2. Hasan M, Shen H-H, Allee D, Pennell M (2000) A behavioral model of a 1.8-v flash a/d converter based on device parameters. IEEE Trans Comput Aided Des Integrated Circ Syst 19(1):69 –82 3. Malcovati P, Brigati S, Francesconi F, Maloberti F, Cusinato P, Baschirotto A (2003) Behavioral modeling of switched-capacitor sigma-delta modulators. IEEE Trans Circ Syst Fund Theor Appl 50(3):352–364 4. Chen K, Zhang W, Yu Z (2009) Behavioral model of wide band sigma-delta modulators for wlan application. In: New Trends in Information and Service Science, 2009. NISS ’09. International Conference on, 30 2009-July 2 2009, pp 597–602 5. Brambilla A, Premoli A (2001) Rigorous event-driven (red) analysis of large-scale nonlinear rc circuits. IEEE Trans Circ Syst Fund Theor Appl 48(8):938–946 6. Yun G, Ning P, Zaiwang D (2009) Mixed-signal modeling and analysis for a digital rf direct sampling mixer. In: 2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC, 2009, pp 623–627 7. Leblebici YS, Kang S (1993) Illiads: a fast timing and reliability simulator for digital mos circuits. IEEE Trans Comput Aided Des 12:1387–1402 8. Resve A, Brian A, Antao A, Singh J (1996) Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans Comput Aided Des Integrated Circ Syst 15(1):68–82 270 F. Bizzarri et al. 9. Okumura M, Sugawara T, Tanimoto H (1990) An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations. IEEE Trans Comput Aided Des Integrated Circ Syst 9:225–235 10. Telichevesky R, Kundert K, White J (1996) Efficient ac and noise analysis of two-tone rf circuits. In: DAC, 1996, pp 292–297 11. Brambilla A, Gruosso G, Redaelli MA, Storti-Gajani G, Caviglia D (2010) Improved small sig- nal analysis for circuits working in periodic steady state. IEEE Trans Circ Syst I 57(2):427–437 12. Kim J, Jones KD, Horowitz M (2007) Variable domain transformation for linear pac analysis of mixed-signal systems. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2007, pp 887–894 13. Hiskens I, Pai M (2000) Trajectory sensitivity analysis of hybrid systems. IEEE Trans Circ Syst Fund Theor Appl 47(2):204–220 14. Giaouris D, Banerjee S, Zahawi B, Pickert V (2007) Control of fast scale bifurcations in power- factor correction converters. IEEE Trans Circ Syst Express Briefs 54(9):805–809 15. Giaouris D, Banerjee S, Zahawi B, Pickert V (2008) Stability analysis of the continuous- conduction-mode buck converter via filippov’s method. IEEE Trans Circ Syst Regular Papers 55(4):1084–1096 16. Di Bernardo M, Budd C, Champneys A, Kowalczyk P (2008) Piecewise-smooth dynamical systems, theory and applications. Springer, London 17. Bizzarri F, Brambilla A, Gajani G.S. Steady state computation and noise analysis of analog mixed signal circuits. IEEE Trans Circ Syst I: Fundam Theory 18. Okumura M, Tanimoto H (1997) A time-domain method for numerical noise analysis of oscillators. In: Design automation conference 1997. Proceedings of the ASP-DAC ’97. Asia and South Pacific, January 28-31 1997, pp 477–482 19. Okumura M, Tanimoto H, Itakura T, Sugawara T (1993) Numerical noise analysis for nonlinear circuits with a periodic large signal excitation including cyclostationary noise sources. IEEE Trans Circ Syst Fund Theor Appl [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] 40(9):581–590 20. Brambilla A, Gruosso G, Redaelli AM, Storti Gajani G (2010) Periodic noise analysis of elec- tric circuits: artifacts, singularities and a numerical method. J Circ Theor Appl 38(7):689–708 21. Aprille T, Trick T (1972) Steady-state analysis of nonlinear circuits with periodic inputs. Proc IEEE 60:108–114 22. Brambilla A, Gruosso G, Storti Gajani G (2010) Fssa: fast steady-state algorithm for the analysis of mixed analog/digital circuits. IEEE Trans CAD 29(4):528–537 23. Farkas M (1994) Periodic motions. Springer, New York 24. Bizzarri F, Brambilla A, Gajani G (2011) Phase noise simulation in analog mixed signal circuits: an application to pulse energy oscillators. IEEE Trans Circ Syst Express Briefs 58(3):154–158 Chapter 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale Technologies Fernando Coito, Helena Fino, and Pedro Pereira 12.1 Introduction Radio frequency and analog/mixed-signal (RF and AMS) are essential and critical technologies for the rapidly growing wireless communications market [1]. The progressive scaling of CMOS technology towards nanometer sizes has made the implementation of highly integrated systems for the wireless communication systems possible. However it is widely recognised that as technology continues to scale down, the variability in process parameters may cause significant deviations in the device behaviour [2–5]. Various techniques such as silicon strain and high- K gate dielectric, among others, have been proposed as a way of maintaining the transistors performance in spite of the ever-diminishing device sizes [6]. These techniques, however, envisage the minimization of the active devices parameter’s variations. Further manufacturing variations should also be accounted for such as the dynamic variations and the interconnect variations. Dynamic variations are caused by fluctuations in the operation of the system, such as in the temperature caused by the existence of highly active blocks within the die. Finally interconnect variations relate fluctuations in metal width and spacing between conductor and the thickness of interlayer dielectrics [7, 8]. Among the RF realm, spiral inductor design and synthesis is still a major concern for analogue designers, since it involves the characterization of complex loss mechanisms in the metal and the substrate, and an ever demand for area reduction is needed [9]. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the development of multi-objective optimization based design methodologies yielding the generation of Pareto-optimal surfaces [9, 10]. F. Coito () • H. Fino • P. Pereira DEE, Faculdade de Ciˆencias e Tecnologia, UNL, Portugal e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 271 DOI 10.1007/978-1-4614-1383-7 12, © Springer Science+Business Media New York 2013 272 F. Coito et al. For the efficient generation of the Pareto surfaces, lumped scalable models have been largely employed for the characterization of integrated inductors [8–11]. The accuracy of the results obtained is strongly determined by the availability of accurate closed-form expressions for all the lumped elements. Although physics- based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. In this way, we may be selecting ideally optimal solutions in detriment of quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. To overcome this misleading, both solutions on the Pareto- optimum surface as well as quasi-optimum solutions should be considered. Finally information on the sensitivity to process parameter variations must be used for electing the best design solutions. In this chapter we propose a methodology for exploring the design space of integrated inductors based on the use of a Pareto extended surface. The evaluation of this extended set of sub-optimum solutions requires methods that are able to find, on the parameter space, the set of local optima, since solutions that are close to each other in the performance index space may be very distant in the design parameter space. Particle swarm optimization (PSO) is an effective method to perform global optimization and it has been successfully used [12] in the evaluation of the Pareto surface for the design of spiral inductors. In order to extend the use of PSO into finding the set of suboptimum solutions it is necessary to consider niching methods [13, 14]. Using PSO niching algorithms may become significantly more complex than the standard algorithm and a number of additional problem dependent parameters must be accounted for. As a way to avoid the additional complexity, we use the approach based in ring topology PSO proposed by [15]. In Sect. 2 this chapter presents a brief description of the adopted inductor model and then the influence the variability of each technological parameter on the inductor performance is justified. In Sect. 3 the PSO algorithm developed or the generation of the Pareto surface is introduced. Section 4 is dedicated to the optimization of the inductor and the evaluation on the robustness of the design solutions, against parameter variability. Finally, Sect. 5 offers the conclusions. 12.2 Sources of Variability in the Performance of Integrated Inductors As already pointed out the interconnect variations account for the fluctuations in the metal width, in the spacing between conductors and in the thickness of interlayer dielectrics. The influence of the fluctuations on the above mentioned parameter values, in both the inductor quality factor, Q, and inductance value, L, will be investigated. For a simple characterization of the inductor behavior the Pi-model, illustrated in Fig. 12.1, will be considered. 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 273 Fig. 12.1 Integrated spiral inductor: (a) Planar inductor pi-model, (b) Single metal layer inductor metal width variation Δw Fig. 12.2 Square inductor geometric parameters For this model physics-based analytical expressions have been proposed for the evaluation of the lumped elements. For the evaluation of the inductance, Ls , the Modified Wheeler formula is used [11], where k1 µ0 n2 davg Ls “ , (12.1) (1 + k2ρ ) given that (dout − din) ρ“ , (dout − din) davg “ 0.5(dout + din), dout “ din + 2nw + 2(n − 1)s. (12.2) Where, n is the number of turns, s is the track-to-track distance, and w is the track width, as represented in Fig. 12.2. Finally, k1 and k2 , are coefficients allowing the model to be adapted to several inductor shapes [11]. 274 F. Coito et al. The evaluation of the spiral resistance, Rs , is obtained by b Rs “ R2dc + R2ac . (12.3) Where, l Rdc “ , (12.4) (σ wt) kRhf “ kl Rac “ . (12.5) (2σ δ (w + t)) And k is a correction factor and takes the value 1.2, σ and t are the metal conductivity and thickness, respectively. The metal length, l, is obtained with [16] π l “ Nside davg n tan . (12.6) Nside And the skin depth, δ , can be determined by [17] 1 δ“? (12.7) σ µπ f For the evaluation of the capacitance, Cs , all overlap capacitances are considered and given by [18] nc w2 εox Cs “ . (12.8) toxM1−M2 Where εox is the oxide permittivity, nc is the number of overlaps and toxM1−M2 is the oxide thickness between the spiral upper and lower metal. The parasitic capacitance, Cox , between the spiral metal and the silicon substrate, is estimated with [18] 0.5 l w εox Cox “ . (12.9) tox Where tox is the thickness of the SiO2 between the inductor and the substrate and lw defines the area of the spiral. Finally the Substrate resistance, Rsi , and capacitance Csi , are obtained with [18] 2 hsi Rsi “ . (12.10) (l w σsi ) 0.5 l w εo εr Csi “ . (12.11) hsi The expression of the quality factor becomes [19] ⎛ ⎞ C p R2s w Ls ⎜ Rp − ω LsC p . 2 ⎟ Q“ ⎜ 2 ⎠ 1− ⎟ (12.12) Rs ⎝ Ls R p + wRLs s + 1 Rs 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 275 Fig. 12.3 Process variables impact on inductor quality factor and inductance Where Rsi (Cox + Csi )2 1 Rp “ + . (12.13) ω 2Cox 2 R si 2 Cox 1 + ω 2(Cox + Csi )Csi R2si C p “ Cox . (12.14) 1 + ω 2(Cox + Csi )2 R2si From the above expressions the influence of the interconnect variations in the inductor behavior may be inferred. In Fig. 12.3, a graphical representation of the dependency of the inductors performance functions, i.e., L and Q, on fluctuations of technological parameters values is illustrated. As we may conclude the variability of the oxide thickness, tox , will cause fluctuations on Cox . Metal thickness, t, will be reflected in Rs only. Finally, the metal width, w, will influence all the elements of the Pi-model. For a quantitative evaluation of the influence of each technological parameter on the inductor behavior, sensitivity analysis must be performed. Yet, for the sake of simplicity, only the influence of metal width will be considered in this chapter. 12.3 Multi-Objective Particle Swarm Optimization The general multi-objective optimization problem is posed as follows [20]: Minimize F(x) “ [ f1 (x), f2 (x), ¨ ¨ ¨ , fn (x)]T . (12.15) x Subject to g j ≤ 0( j “ 1, 2, . . . , m), and hi “ 0(i “ 1, 2, . . . , q). 276 F. Coito et al. Where n is the number of objective functions, m is the number of inequality constraints, and q is the number of equality constraints. x “ (x1 , x2 , . . . , xD ) is a vector of D real valued independent design parameters (also called decision variables). F(x)is a vector of real valued performance indexes. The feasible design space is the set X “ {x : g j ≤ 0, j “ 1, 2, . . . , m; and hi “ 0, i “ 1, 2, . . . , q}. As opposed to what happens in single-objective optimization, in general there is no single solution to a multi-objective optimization problem. Usually, the optimization result is a set of points on the design space all of them fitting a certain definition of optimum known as Pareto optimality. Let us start by defining the concept of dominance between two vectors. x1 weakly dominates x2 : x1 x2 iff ∀i : fi (x1 ) ≤ fi (x2 ). (12.16) x1 dominates x2 : x1 ≺ x2 iff ∀i : fi (x1 ) ≤ fi (x2 ) and ∃i : fi (x1 ) < fi (x2 ) (12.17) This leads to the concept of Pareto Optimal solution: A point x∗ is Pareto optimal if there is no x ∈ X for which x ≺ x∗ (12.18) The Pareto optimal set (P) is the set of all non-dominated solutions, and the Pareto front is: PF “ {u “ F(x) : x ∈ P}. The Pareto front corresponds to the best possible trade-off between the n performance indexes. It is not possible to improve one of the performance indexes fi (x) without degrading some other. Therefore the goal for a global multi-objective optimization algorithm is to determine the Pareto set and the Pareto front associated to the problem under analysis. Evolutionary strategies aim to improve on the performance of random searches for points of optimality. This is accomplished by the identification of regions containing good designs and assuming that searches in the region of good designs may uncover further improved designs. Different strategies are used to identify and explore regions with a high probability of improved candidate solutions. These strategies distinguish between different evolutionary computation algorithms. Particle Swarm Optimization (PSO) is an efficient optimization method for constrained or unconstrained single objective optimization. More recently it has gained an increasing interest as a means of solving multi-objective optimization problems [12–14, 21, 22]. PSO is inspired by studies on the social behavior of insects and animals [23, 24]. A population of particles is made to evolve within the parameter search space. Each particle position x corresponds to a candidate solution for the optimization problem. As the population evolves the particles are guided towards the most promising region within the parameter search space. 12.3.1 The Canonical PSO Algorithm In this section the canonical PSO algorithm is addressed. Therefore we will focus on the case where a single performance index is considered (F(x) is scalar). 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 277 Fig. 12.4 PSO flowchart Its velocity determines a particle progress within the search space. At each moment this velocity depends on the particle’s current position, on the best position it has found so far, and on the best position found by all the other particles on the swarm [25], as given by vik+1 “ α vik + c1 rand1 pik − xik + c2 rand(pgk − xik ). (12.19) xik+1 “ xik + vik+1 . (12.20) Where vik is the ith particle velocity vector at iteration k, pik is the best position the g particle has found up to that iteration and pk is the best position found by the swarm (global best); rand1 and rand2 are D-dimensional column vectors whose elements are independent random numbers, uniformly distributed in the range [0,1]; α, c1 and c2 are coefficients (> 0). The basic flowchart for the canonical PSO algorithm is presented in Fig. 12.4. Each particle is initialized with a random position and velocity. At every iteration each particle position is assessed through the performance index. The particle keeps 278 F. Coito et al. track of the best position it has found so far (pik ). The swarm keeps track of the best position ever found by any particle (pgk ). As the algorithm evolves the particles are attracted towards a single global solution. 12.3.2 PSO and Discrete Search Space Like most nonlinear optimization methods, the canonical PSO algorithm assumes that the parameters defining the search space are continuous variables. However, technical constraints may restrict the values that can be used for the design parameters, confining them to discrete valued sets, therefore leading to a discrete search space. The set of technical constraints used on the design of the Spiral Inductor is presented in Table 12.1. While the values for w and din are only incremented with steps of 0.25µ m, the number of spires of the inductor may only be increased by integer values. As for the inductor shape only three types are considered (square, hexagonal and octagonal). Expressions (12.19) and (12.20) do not account for this discrete nature of the design parameters. The problem is illustrated in Fig. 12.5 for a one-dimensional search space. Minimizing the function on the continuous space yields xˆ as the optimum. It’s nearest discretized value is xˆd . However, the optimal feasible value corresponds to x∗d . To insure that the solution yielded by the algorithm is in fact optimal, it is necessary to force the particles to move only over this discrete search set. Therefore instead of (12.20) the new particle position is computed according to xik+1 “ round xik + vik+1 . (12.21) Table 12.1 Spiral inductor Parameter Min Step Max design constraints w(µ m) 5.0 0.25 1.0 din (µ m) 20.0 0.25 2.0 N 1.5 1.0 15.5 Nside Square (4)/ Hexagonal (6) / Octagonal (8) Fig. 12.5 Effect of discretizing a continuous search space 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 279 Where round(x) replaces the value x by the nearest discretized value. It is relevant to notice that the particle’s performance must be evaluated only after its discretized position is computed. This guarantees that the optimal solution found by the PSO algorithm truly corresponds to a feasible solution. 12.3.3 Handling Multiple Objectives with PSO The simplicity from the canonical PSO algorithm makes it a candidate method for multi-objective optimization. However, the algorithm is not truly fit for the task. Its focus is the determination of a single optimal solution, while there is no absolute global optimum in a multi-objective performance index. Usually it is not possible to define a single best position either for a particle (pik ) or for the entire swarm (pgk ). Due to its point-centered features the algorithm is unable to locate the Pareto front. Therefore, it is necessary to modify the basic algorithm. Examples of such modi- fications may be found in [13, 14, 21, 22, 26–28]. In the modified versions the search for a global best is replaced by the search for a set of non-dominated solutions, defining the Pareto front. The speed of each particle is updated using one of the non-dominated positions instead of the global best pgk . Different algorithms take different approaches on how to select each non-dominated position. Algorithms also differ on how particle positions integrating the non-dominated set, are determined at each iteration. 12.3.3.1 The Dual-Objective PSO Algorithm for Inductor Design The optimization scheme has two simultaneous objectives • To maximize the inductors quality factor(Q). |Ls −Lspecified | • To minimize the designed inductance deviation Lspecified . These objectives may not be simultaneously fulfilled as improving the inductors precision generally leads to a decrease on the quality factor. Therefore the goal is to find the points in the search space that reflect the optimum trade-off between the two goals. The two objective functions define a two-dimensional value space. The Pareto front is a line in this space, corresponding to the boundary of the region where the feasible performance values lie. To minimize the inductance deviation while maximizing the quality factor, this boundary is located at the top left side of the feasible region (Fig. 12.6). This figure sketches a simple method to determine the points from the Pareto front proposed by [13]. The method starts by fixing the value for one of the performance values, and then optimizing the other performance index with this additional constrain. The result of this optimization yields a point on the Pareto. 280 F. Coito et al. Fig. 12.6 Example of a two-dimensional performance value space In Fig. 12.6 the inductance deviation values are fixed, and the optimization is performed over the quality factor. When the parameter values are chosen from a discrete set, the Pareto front is not a continuous boundary. In the discrete case, the Pareto front is composed by a set of isolated points (marked as “O”), as represented in Fig. 12.6. As the optimization problem cannot be solved with an equality goal on one of the performance index, an inequality constrain (≤) is used. 12.3.4 Design Results A group of particle swarms is used to determine the set of parameter combinations that yields the best compromise between precision and quality factor. One of the swarms aims to minimize the inductance deviation, with no constrain on Q. The other swarms aim to maximize Q, constrained by a maximum deviation allowed (devmax ). Three swarms are used with different values for devmax : 1%, 5% and 7%. The four swarms run simultaneously, allowing crossing information among them. When a particle from one of the swarms reaches a position, the performance indexes for all the swarms are evaluated. If one of these indexes is better than it’s corresponding global best, that global best position is updated. Each swarm is composed of 25 particles and runs for 6 iterations. The algorithm parameters are α “ 0.98, c1 “ 0.2 and c2 “ 0.1. The algorithm is run twice and the Pareto front results are merged. The best design results obtained by this procedure are illustrated in Fig. 12.7 and given in Table 12.2. Although the maximum deviation allowed for the inductance 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 281 Fig. 12.7 Best design results obtained by the group of four swarms Table 12.2 Best design results obtained by the group Inductor of 4 swarms Q Deviation (%) w (µm) din (µm) n Nside 15.51 0.39 11 55.25 5.5 4 15.09 0.27 10.75 55.5 5.5 4 15.08 0.13 10.75 55.75 5.5 4 12.48 0.02 9 60 5.5 4 10.63 0.6 6.75 78.75 5.5 8 design is 7%, the highest quality factor corresponds to an inductance deviation of only 0.4%. Higher values for Q are achieved only for a deviation larger than the 7% limit. 12.3.5 Features of the Canonical PSO Based Algorithm Table 12.2 shows that the top four results correspond to different combinatins of the same inductor structure, i.e., a square inductor with 5.5 turns. This is caused by the fast convergence of the PSO canonical algorithm towards pg . It also leads the algorithm to miss some Pareto front optimal solutions that associated to different inductor structures. Table 12.3 presents two solutions which are not captured by the algorithm. This limitation is caused by an intrinsic property of the canonical PSO algorithm. When a particle position reaches the global best (Xik “ pik “ k) the velocity update depends only on the inertia term α vik . Therefore, when a particle approaches the 282 F. Coito et al. Table 12.3 Pareto front Inductor points missed by the PSO Q Deviation (%) w (µm) din (µm) n Nside canonical algorithm 13.80 0.017 9 46.75 6.5 8 12.40 0.5 8.75 76.75 5.5 6 global best solution its velocity approaches zero, and the particle will, eventually, stop moving. As a result, the particle will converge to the best position found so far, without granting that the true global optimum has been reached. In fact it may not even correspond to a local optimum. We may therefore conclude that the canonical PSO based algorithm is able to find a set of good design solutions that allow establishing a compromise between the inductor’s precision and quality factor. However it does not find all the solutions that lie in the Pareto front. Furthermore, the performance indexes used for optimization may not fully represent all the features aimed by a designer. This stems from both the difficulty in formalizing some of the features as a performance index, and the computational burden that the analysis of some features may add to the algorithm. In these conditions, to obtain relevant design information requires the optimiza- tion algorithm to be able to provide not only optimal trade-off solutions, but also solutions the lie in the vicinity of the Pareto front (quasi-optimal solutions). Next section presents an example of such an algorithm. 12.4 Niching PSO Using Ring Topology 12.4.1 The Niching PSO Algorithm When multiple satisfactory solutions exist and it is difficult to define a performance index to do the selection, it is important to develop a method able to pick the set of satisfactory solutions, and not only finding global optimal ones. In this section satisfactory solutions are considered to be a sub-set of the optimization problem local optima. For sake of simplicity the method proposed uses a local best PSO algorithm based on a ring topology population map [15]. Let the swarm of particles be mapped on to a ring topology as presented in Fig. 12.8. Each particle’s search movement is driven by it’s own (pik ) position, and g,i by a group best position (pk ), which takes the place of the global best used in expression (12.19). g,i The evaluation of each particle group best (pk ) takes into account the personal best positions from its direct neighbours. For example, the personal best of particle 3 (pg,3 2 3 4 k ) is determined from the set {pk , pk , pk }. The fact that each particle interacts only with its two neighbours slows down the communication within the swarm. As shown in [15, 24] this leads the particles to associate in clusters around the local optima, instead of converging to a single point. 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 283 Fig. 12.8 PSO swarm ring topology with six particles Slow communication is a desirable feature on algorithms that aim to locate multiple optima as it allows the particles to thoroughly search in its local neighbourhood. When the algorithm stops the set of group best positions {pg,i k : 1 “ 1, . . ., n} corresponds to the set of local optimal solutions. 12.4.2 Design Results To deal with the dual-objective problem two different swarms are used. One of them aims to minimize the inductance deviation. The goal of the second swarm is to maximize the quality factor, constrained to a 5% maximum inductance deviation. Each swarm is composed of two particles and runs for four iterations. The algorithm parameters are α “ 0.75 and c1 “ c2 “ 0.3. The local optima found by the two swarms are merged in Fig. 12.9. Table 12.4 presents the extended-Pareto front containing the non-dominated set of solutions (shaded rows) as well as a set of quasi-optimal solutions. Only solutions correspond- ing to a precision under 2.5% are presented. Only five of the displayed solutions are non-dominated solutions (marked as O in the figure). For all the other solutions it is possible to increase the quality factor without losing precision (or vice-versa). From a Pareto-optimal approach these five solutions correspond to the set from which the designer ought to select. 12.4.3 Analysis of the Robustness to Parameter Variation In this section the effect of parameter uncertainty is integrated on the optimization results analysis. It is assumed that the implemented values for the track width (w) 284 F. Coito et al. Fig. 12.9 Local optima obtained by the niching PSO algorithm Table 12.4 Extended-pareto front Inductor Q deviation (%) w (µm) din (µm) n Nside 15.49 0.78 11.00 55.5 5.5 4 15.08 0.13 10.75 55.75 5.5 4 14.66 0.12 10.5 56.25 5.5 4 14.23 0.43 9.25 46.25 6.5 8 13.81 0.46 9.25 75.00 5.5 8 13.80 0.02 9.00 46.75 6.5 8 13.40 0.20 9.25 47.00 6.5 6 13.39 0.06 8.75 47.5 6.5 8 12.99 0.12 8.5 48.25 6.5 8 12.72 0.16 9.00 76.25 5.5 6 12.62 0.20 8.25 48.75 6.5 8 12.40 0.005 8.75 76.75 5.5 6 12.25 0.02 8.5 49.00 6.5 6 11.83 0.20 7.75 77.75 5.5 8 11.70 0.27 8.75 97.00 4.5 4 11.24 0.22 8.00 62.00 5.5 4 11.23 0.05 7.75 51.00 6.5 6 10.18 0.16 6.5 32.5 7.5 8 9.54 0.03 6.00 34.25 7.5 8 9.28 0.05 6.25 34.25 7.5 6 and the internal diameter (din ) may differ from the design values. The maximum tolerance for each of these parameters is taken to be equal to half the value of the design parameter step from Table 12.1. The values for Q and Inductance precision are re-evaluated taking into account the above-mentioned tolerances, for each local optima presented in Fig. 12.9. It is assumed that, in the vicinity of each local optimum, both Q and the inductance precision show a monotonic behaviour. Therefore, using a worst-case approach, the 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 285 Fig. 12.10 (a) Local optima. (b) Worst-case robustness results for the local optima largest deviation from the nominal performance will be found on the boundary of the region defined by {x: x ∈ pg,i ± [0.125, 0.125, 0, 0]}, where pg,i is a local optimum. For each of the local optima, Q and inductance deviation are computed at the corners of the region. The worst performance values are used to characterize the inductor. The results from this procedure are presented in Fig. 12.10b. Not surprisingly, the worst-case inductance deviation values are larger than in the error free case. More relevant, however, is the fact that not all the solutions, which are non-dominated in the error free, case (Fig. 12.10a) also stay non-dominated in Fig. 12.10b. Therefore, an optimal design choice may lead to a less than optimal implementation. Results from Fig. 12.11 show that, after implementation, some of the error free quasi-optimal solutions may correspond to a better trade-off than other taken from the nominal optima. Therefore, the set of solutions presented to the designer should be composed not only by the non-dominated optimal set, butinclude the quasi- optimal solutions as well. It is, of course, possible to integrate the proposed procedure in the optimization algorithm. However the procedure will heavily increase the overall computational burden. Hence it is preferable to use it to post-process only the optimization solutions. 12.5 Conclusions In this chapter a multi-objective optimization based methodology for the design of integrated inductors is described. The necessity for obtaining design solutions robust against the technological parameters variability has led to a new methodology 286 F. Coito et al. Fig. 12.11 Location on the local optima plane (a) of the worst-case non-dominated solutions (b) where an extended-Pareto surface is generated. This extended-Pareto front contains both optima solutions and quasi-optimum solutions. Finally information on the robustness against process parameter variations is used for electing the best design solutions. References 1. International Technology Roadmap for Semiconductors, http://public.itrs.net 2. Chan HHY, ZZilic Z Modeling layout effects for sensitivity-based analog circuit optimization. In: Proceedings of ISQED’2005, pp 390–395 3. Kuo C.-C, Lee M.-J, Liu C.-N, Huang C.-J (2009) Fast statistical analysis of process variation effects using accurate pll behavioral models. IEEE Trans Circ Syst-I, Regulas papers 56(6):1160–1172 4. Sapatnekar SS (2011) Ovecoming variations in nanometer-scale technlogies. IEEE Transac- tions on Emerging and Selected Topics in Cicuits an Systems 1(1):5–18 5. Elie Maricau, Georges Gielen (2011) Computer-aided analog circuit design for reliability in nanometer CMOS. IEEE Transactions on Emerging and Selected Topics in Cicuits an Systems 1(1):50–58 6. Shah D, Siva K, Girishankar G, Nagaaj NS (2006) Optimizing interconnect for performance in standard cell library. In: Proceedings of IEEE Asian Pacific Conference on Circuits and Systems. doi: 10.1109/APCCAS.2006.342397 7. Bi Y, Siva K, Schilders WHA (2007) Effects of manufacturing variability on integrated passive components. In: Proceedings of IEEE ProRISC workshop on Circuits, Systems and Signal Processing, Veldhoven (NL) Nov 2007 ISBN 978–90–73461–49–9 8. Bi Y, Siva K, Schilders WHA (2008) Process variation aware modeling of interconnect capacitance. In: Proceedings of IEEE ProRISC workshop on Circuits, Systems and Signal Processing, Veldhoven STW, Veldhoven (NL) Nov 2008 12 Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale. . . 287 9. Nieuwoudt A, Massoud Y (2006) Variability-aware multilevel integrated spiral inductor synthesis. IEEE Trans Comput Aided Des Integrated Circ Syst 25(12):2613–2625 10. Schmedt BD, Gielen G (2003) WATSON: design space boundary exploration and model generation for analog and RFIC design. IEEE Trans Comput Aided Des Integrated Circ Syst 22(2):213–224 11. Mohan S, Hershenson M, Boyd S, Lee T (1999) Simple accurate expressions for planar spiral inductances. IEEE J Solid State Circ 34(10):1419–1424 12. Goudos SK, Sahalos JN (2006) Microwave absorber optimal design using multi-objective parti- cle swarm optimization Microw Optic Technol Lett 48(8):1553–1558 doi: 10.1002/mop.21727 13. Hu X, Eberhart R (2002) Multiobjective optimization using dynamic neighborhood particle swarm optimization. Proc 22 Congr Evol Comput 2:1677–1681 doi: 10.1109/CEC.22.14494 14. Coello CAC, Pulido GT, Lechuga MS (2004) Handling multiple objectives with particle swarm optimization. IEEE Trans Evolut Comput 8(3):256–279 doi: 10.1109/TEVC.24. 826067 15. Li X (2010) Niching without niching parameters: particle swarm optimization using a ring topology. IEEE Trans Evolut Comput 14(1):150–169 16. Allstot DJ, Choi K, Park J (2003) Parasitic-aware optimization of CMOS RF circuits. Kluwer Academic Publishers, ISBN 1–4020- 7399–2 17. Park M, Kim CH, Kim CS, et al (1999) Frequency-dependent series resistance of monolithic spiral inductors. IEEE Microwave Guided Lett 9(12):514–516 18. Murphy Olive H (2005) Advanced physical modelling of multilayer inductors for CMOS RF front-end applications. PhD Thesis, University College Cork - National University of Ireland 19. Patrick Yue C, Simon Wong S (1999) Design strategy of on-chip inductors for highly integrated RF systems. Invited Paper in Proceedings of the 1999 Design Automation Conference 982–987 20. Marler RT, Arora JS (2004) Survey of multi-objective optimization methods for engineering. Struct Multidiscip Optim 26:369–395 doi: 10.17/s158–3–0368–6 21. Daneshyari M, Yen GG (2011) Cultural-based multiobjective particle swarm optimization. IEEE Trans Syst Man Cybern 41(2):553–567 doi: 10.1109/TSMCB.2010.2068046 22. Li X (2004) Better spread and convergence: particle swarm multiobjective optimization using the maximin fitness function. In: Deb K et al. (eds) Genetic and evolutionary computation – GECCO 24, LNCS, Springer, Berlin/Heidelberg. doi: 10.17/978–3–540–24854–5 11 23. Kennedy J, Eberhart R (1995) Particle swarm optimization. Proc IEEE Int ConfNeural Netw 4:1942–1948 doi: 10.1109/ICNN.1995.488968 24. Kennedy J, Eberhart RC, Shi Y (2001) Swarm intelligence. Morgan Kaufmann, San Fran- cisco, CA 25. Evers GI, Ben Ghalia M (2009) Regrouping particle swarm optimization: a new global optimization algorithm with improved performance consistency across benchmarks. Proc IEEE Int Conf Syst Man Cybern 3901–3908 doi: 10.1109/ICSMC.2009.5346625 26. Abido M (2010) Multiobjective particle swarm optimization with nondominated local and global sets. Natural Computing 9:747–766 doi: 10.17/s11047–9–9171–7 27. Lechuga SM, Rowe JE (2002) Particle swarm optimization and fitness sharing to solve multi- objective optimization problems. Proceedings of 25 IEEE Congr Evol Comput 2:1204–1211 doi: 10.1109/CEC.25.1554827 28. Pires ES, Oliveira PM, Machado JT (2005) Multi-objective MaxiMin sorting scheme. In: Coello CC, Aguirre AH, Eckart Z (eds) Evolutionary multi-criterion optimization, LNCS, Springer, Berlin/Heidelberg doi: 10.17/978–3–540–31880–4 12 Chapter 13 A Survey on the Static and Dynamic Translinear Paradigm Rafael Vargas-Bernal and Carlos A. De La Cruz Blas 13.1 Introduction Nowadays, electronic designers are facing up the analog design using low-supply- voltages and low power consumption to fulfill the requirements of technology and portable applications. The VLSI technology is leaded by the CMOS processes due to the suitability for digital design and their lower cost than other fabrication processes involving BJT transistors. In this scenario, the new trends are to reduce the transistor length to increase the integration density and speed. Moreover, these characteristics allow implementing more sophisticated systems in less chip area to be exploited, for instance, in portable equipment. The size of silicon devices has decreased at a fairly steady rate by factor of about 100, since the invention of the integrated circuit (IC). Such reduction is making that the fabrication processes are moving to constant-field scaling instead of constant–voltage scaling, to reduce power consumption and to obtain an adequate performance of the integrated devices. The goal is mainly to avoid the breakdown of the thin gate-oxide insulator of the submicron process. However, this approach also requires diminishing the supply voltage by the same scaling factor. Besides, the threshold voltage is not reduced by the same ratio that scaling factor to avoid high leakage currents in the digital implementations. Therefore, analog designers are investigating novel techniques or revisiting the known procedures to design high performance mixed signal designs according to these new trends, i.e., very low voltage operation. R. Vargas-Bernal () Departamento de Ingenier´ıa en Materiales, Instituto Tecnol´ogico Superior de Irapuato, Carretera Irapuato-Silao Km. 12.5, Irapuato, Guanajuato, C.P. 36821, Mexico e-mail: [email protected] C.A. De La Cruz Blas Departamento de Ingenier´ıa El´ectrica y Electr´onica, Universidad P´ublica de Navarra, Campus Arrosad´ıa, Pamplona, Navarra, Espa˜na, C.P. 31006, Spain e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 289 DOI 10.1007/978-1-4614-1383-7 13, © Springer Science+Business Media New York 2013 290 R. Vargas-Bernal and C.A. De La Cruz Blas Within these strategies, the main issues are operation of the MOS transistors with the minimum voltage available, rail-to-rail input and output voltages and that the internal voltage swings have to be as small as possible with maximum dynamic ranges and bandwidths. Obviously, a trade-off among these parameters exists, thus the optimal implementation will depend on the specifications of the design. For instance, current-mode processing exploits the signal-handling capability of currents, whereas voltages are nonlinearly related to circuit currents according to their inherent compression law, for MOS and bipolar junction transistors (BJTs). In this way, the signal dynamic range becomes less influenced by a reduction in supply voltage. Translinear (TL) loops fall into this category, and it is based on large-signal behavior, exploiting a wide set of regions of operation of MOS transistors, thus, making it an interesting alternative for nonlinear and linear current-mode signal processing in the current scenario of IC analog design. TL loops are formed by a special transistor topology, where the devices can oper- ate in different regions of operation providing different linear–nonlinear processing; besides with the addition of capacitors, it is possible to form dynamic systems which can operate linearly or nonlinearly. Thus, when BJT transistors or CMOS in weak inversion are used the circuits are known as log-domain circuits; when CMOS are operating in the quasi-quadratic law, they are called square-root domain circuits. The main contribution of translinear circuits is the fast and efficient realization of many analog nonlinear signal processing functions with small quantities of MOS transistors [1, 5, 7, 14–18, 21–23, 25–30, 32, 33, 35–40], BJTs [2, 4, 8, 12–14, 20, 24, 31, 32, 34, 35], BJT/HBTs [10], floating-gate MOS transistors [3, 6, 11, 19] or ISFETs [9,52,53,66,80]. Also, TL circuits have several advantages: high frequency operation, tuneability, low supply voltage, lower-power consumption, low noise, low third order intermodulation distortion, low total harmonic distortion, the immunity to body effects, extended dynamic range, compactness, design modularity, and low circuit complexity. The content of this chapter is as follows: Section 13.1 describes the interest in reviewing the state-of-art of this paradigm used for designing analog signal processing applications based on low-voltage and low-power. The static translinear principle is analyzed in Sect. 13.2, where translinear circuits based on BJTs, MOS transistors, and FMOS transistors can be used under different operation regions (strong inversion, triode, weak inversion). In Sect. 13.3, the dynamic translinear paradigm is firstly described in a generic way, then particularized to log-domain applications and square-root domain circuits. In addition, the dynamic nonlinear building blocks are studied with the aim of presenting different strategies of design that have been used in dynamic translinear circuits. A lot of work can still be realized on TL circuits, nevertheless, the huge advances achieved until now, and this is addressed in Sect. 13.4. In Sect. 13.5, a set of applications in analog signal processing are enumerated and related with the corresponding papers that have been published until now. Finally, conclusions associated with this study are given in Sect. 13.6. 13 A Survey on the Static and Dynamic Translinear Paradigm 291 13.2 Static Translinear Paradigm A translinear circuit (TC) is a current-mode circuit based on non-linear current–voltage characteristic of the input port, which carries out its function using the translinear principle. The term translinear was first introduced by Gilbert in 1975, underlining the fact that transconductance gm is linear with current, for the case of BJT and MOS transistors in weak inversion. However, when transconductance is linear and voltage are used, another class of TCs based on quasi-quadratic law are obtained. The translinear principle (TP) consists in that a closed loop including an even number of translinear elements are arranged of manner that an equal number of them are placed clockwise (CW ) and the rest in counter-clockwise (CCW ). For the case of BJT transistors, the translinear loop (TL) is formed by the series connexion of base-emitter junctions, while ports gate and source are used in MOS transistors. Therefore, the non-linear relationship of the currents circulating through the CW elements equals the non-linear relationship of the currents circulating through the CCW elements. The translinear elements can be implemented by means of BJTs, MOS transistors, and FGMOS transistors. For the case of BJT transistors, and MOS transistors in weak inversion such a non-linear relationships is a product. For the case of MOS transistors working in the saturation region; it is a sum of current square-root. Both operations plus MOS transistors working in triode will be explained in the following sections. Three basic configurations for forming TL loops can be implemented: (1) alter- nating cell (elements with different type of transistor are interconnected one to one in the TL), (2) balanced cell or stacked cell (elements with similar type of transistor are interconnected first, after the rest of transistors of the other type are joined to the TL) or (3) electronically simulated o tunable cell (elements are operated by adjusting the gate voltages making possible to cancel the possible circuit nonlinearity caused by the input voltages). These topologies are shown in Fig. 13.1 for n-channel MOS transistors, using a TL of four transistors for the case of Fig. 13.1a, and Fig. 13.1b. For the case of Fig. 13.1c; a floating gate realization is shown, since with these devices the extra circuitry to force the gate voltages is notably reduced. a b c Fig. 13.1 Topologies of translinear circuits: (a) alternating, (b) balanced, and (c) electronically simulated 292 R. Vargas-Bernal and C.A. De La Cruz Blas Fig. 13.2 Translinear circuits based on bipolar transistors TCs are classified in two main groups: static translinear circuits (STCs) and dynamic translinear circuits (DTCs) [32]. STCs are used to implement linear and nonlinear transfer functions between the input and output of an analog circuit without the time as reference. Otherwise, DTCs can be used to obtain the same transfer functions but in these the frequency, phase or time dependence of the input signals is used as reference to manipulate the desired outputs. In the following subsections, the main nonlinear TL characteristics of MOS and BJT transistors will be introduced; but only from a mathematically and described point of view; since the pages number available for this chapter is limited, and there is not room to present the bias circuits required to force the input–output currents, thus, the readers are directed to References. 13.2.1 Translinear Circuits Based on Bipolar Junction Transistors A bipolar junction transistor (BJT) is a three-terminal bidirectional electronic device used in the first generation of translinear circuits. Its terminals are called collector (C), base (B), and emitter (E) and has two junctions called: base–emitter (BE) and base–collector (BC). The collector–emitter (CE) current or output current is controlled by the BE current (current control), or by the BE voltage (voltage control). The translinear principle exploits the exponential or logarithmic relationships between the base–emitter voltage (VBE ) and the collector current (IC ), which is holded for almost five decades of current, and it is expressed as: VBE IC IC “ IS exp or VBE “ VT ln (13.1) VT IS where IS is the saturation current, and VT is the thermal voltage of the device, respectively. A translinear circuit based on BJTs is illustrated in Fig. 13.2. Consider a general translinear circuit composed by i NPN transistors, and j PNP transistors in each direction, respectively. By applying the definition of the translinear principle given previously, then it can generically be established as: ∑ VBE i + ∑ VEB j “ ∑ VBE i + ∑ VEB j (13.2) i∈{CW } j∈{CW } i∈{CCW } j∈{CCW } 13 A Survey on the Static and Dynamic Translinear Paradigm 293 or I IC I IC ∑ VT ln Ci ISn + ∑ VT ln j IS p “ ∑ VT ln Ci ISn + ∑ VT ln j IS p i∈{CW } j∈{CW} i∈{CCW } j∈{CCW } (13.3) where ICi and IC j are the collector currents associated with each transistor, and Isn and Is p are NPN and PNP saturation currents of the transistors, respectively. A simplification process to (13.3) is realized as follows: VT can be omitted in all terms, and the sum of terms with natural logarithm can be replaced by products of currents. In addition, if all transistors are equal and k “ i + j is the number of junctions in each direction, then the translinear principle can be simplified as: ICi IC j ICi IC j ∏ I I “ ∏ I I or ∏ ICk “ ∏ ICk . (13.4) (i, j)∈{CW } Sn S p (i, j)∈{CCW } Sn S p k∈{CW } k∈{CCW } Briefly, the biasing circuit of BJT TL circuits are easy, and a small number of transistors is needed for the implementations. Basically these circuits operate in Class-A, but replicating a forming proper input current the cell can operate in Class-AB. 13.2.2 Translinear Circuits Based on MOS Transistors In the following, we consider that MOS transistors follows the quasiquadratic law; however in the new CMOS process this law can be seriously affected; nevertheless increasing the channel length this law can be valid, so there is a trade-off between area and quasi-quadratic law. Also, this law can only be valid for 2 decades of current. A metal-oxide-semiconductor field-effect transistor or MOS transistor is a four-terminal unidirectional electronic device. Its terminals are called gate (G), drain (D), source (S), and bulk (B). The latter commonly is tied to ground and/or bias voltage, and therefore, it is not considered in current and voltage relationships of the device as electrical variable. A threshold voltage (Vth ) is the gate voltage necessary to form an inversion layer of carriers at the interface between the insulating layer (oxide) and the substrate (bulk) of the transistor, which have as aim to allow the flow of electrons or holes through the gate-source junction. MOSFETs have three operational modes: • Subthreshold or Weak-Inversion Mode VGS « Vth : There is a weak-inversion current o subthreshold leakage due a insignificant flow of electrons at the source to enter the channel and flow to the drain, which is an exponential function of gate-source voltage. The weak-inversion current IDS is expressed as: VGS − Vth IDS « ID0 exp (13.5) nVT 294 R. Vargas-Bernal and C.A. De La Cruz Blas where ID0 is the current at VGS “ Vth , i.e., ID0 “ IsW /L, VT is the thermal voltage equal to kT /q, and the slope factor n is given by n “ 1 + CD /Cox , where CD is the capacitance of the depletion layer, and Cox is the capacitance of the oxide layer per unit area. In this region of operating, the MOS transistors can be used in the same configuration of BJT TL loops. TL loops in weak inversion are used in artificial neural networks, log-domain filters [6, 7, 19, 28, 37, 38], multiplier/divider circuits [36], biochemical sensors [9], Lorenz oscillators [11], neural networks, and Σ Δ A/D converters [30]. This operation allows overall lower-power consumption for low-frequency applications [30], and the bulk terminal can be used to form an extra exponential relationship, which has not been fully exploited. • Triode, Ohmic or Linear Mode VGS > Vth and VDS < (VGS − Vth ): An electrical current between drain and source terminals occurs due to that a channel of electrical carriers is created. Such channel allows to the device to operate as a resistor controlled by the gate voltage relative to both the source and drain voltages. The drain-source current is expressed as: 2 VDS W IDS “ µ Cox (VGS − Vth )VDS − (13.6) L 2 where µ is the charge–carrier effective mobility, W is the gate width, and L is the gate length. • Saturation, Active or Strong-inversion Mode VGS > Vth and VDS > (VGS − Vth ): A current flow between drain and source through a broader, two- or three- dimensional current distribution extending away form the interface and deeper in the substrate, due to the difference higher between drain voltage and gate voltage. The drain-source current is expressed as: µ Cox W IDS “ (VGS − Vth )2 (1 + λ (VDS − VDSsat )) (13.7) 2 L where λ is the channel-length modulation parameter. The maximum value of IDS occurs when VDS “ VDSsat , and therefore, IDS is expressed as: µ Cox W IDS “ (VGS − Vth )2 . (13.8) 2 L A translinear circuit based on MOS transistors is illustrated in Fig. 13.1. 13.2.2.1 Translinear Principle for MOS Transistors in Strong Inversion Consider a general translinear circuit composed by i p-channel MOS transistors, and j n-channel MOS transistors in each direction, respectively. For MOS transistors working in strong inversion, the translinear principle can be expressed as: 13 A Survey on the Static and Dynamic Translinear Paradigm 295 ∑ VGSi + ∑ VSG j “ ∑ VGSi + ∑ VSG j (13.9) i∈{CW } j∈{CW } i∈{CCW } j∈{CCW } where d d 2IDS IDS VGS “ Vth + “ Vth + . (13.10) µ Cox WL K WL If identical MOS transistors are used, then (13.9) is reduced to: /c d 0 /c d 0 IDSi IDS j IDSi IDS j ∑ Kn ( W L )i + K p ( WL ) j “ ∑ Kn ( WL )i + K p ( WL ) j (13.11) (i, j)∈{CW } (i, j)∈{CCW } Equation (13.11) involves Kn and K p which are process dependent, but it can be simplified if only one type of MOS transistor is used as follows: d d d d IDS j IDS j IDS j IDS j ∑ W “ ∑ W or ∑ Sj “ ∑ Sj j∈{CW } L j j∈{CCW } L j j∈{CW } j∈{CCW } (13.12) where j is the number of translinear elements, and S “ W /L. TL loops in strong inversion are used to form translinear loops or translinear circuits in RMS-DC converters [3, 17], chaotic analog noise generators [5], a differentiator circuit [14], a flipped voltage followers (geometric-mean circuits and squarer/divider circuits) [16], square-root domain filters [18, 21–23], log domain filters [24, 25, 27, 28, 32, 40], integrators [26], oscillators [29], square-root circuits [33], squarer/dividers [33], and multiplier/divider circuits [33, 39]. Most of above references uses four transistors single loops for the cell implementation operating in Class-A, however in [3] multicoupled cells are proposed operating in Class- AB. These last procedure has no be generalized, and can be a challenge for a new research. 13.2.2.2 Translinear Principle for MOS Transistors in Triode To overcome the increased parametric mismatch and poor frequency response of translinear circuits operating in weak inversion, and the lack of differential outputs in translinear circuits working in strong inversion, in [58] it is proposed a novel scheme to develop translinear circuits in the triode region of MOS transistors. Consider a general translinear circuit composed by i p-channel MOS transistors working in triode, the translinear principle can be expressed as (13.9), where IDS VDS VGS “ + + Vth (13.13) µ Cox W L VDS 2 296 R. Vargas-Bernal and C.A. De La Cruz Blas Fig. 13.3 Translinear circuits based on FGMOS transistors If Vth is matched for all transistors, all transistor have the same dimensions, and VDS it is considered very small or equals in a first approximation, then the translinear principle can be expressed as: IDS j IDS j ∑ V “ ∑ V (13.14) j∈{CW } DS j j∈{CCW } DS j There are a few research works on [58]; and there is an open door for further implementations. One line to follow can combine triode MOS transistors with FGMOS. The circuits proposed in [58] are used to demonstrate the principle and the bias circuits, thus an optimized design of the circuits or simplifications can be desirable. 13.2.3 Translinear Circuits Based on FGMOS Transistors A floating gate MOSFET (FGMOS) was used in the third generation of translinear circuits, which is a field-effect transistor with a floating node in DC and a finite number of secondary gates or inputs which are electrically isolated of the floating gate (FG). Such inputs are only capacitively coupled to the FG, and therefore, this device is called a MITE (multiple-input translinear element) [102]. It has N inputs with an input voltage that can represented as a weighted summation, where Vn is the input voltage of the nth input and wn is the constant gain or weighting coefficient of the corresponding input wn “ (Cn /CT ), that is, partial capacitance between total capacitance, being Cn large to reduce nonlinear parasitic capacitances. The gate voltage for the case of MOS transistor can be expressed as: N VGS “ ∑ wnVn (13.15) n “1 A general translinear circuit based on FGMOS transistors is illustrated in Fig. 13.3. It is composed by a set of N input transistors labeled as FCW 1 to FCW N , and a set of M ouput transistors labeled as FCCW 1 to FCCW M . N input currents (ICW 1 , . . . , 13 A Survey on the Static and Dynamic Translinear Paradigm 297 ICW N ) bias to the N input transistors producing N drain voltages (VCW 1 , . . . , VCW N ) forming a N × N input connectivity matrix, CCW . CCW nk is a capacitive coupling between the drain of FCW k and the floating gate of FCW n . The circuit generates M output currents (ICCW 1 , . . . , ICCW M ) by combining the N drain voltages in a M × N output connectivity matrix, CCCW . CCCW mn is a capacitive coupling between the drain of FCW n and the floating gate of FCCW m . If all FGMOS transistors are identical and matrix CCW has inverse, then, the translinear principle for weak inversion and strong inversion, respectively can be expressed as: CCW CCCW ∏ ICCW “∏ ICW (13.16) a a CCW ICCW “ CCCW ICW (13.17) In strong inversion, ICCW is dependent of capacitive coupling as a multiplicative factor, while, in weak inversion, the ICCW is dependent of capacitive coupling as an exponent. FGMOS transistors provide versatility to TL principle leading simple bias circuitry, but the capacitors coupled to the gate lead to small bandwidth, and an increment in area. 13.3 Dynamic Translinear Paradigm The dynamic translinear principle is formed adding capacitors to the inputs and/or outputs of basic translinear components [32, 69, 76, 100]. It is possible implement all kinds of frequency-dependent or time-dependent linear transfer functions. The DTCs allow us to realize linear filters, and linear- and nonlinear differen- tial equations. These later has been used for realizing mixer-filter combinations, oscillators, phase-locked loops, syllabic companding filters, and chaos generators [84, 91, 95, 106]. In order to describe DTC, we will use an integrator as example, and the generalization of DTC can be found in References. Consider a translinear circuit represented by the block diagram shown in Fig. 13.4. The current inputs denoted as iin and i′ are supplied to a divider block, whose output current is denoted as I0 (iin /i′ ), where I0 is a normalizing constant. This current is integrated by means of the capacitor C, generating the voltage v. Next, the voltage v is introduced to the nonlinear block to produce two equal general output currents. One of such currents is supplied together with the voltage v to a derivative block, which generate the input current i′ that can be expressed as V0 (diout /dv), where V0 is a normalizing constant. Output currents can be expressed as iout “ f (v). Of the expression of i′ , it is possible to obtain an equation for the derivative of the output current: diout i′ “ (13.18) dv V0 298 R. Vargas-Bernal and C.A. De La Cruz Blas Fig. 13.4 Dynamic translinear principle The capacitor current is equal to the current generated by the divider, then dv iin Icap “ C “ I0 ′ , (13.19) dt i which can also be expressed as: dv I0 iin “ . (13.20) dt C i′ Equations (13.18) and (13.20) can be related by means of the chain rule as follows: diout diout dv “ . (13.21) dt dv dt By substituting (13.18) and (13.20) in (13.21), it can be rewritten as: diout i′ I0 iin I0 “ ′ “ iin (13.22) dt V0 C i V0C The output current can be obtained by integrating (13.22) with respect to the time: I0 iout “ iin dt (13.23) V0C Equations (13.18) to (13.23) are generals and can be used to implement different companding systems. If f in Fig. 13.4 is a exponential law the systems are called log-domain; and if f is the quasiquadratic law the systems are called square-root domain. Note that the divider can be implemented using static translinear circuits. For the case of log-domain usually only one loop of four elements is required, and for the square-root domain, at least 2 loops or 1 multi-coupled loop is necessary. 13 A Survey on the Static and Dynamic Translinear Paradigm 299 13.3.1 log-Domain Circuits log-Domain filters are a subclass of dynamic translinear circuits that develop linear transfer functions using exponential functions f in Fig. 13.4 [4, 6–8, 19, 20, 22– 25, 27–31, 34, 35, 38, 40, 42–47, 50–52, 54–56, 62, 65, 67, 70, 74, 75, 78, 81–98, 106]. The nonlinearity is directly exploited without depending on linearization. Thanks to overall linear behavior, they can be used in applications where are needed a large-signal linearity. These are also called as translinear filters, companding current-mode filters, or exponential state-space filters. Among the advantages that a log-domain filter offers are: (1) only transistors and capacitors are required for its implementation, and (2) for ultra low-power applications, the absence of resistors in the filters reduce the size of the VLSI design.The filters have been designed for four different approaches: Chebyshev [6, 19], Bessel [7], Elliptic [19, 24], and state- space synthesis [8,18,19,21,23,24,27,28,31,32,35,37,40]. Additionally, these filters have been implemented using topologies either ladder [6, 7, 19], multiple feedback [8, 14, 18, 19, 21, 23, 24, 27, 28, 31, 32, 35, 37, 40] or biquad [4, 22, 23, 34, 38]. 13.3.2 Square-Root Domain Circuits Among its advantages are: operation to low-voltage, operation to low-power, large dynamic range, high-frequency applications, and electronic tuneability. Until now, there are three different synthesis methods for square-root domain circuits: (1) state- space synthesis, (2) signal flow graph synthesis, and (3) the substitution of the LC ladder of the equivalent circuit by their square root domain equivalents. Through square-root domain circuits, it is possible to design state variable filters by means of one or more integrators connected in some feedback configuration, where each integrator represents one state and each output voltage of them is considered one state variable [14, 18, 21, 23, 26, 49, 73, 103, 104, 107]. The main advantages of these filters is that: (1) the use of different states as outputs generates different kinds of filters, (2) the circuit can directly realize the state-space models proposed, and (3) larger signal swings. A clear example of this type of filters is the Kerwin–Huelsman–Newcomb (KHN) biquad filter. 13.3.3 Dynamic Nonlinear Building Blocks Square-root circuits, squaring circuits, geometric-mean circuits, current conveyors, and/or squarer/divider circuits are the basic blocks for designing multiplier/divider circuits [1, 33, 36, 39]. Multipliers/dividers, squarers/dividers, geometric-mean circuits, square-root circuits, and/or squaring circuits are elemental to build a RMS-to-DC converter or a flipped voltage followers [2, 3, 16, 17]. The integrators, 300 R. Vargas-Bernal and C.A. De La Cruz Blas geometric-mean circuits, multipliers/dividers, logarithmic circuits, exponential circuits, square-root circuits, squarer/divider circuits, squaring circuits, current conveyors, and/or multipliers are fundamental elements of analog filters [4, 6, 7, 18, 19, 21–25, 27, 28, 31, 32, 34, 37, 38]. A harmonic mixer, modulators and frequency doublers can include multiplier circuits [10, 33]. A differentiator can contain geometric-mean circuit and multipliers [14, 15, 20]. Low-voltage current controlled current conveyor can be used as basic blocks to design current mode filters. An integrator can be designed by means of geometric-mean and multiplier/divider blocks [26, 32]. Oscillators can be based on translinear current conveyors, which have frequency of oscillation and the condition of oscillation controlled electronically, and independently of the bias current [13]. Also, the oscillators can have as elemental blocks analog filters, square-root circuits, squarer/divider circuits, and geometric mean circuits [14, 22, 27, 29]. Σ Δ A/D converters can be implemented using analog filters, and integrators as basic blocks [30]. 13.4 Open Research Lines In spite of the design advantage that TL systems provides; there are still some open research fields that requires investigation. Among these we can find, the noise performance, to find a systematic method to synthesize the cells; since now most of the proposals are based on four loop transistors. To explore another operation regions completing the possibility design, for example MOS transistor working in triode. Moreover also another TL structures can be explore for example CCII and diodes. Analog noise generators for applications such as cryptography systems (watermarking systems), and secure communications (spread spectrum) [5, 11] must be developed using controlled gain in the feedback loop and null intermittency effect, which only can be obtained by means of translinear circuits. In artificial neural networks, the use of translinear circuits is searching modularity, scalability, computational density, real time operation, and power efficiency. A lot of work related with these topics must be realized. Methods with the aim of reducing the errors generated by the second order effects in translinear loops have been discussed [1, 2, 6, 11, 17, 21, 30, 33, 34, 36–38], which are based in the changes in V–I relationship associated with the reduction of MOS transistors, smaller chip size and much higher operation frequencies. Between the effects before mentioned that must still be completely studied are body effects, mobility reduction, weak inversion, channel length modulation, component mismatch, parasitic resistances and capacitances, input and/or output resistance, multiple operating points (MOPs), waveform asymmetry, cycle limit, chaos, thermal noise, and temperature dependence of these parameters. The use of graph theory as a tool of design and analysis has been poorly exploited [60, 73, 108, 109]. In the future, these techniques will must be more used to verify and optimize the efficiency and performance of translinear circuits. 13 A Survey on the Static and Dynamic Translinear Paradigm 301 Although the companding technique permits the design of filters featuring small distortion levels, large signal-to-noise ratios, low supply voltages, and wide bandwidths, it may also give rise to externally-nonlinear behavior. The occurrence of unwanted limit-cycle behavior in log-domain filters is reported in [107] and investigated in [67]. The appearance of multiple operating points in such filters is discussed in [105]. So far, these nonlinear phenomena have been reported only in log-domain filters and more recently in instantaneously digital companding [55,78]. But the square root-domain filters may also suffer from external nonlinearity. In [104], a fully-differential class-AB second-order SRD filter is designed, and then modified according to a standard linear IC design technique, i.e. any pair of equal- value capacitors, each connected between a node and ground, is replaced with a single half-sized floating capacitor, placed between those nodes. This saves IC area, but may induce zero-input limit cycle behavior under particular conditions describe in [104]. 13.5 Applications This section is devoted to describe the applications that can be implemented by TL principle, but are not described in the previous sections: square-root circuits [1, 2, 14, 18, 21–23, 26, 27, 29, 33, 40, 49, 69, 73], squarer/divider circuits [1, 3, 17, 21, 22, 25, 33, 36, 39, 40, 57, 64, 72, 103], multiplier/divider circuits [1, 7, 19, 25, 26, 33, 36, 39, 57, 59, 72, 73], squaring circuits [2, 14, 16, 28, 29, 36, 69], geometric mean circuits [2, 3, 6, 7, 14, 17, 21, 22, 25, 26, 29, 36, 39, 40, 60, 70, 72, 73, 79, 83, 99], differentiators [6–8, 14, 20], integrators [4, 6, 15, 26, 31, 34, 45, 48, 51, 67, 70, 73, 83, 84, 86, 88, 90, 94, 96–98], filters low pass, high pass, band pass, all pass, notch, low pass notch, high pass notch, sinh, tanh, log-domain, square-root, wave, anti-aliasing, and adaptive filters) [4, 6–8, 14, 16, 18–25, 27, 28, 31, 32, 34, 35, 37, 38, 40, 43– 45,48–52,55,56,64,65,67,69–76,78,81–83,85–90,92,94–98,103,104], oscillators [11,14,16,22,27,29,43,46,47,80,91], multipliers [4,9,14,16,20,42,58,73], RMS- DC converters [2,3,16,17,69], modulators [33], harmonic mixers [10], phase shifters [41], sine/cosine synthesizers [13, 43, 63], fuzzy logic controllers [61, 77], artificial neural networks [61, 93], cryptography systems [5], chaotic analog noise generators [5,11,46,47,67,91], programmable gain current amplifiers [12,59,62,68,77,89,101], current conveyors [13], Σ Δ A/D converters [30, 77], frequency multipliers [41, 60, 63], exponential function converters [42,54], group-delay equalizers [44,48], divider circuits [53, 69, 83, 89], sensors [53, 66], RMS detectors [64], 2-D vector-magnitude circuits [69], 2-D vector-normalization circuits [69], defuzzifiers [77], one-quadrant multiply-reciprocal circuits [79], etc. Some of these cells are used as building blocks of the above applications. FGMOS retain a long time the injected charge in the gate and then weighted volt- age addition at the input terminals is a direct consequence. Such qualities provide attractive characteristics as accuracy, high-speed, and compactness. MITEs have specific applications [3,6,19,69,71,75,77,79,88] such as weighted average circuits 302 R. Vargas-Bernal and C.A. De La Cruz Blas for resistive networks, defuzzifiers, FIRs, common-mode feedback networks, sigma- delta modulators, log-domain filters, multipliers/dividers, integrators, square-root circuits, squaring circuits, one-quadrant divider circuits, 2-D vector-magnitude circuits, 2-D vector-normalization circuits, RMS-to-DC converters, geometric-mean circuits, and fast A/D and D/A converters. 13.6 Conclusions Translinear circuits use the large signal characteristic of transistors to implement static-dynamic systems, processing the signals nonlinearly. These systems are versatile, and can provide a very well solution in the current scenario of low voltage, low power, and high efficiency circuits. The chapter is a survey of the techniques that have been proposed in the last years; such techniques have been reviewed as a tutorial for beginners in the field, but it can be used as reference for researches since the number of publications and results are so many, that all the information cannot be acceded from only one source, and this is one of the objectives of this survey. Finally, some uncover topics, and new research lines were discussed in order to show a general frame of translinear circuits. Acknowledgements This work was supported by the Spanish Ministerio de Ciencia e Innovacion and the European Regional Development Fund (FEDER) under Grant TEC2010–21563-C02–01. The first author wish thank to their wife and son for your time to realize this study, and to PROMEP agreement 92434 for the support to this project. References 1. Menekay S et al (2009) Novel high-precision current-mode circuits based on the mos- translinear principle. AEU-Int J Electron Commun 63(11):992–997 2. Kaewdang K et al (2009) A translinear-based true RMS-to-DC converter using only NPN BJTs. AEU-Int J Electron Commun 63(4):472–477 3. Farshidi E et al (2008) A 1.2 V current-mode true RMS-DC converter based on the floating gate MOS translinear principle. Microelectron J 39(2):293–298 4. Tola AT et al (2008) Current mode high-frequency KHN filter employing differential class ab log domain integrator. AEU-Int J Electron Commun 63(7):600–608 5. D´ıaz-M´endez A et al (2009) Chaotic noise MOS generator based on logistic map. Microelec- tron J 40(3):638–640 6. Farshidi E (2010) Synthesis of class-AB log-domain filters based on nonlinear transconduc- tance. Microelectron J 41(5):266–276 7. Ip HMD et al (2009) A 19 nW analogue CMOS log-domain 6th-order bessel filter without E-minus cells. Microelectron J, 40(8):1170–1174 8. Kircay A et al (2006) Novel first-order differential Class-AB log-domain allpass filters. AEU- Int J Electron Commun 60(10):705–712 9. Shepherd L et al (2005) Weak inversion ISFETs for ultra-low power biochemical sensing and real-time analysis. Sens Actuators B Chem 107(1):468–473 13 A Survey on the Static and Dynamic Translinear Paradigm 303 10. Wu Y et al (2002) A SiGe HBT translinear harmonic mixer. Analog Integ Circuits Signal Process 31(1):65–67 11. Odame K et al (2009) Implementing the Lorenz oscillator with translinear elements. Analog Integr Circuits Signal Process 59(1):31–41 12. Tadi´c N et al (2011) A BJT translinear loop based optoelectronic integrated circuit with variable transimpedance for optical storage systems. Analog Integr Circuits Signal Process 66(2):293–298 13. Kumngern M et al (2010) Electronically tunable multiphase sinusoidal oscillator using translinear current conveyors. Analog Integr Circuits Signal Process 65(2):327–334 14. Loizos DN et al (2008) A translinear sige bicmos current-controlled oscillator with 80 Hz–800 MHz tuning range. Analog Integr Circuits Signal Process 57(1–2):107–115 15. Vlassis S et al (2004) A square-root domain differentiator circuit. Analog Integr Circuits Signal Process 40(1):53–59 16. L´opez-Mart´ın AJ et al (2004) Very low voltage mos translinear loops based on flipped voltage followers. Analog Integr Circuits Signal Process 40(1):71–74 17. L´opez-Mart´ın AJ Carlosena A (2003) A 1.5 V current-mode CMOS RMS-to-DC converter. Analog Integr Circuits Signal Process 36(1–2):137–143 18. Yu G-J et al (2005) Design of current-mode square-root domain band-pass filter with reduced voltage. Analog Integr Circuits Signal Process 44(3):239–250 19. L´opez-Mart´ın AJ et al (2004) A 1 V micropower FGMOS Class AB log-domain filter. Analog Integr Circuits Signal Process 41(2–3):137–145 20. Vlassis S et al (2002) A novel log-domain differentiator. Analog Integr Circuits Signal Process 32(3):285–287 21. Eskiyerli M et al (2000) “Square root domain” filter design and performance. Analog Integr Circuits Signal Process 22(2–3):231–243 22. L´opez-Mart´ın AJ et al (2001) Systematic design of companding systems by component substitution. Analog Integr Circuits Signal Process 28(1):91–106 23. Yu G-J et al (2005) Design of square-root domain filters. Analog Integr Circuits Signal Process 43(1):49–59 24. Kircay A et al (2009) A new 5th-order differential type Class-AB log-domain elliptic lowpass filter for video frequency applications. Analog Integr Circuits Signal Process 60(3):221–229 25. De la Cruz-Blas CA et al (2004) Low-voltage CMOS nonlinear transconductors and their application to companding current-mode filters. Analog Integr Circuits Signal Process 38(2–3):137–147 26. Psychalinos C et al (2002) A high performance square-root domain integrator. Analog Integr Circuits Signal Process 32(1):97–101 ¨ guz S et al (2006) Novel approximate square-root domain all-pass filter with application 27. Ozo˘ to multiphase oscillators. Analog Integr Circuits Signal Process 46(3):297–301 28. Grech I et al (2003) Low-power log-domain CMOS filter bank for 2-D sound source localization. Analog Integr Circuits Signal Process 36(1–2):99–117 29. Mohammed KO et al (2005) A tunable square root domain oscillator. Analog Integr Circuits Signal Process 43(1):91–95 30. Serra-Graells F (2003) 1 V all-MOS Σ △ A/D converters in the log-domain. Analog Integr Circuits Signal Process 35(1):47–57 31. Shah NA et al (2009) Log-domain synthesis of nth order universal filter. Analog Integr Circuits Signal Process 59(3):309–315 32. Mulder J et al (2000) Dynamic translinear circuits—An overview. Analog Integr Circuits Signal Process 22(2–3):111–126 33. Menekay S et al (2009) Novel high-precision current-mode multipler/divider. Analog Integr Circuits Signal Process 60(3):237–248 34. Leung VW et al (2000) Analysis and compensation of log-domain biquadratic filter re- sponse deviations due to transistor nonidealities. Analog Integr Circuits Signal Process 22(2–3):147–162 304 R. Vargas-Bernal and C.A. De La Cruz Blas 35. Edwards RT et al (2000) Synthesis of log-domain filters from first-order building blocks. Analog Integr Circuits Signal Process 22(2–3):177–186 36. L´opez-Mart´ın AJ et al (2001) Current-mode multiplier/divider circuits based on the MOS translinear principle. Analog Integr Circuits Signal Process 28(3):265–278 37. Masmoudi D et al (2000) A new current-mode synthesis method for dynamic translinear filters and its applications in hearing instruments. Analog Integr Circuits Signal Process 22(2–3):221–229 38. Shoemaker P (2005) A methodology for long time constant log-domain filters in CMOS. Analog Integr Circuits Signal Process 42(2):161–178 39. Lopez-Martin AJ et al (2011) Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions. Analog Integr Circuits Signal Process 66(2):299–302 40. L´opez-Mart´ın AJ, Carlosena A (2002) 1.5 V CMOS companding filter. Electron Lett 38(22):1346–1348 41. Lin TY et al (2002) Translinear sinusoidal frequency tripler. Electron Lett 38(10):441–442 42. Kao C-H et al (2005) Low-voltage low-power current mode exponential circuit. IEE Proc Circuits Devices Syst 152(6):633–635 43. Prommee P et al (2010) High-frequency log-domain current-mode multiphase sinusoidal oscillator. IET Circ Device Syst 4(5):440–448 44. Teplechuk MA et al (2007) Wave realisation of filters and equalisers in log-domain. IET Circuit Devices Syst 1(6):433–443 45. Ng AEJ et al (2004) Unified matrix method for systematic synthesis of log-domain ladder filters. IEE Proc Circuits Devices Syst 151(4):285–293 ¨ guz S (2001) Simple log-domain chaotic oscillator. Electron Lett 37(23):1378–1379 46. Ozo˘ 47. Mahon A et al (2001) Nonlinear dynamics of log-domain circuit. Electron Lett 37(15):929–930 48. Cuypers C et al (2005) General synthesis of complex analogue filters. IEE Proc Circuits Devices Syst 152(1):7–15 49. De La Cruz-Blas CA et al (2004) 1.5 V tunable square-root domain filter. Electron Lett 40(4):213–214 50. Fragoulis N (2010) Universal log-domain biquad. Electron Lett 46(7):487–488 51. Frey DR et al (2009) Unifying perspective on log-domain filter synthesis. Electron Lett 45(17):861–863 52. Georgiou P et al (2009) Chemical log-domain filter. Electron Lett 45(8):391–392 53. Juffali W et al (2010) ISFET based urea creatinine translinear sensor. Electron Lett 46(11):746–748 54. Kao CH et al (2005) Low-voltage exponential function converter. IEE Proc Circuits Devices Syst 152(5):485–487 55. Krishnapura N et al (2000) Simplified technique for syllabic companding in log-domain filters. Electron Lett 36(15):1257–1259 56. Teplechuk MA et al (2006) Approximation of arbitrary complex filter responses and their realisation in log domain. IEE Proc Circuits Devices Syst, 153(6):583–590 57. De La Cruz-Blas CA et al (2003) 1.5 V four-quadrant CMOS current multiplier/divider. Electron Lett 39(5):434–436 58. Miguel JMA et al (2011) Fully differential current-mode CMOS triode translinear multiplier. IEEE Trans Circuits Syst II Express Briefs 58(1):21–25 59. Fern´andez D et al (2008) A MOSFET-based Wide-dynamic-range translinear element. IEEE Trans Circuits Syst II Express Briefs 55(11):1124–1128 60. Ilsen D et al (2008) Algebraic and combinatorial algorithms for translinear network synthesis. IEEE Trans Circuits Syst I Regul Pap 55(10):3131–3144 61. Le˜nero-Bardallo JA et al (2008) A calibration technique for very low current and compact tunable neuromorphic cells: application to 5-bit 20-nA DACs. IEEE Trans Circuits Syst II Express Briefs 55(6):522–526 62. De la Cruz-Blas CA et al (2007) A ±0.75-V compact CMOS Class-AB current-mode expo- nential variable gain amplifier. IEEE Trans Circuits Syst II Express Briefs 54(12):1042–1046 13 A Survey on the Static and Dynamic Translinear Paradigm 305 63. Abuelma’atti MT (2005) A translinear circuit for sinusoidal frequency division. IEEE Trans Instrum Meas 54(1):10–14 64. Yin Q et al (2005) A translinear rms detector for embedded test of RF ICs. IEEE Trans Instrum Meas 54(5):1708–1714 65. Serra-Graells F et al (2005) Low-voltage cmos subthreshold log-domain filtering. IEEE Trans Circuits Syst I Regul Pap 52(10):2090–2100 66. Shepherd LM et al (2005) A biochemical translinear principle with weak inversion ISFETs. IEEE Trans Circuits Syst I Regul Pap 52(12):2614–2619 67. Ascoli A et al (2005) Nonlinear dynamics of first- and second-order log-domain circuits. IIEEE Trans Circuits Syst I Regul Pap 52(7):1372–1381 68. Senani R et al (2004) A new floating current-controlled positive resistance using mixed translinear cells. IEEE Trans Circuits Syst II Express Briefs 51(7):374–377 69. Minch BA (2004) Synthesis of static and dynamic multiple-input translinear element networks. IEEE Trans Circuits Syst I Regul Pap 51(2):409–421 70. Fox RM et al (2004) Differential log-domain filters with high-gain common-mode feedback. IEEE Trans Circuits Syst I Regul Pap 51(2):254–263 71. Minch BA (2003) Construction and transformation of multiple-input translinear element networks. IEEE Trans Circuits Syst I Fundam Theory Appl 50(12):1530–1537 72. De la Cruz-Blas CA et al (2003) 1.5-V MOS translinear loops with improved dynamic range and their applications to current-mode signal processing. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50(12):918–927 73. Psychalinos C et al (2002) A systematic design procedure for square-root-domain circuits based on the signal flow graph approach. IEEE Trans Circuits Syst I Fundam Theory Appl 49(12):1702–1712 74. Psychalinos C et al (2002) On the exact realization of log-domain elliptic filters using the signal flow graph approach. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(12):770–774 75. Minch BA (2001) Multiple-input translinear element log-domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(1):29–36 76. Mulder J et al (2001) A generalized class of dynamic translinear circuits. IEEE Trans Circuits Systems II: Analog Digit Signal Process 48(5):501–504 77. Ram´ırez-Angulo J et al (2001) MITE circuits: the continuous-time counterpart to switched- capacitor circuits. IEEE Trans Circuits Systems II: Analog Digit Signal Process 48(1):45–55 78. Frey D et al (2001) Syllabic-companding log domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(4):329–339 79. Minch BA. et al (2001) Multiple-input translinear element networks. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(1):20–28 80. Chan WP et al (2010) An integrated isfets instrumentation system in standard CMOS technology. IEEE J Solid-State Circuits, 45(9):1923–1934 81. Kircay A et al (2008) Differential type Class-AB second-order log-domain notch filter. IEEE Trans Circuits Syst I Regul Pap 55(5):1203–1212 82. Psychalinos C (2008) Low-voltage log-domain complex filters. IEEE Trans Circuits Syst I Regul Pap 55(11):3404–3412 83. Katsiamis AG et al (2008) Insights and advances on the design of CMOS sinh companding filters. IEEE Trans Circuits Syst I Regul Pap 55(9):2539–2550 84. L´opez-Mart´ın AJ et al (2005) 1.2-V 5-µ W Class-AB CMOS log-domain integrator with multidecade tuning. IEEE Trans Circuits Syst II Express Briefs 52(10):665–668 85. Kontogiannopoulos N et al (2005) Log-domain filtering by simulating the topology of passive prototypes. IEEE Trans Circuits Syst I Regul Pap 52(10):2043–2054 86. Psychalinos C et al (2004) Log-domain wave filters. IEEE Trans Circuits Syst II Express Briefs 51(6):299–306 87. Fragoulis N et al (2004) Modular log-domain filters realized using wave port terminators. IEEE Trans Circuits Syst I Regul Pap 51(11):2235–2244 306 R. Vargas-Bernal and C.A. De La Cruz Blas 88. Rodr´ıguez-Villegas E et al (2004) A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion. IEEE J Solid-State Circuits 39(1):256–259 89. Serra-Graells F et al (2004) A true-1-V 300-µ W CMOS-Subthreshold log-domain hearing- aid-on-chip. IEEE J Solid-State Circuits 39(8):1271–1281 90. Baki RA et al (2003) A low-power 5–70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications. IEEE J Solid- State Circuits 38(2):205–215 ¨ guz S et al (2003) On the realization of NPN-only log-domain chaotic oscillators. IEEE 91. Ozo˘ Trans Circuits Syst I Fundam Theory Appl 50(2):291–294 92. Drakakis EM et al (2003) Operational DC constraints for a Class-A, third-order, ob- server canonical-form log-domain filter. IEEE Trans Circuits Syst I Fundam Theory Appl 50(10):1337–1342 93. Serrano-Gotarredona T et al (2003) Log-domain implementation of complex dynamics reaction-diffusion neural networks. IEEE Trans Neural Netw 14(5):1337–1355 94. Baki RA et al (2003) Distortion Analysis of high-frequency log-domain filters using volterra series. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50(1):1–11 95. Drakakis EM et al (2003) Spectral impact of the modulation index upon internal log-domain currents. IEEE Trans Circuits Syst I Fundam Theory Appl 50(10):1343–1347 96. Ng AEJ et al (2002) Direct noise analysis of log-domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(2):101–109 97. El-Gamal MN et al (2002) A 1.2-V N-P-N-only integrator for log-domain filtering. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(4):257–265 98. Python D et al (2001) A micropower Class-AB CMOS log-domain filter for DECT applications. IEEE J Solid-State Circuits 36(7):1067–1075 99. Minch BA (2008) MOS translinear principle for all inversion levels. IEEE Trans Circuits Syst II Express Briefs 55(2):121–125 100. Diepstraten FM et al (2001) Dynamic behavior of dynamic translinear circuits: the linear time- varying approximation. IEEE Trans Circuits Syst I Fundam Theory Appl 48(11):1333–1337 101. Seevinck E et al (2000) CMOS translinear circuits for minimum supply voltage. IEEE Trans Circuits Syst II: Analog Digit Signal Process 47(12):1560–1564 102. Minch BA et al (1996) Translinear circuits using subthreshold floating-gate MOS transistors. Analog Integr Circ Signal Process 9(2):167–179 103. De La Cruz-Blas CA et al (2005) 1.5-V square-root domain second-order filter with on-chip tuning. IEEE Trans Circuits Syst I Regul Pap 52(10):1996–2006 104. De La Cruz-Blas CA et al (2011) Limit cycle behavior in a Class-AB second-order square root domain filter. Analog Integr Circ Signal Process 68(8):175–181 105. Fox RM et al (1999) Multiple operating points in a cmos log-domain filter. IEEE Trans Circuits Syst II: Analog Digit Signal Process 46(6):705–710 106. Frey DR (1996) Exponential state space filters: a generic current mode design strategy. IEEE Trans Circuits Syst I Fundam Theory Appl 43(1):34–42 107. Ferrer E et al (1999) Limit-cycle oscillations in a log-domain based filter. IEEE Trans Circuits Syst II: Analog Digit Signal Process 46(6):832–836 108. Vargas-Bernal R et al (2000) Identifying translinear loops in the circuit topology. In: Proceedings of the IEEE ISCAS, vol 2. Geneva, pp. 585–588 109. Vargas-Bernal R (2002) Prediction of multiple dc operating points in a CMOS log-domain filter. In: Proceedings of the IEEE Latin-American CAS Tour. Puebla, pp. 70–73 Index A SRCO (see Single resistance controlled Active devices oscillators (SRCO)) BGE (see Binary genetic encoding (BGE)) synthesis and design, active networks, 34 circuit optimization, 13–28 Active filters circuit topologies, 202 B and T matrices, bi-band circuit, 112 conventional systematic synthesis, 86 LC, element, 110 current/voltage, 54 lossless LC-filters to active RC-circuits DDD (see Determinant decision diagrams application, synthesis, 109–114 (DDD)) designing lossy filters, 115–119 evolutionary algorithms, 24–28 two-graph technique, 108–109 multi-objective evolutionary algorithm, lossless parallel LC, 111 21–23 RC element, 110 multi-objective particle swarm RC equivalent circuit, B and T matrices, 112 optimization, 23–24 transfer function, 113, 114 NSGAII, 20–21 two-graph based transformation technique nullor models, 33 circuit synthesis, 107 pathological elements, 86 classical two-graph method, 108 symbolic analysis, 56 MNA, 107 symbolic nodal analysis (see Symbolic voltage source, 111 nodal analysis) Active RC filters systematic design analog baseband architecture, 133 CMOS VFs, 10, 13 automatic tuning scheme, 132 computational synthesis, CMs, 10–11 broadband receivers, 132 current biases, 10, 11 pole-zero placement, 133 dual topology, VF and CF, 9 ADC. See Analog-to-digital converter (ADC) gate and drain, MOSFET, 10, 11 Amplifiers mixed-mode, 12–13 analog signal, 265 nullator-norator joined-pairs, 10 CDBA, 77 VFs synthesis, 10, 12 CDTA, 78 VMs VFs, 10, 14 CLASS-D audio, 267–269 Active elements GBW, 135 frequency stability, 66 HSPICE vs. derived symbolic nullators and norator, 85 expression, 7, 8 op-amp, 34 low noise (see Low noise amplifiers pathological elements, 86 (LNAs)) E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, 307 DOI 10.1007/978-1-4614-1383-7, © Springer Science+Business Media New York 2013 308 Index Amplifiers (cont.) FET/MOSFET, 33 noise density, 135 FTFN, 32 nullor equivalent, 7 CCIIΘ -based floating impedance, OFA, 32 41–43 OMA, 36 floating impedance converters/inverters, operational amplifier, 85 39–41 operation transresistance, 78 floating inductance circuits, 43–45 Op operational, 267, 268 single resistance floating inductance OTA, 33, 136 simulation, 45 OTRA, 8, 56, 78 nullors, analog circuit building blocks, passive current-mode mixer, 122 33–34 PGA, 134, 135, 301 OFA and FTFN, 34–36 resistors and capacitors, 85 RC circuits, 52–54 sinusoidal oscillator, 9 SRCO, 46–48 uncompensated low voltage, 7 universal biquad, differential and inverse AMS. See Analog mixed signal (AMS) filters Analog adjacent channels CM inverse filter, 51–52 consumption, ADC, 131, 132 current-mode, 48–49 dynamic range, 130–131 differential CM, 49–51 single analog carrier per channel, 130 VF and CF, 33, 34 Analog and semi-digital sensor conditioning VM and op-amp, 31 circuits Analog/digital circuit. See also Steady-state alternative method, 224 simulation of mixed analog/digital robustness vs. environmental noise, 225 circuits traditional method, 224 CFOAs, 62 types, readouts, 224 current-mode, 61 Analog baseband dynamic range requirements terminal equations, 62 analog and digital adjacent blockers, 122 Analog divider. See MOSFET-C interdependence, filter and ADC Analog mixed signal (AMS) simulation defined, sensitivity receiver, 125 circuits effects, 125, 126 analog domain parameters, 253 inverse Chebyshev, 127 darker gray regions, 253, 254 I/Q demodulation, 126 differential and algebraic variables, PAR and OFDM, 125–126 252 residual power evaluation, 126 external or internal events, 254 residual undesired power (see Analog generic architecture, 252, 253 adjacent channels; Digital adjacent Jacobian matrix, 255 channels) manifolds and normal vectors, 255 signal chains, 122–123 real values and dynamical behaviour, spurious-free (see Spurious-free-dynamic- ADE, 252 range (SFDR)) saltation matrix SΦ , 256 wireless radio, direct conversion sensitivity matrix, 255–256 architecture, 122, 123 definition, 245 Analog circuits saltation matrices evolution, CFOAs, 62 defined, 247 impedance realization, 63 impact/switch phenomenon, 248 slew rates, 63 ODEs, 247–249 Analog circuit synthesis smooth non-autonomous active networks design, 34 DAE, 245–247 building blocks, 31 defined, 245 CCII+, nullor, 33 ODE, 247 CCII-, nullor model, 33 switching non-autonomous CM and VM, 54–55 description, 249 CMOS and bipolar implementations, 36–39 Jacobian matrix, 250–251 Index 309 saltation matrices, 251–252 ideal transistors, 33 two-dimensional “jumping” trajectories, and MOS, 290 249–250 and Op-Amp, 32 Analog signal processing translinear circuits active devices (see Active devices) defined, 292 current-mode circuits, 61 exponential/logarithmic relationships, MOSFET-C, 82 292 pathological elements and nullor, 28 NPN and PNP saturation currents, Analog-to-digital converter (ADC) 292–293 circuit design, 178 translinear elements and loop, 291 clock delays, 174 Biquad filters conversion rate, 171 current-mode, 72 flash, 191 filter functions, 71 folding converter system, 191 input voltages, 70 gate tunnel current, 178 MISO, 70 input voltages, 171 mixed-mode, 71 interdependence, baseband filter trans-admittance and impedance, 72 ADC DR, 126 voltage-mode universal, 71–72 receiver sensitivity, 125 Bit error ratio (BER) residual power evaluation, 126 amplitude, PRBS, 185 residual undesired power (see Residual analyzer stations, 175 undesired power) vs. CINP, 184 regenerative comparator, 171 combined noise, 175 input voltage difference, 183 metastability, 176 B probability density function, 175 BCI. See Brain-computer interface (BCI) regenerative comparator, 175 BER. See Bit error ratio (BER) BJTs. See Bipolar junction transistors (BJTs) BGE. See Binary genetic encoding (BGE) Boundary-value problem (BVP), 257 Binary genetic encoding (BGE) Brain-computer interface (BCI), 213 CM modeling, 11, 15 BVP. See Boundary-value problem (BVP) evolutionary algorithms, 101 mixed-mode circuit topologies, 202 BioChem Lab-On-A-Chip, 196 C Biomedical sensors applications Capacitive sensor conditioning circuits, 225 artificial retina, 196–197 Cascode with an inductively source BioChem Lab-On-A-Chip, 196 degeneration (CISD), 153, 154 cancer detector, 199 CC. See Current conveyors (CC) general health monitor, 199–200 CDBA. See Current differencing buffer glucose level monitor, 198 amplifier (CDBA) organ monitoring, 198–199 CDTA. See Current differencing Biosensors transconductance amplifier challenges, 200–201 (CDTA) classification CFOA. See Current-feedback opamp (CFOA) chemical sensors, 195 Circuit analysis high-risk workers, 195 effect, parasitic capacitance, 230–231 home care monitoring, 195 maximum sensing capacitance, 229–230 invasive and non-invasive, 195 noise and readout resolution, 232–237 minimally invasive, 195 oversampling, 237–238 rehabilitation, 195 reconfigurable readout dynamic range and top ten targets, wireless health, 195, 196 sensitivity, 231–232 wireless hospital network, 195 Circuit implementation Bipolar junction transistors (BJTs) active RC FET/MOSFET, 33 filters, 132 310 Index Circuit implementation (cont.) cross-coupled inverter, 171 GBW, 135 delay time reduction, 185–190 MFB filter structure, 134 ideal comparator, 171, 172 output spot noise spectral density, 135 input impedance, 227 PGA, 135–136 0.12 µm CMOS technology, 180–185 SC (see Switched capacitor (SC)) positive feedback, 171, 172 variation, integrated noise, 135, 136 regenerative comparator, 171, 172 cascaded hybrid baseband architecture signal, 236 analog, 133 small-signal equivalent circuit, latch, 171 biquad transfer function, 133 small-signal representation, 172 Inverse Chebyshev approximation, Clocked nanometer CMOS comparators, 235, 133–134 238 pole-zero placement, baseband inverse CM. See Current-mode (CM) Chebyshev approximation, 132, 133 CM filters SC filters, 132–133 active filter, 5, 6 UHF receiver and the analog baseband, 132 admittance matrix, 6 Circuit modeling, 260 CM (see Current mirrors (CMs)) Circuit optimization symbolic expression, 6 CFOA-topologies, 13, 17 CMOS technology. See also Clocked equality constraints and vector function, 14 comparator evolutionary algorithms (see Evolutionary DSM (see Deep-sub-micron (DSM)) algorithms) gate-leakage mismatch, 178 MOEA/D (see Multi-objective evolutionary 0.12 µm, 600 MHz algorithm, decomposition BER measurements, 184 (MOEA/D)) bias voltage, 180 MOP, 13 CLK and CLKR, 180 MO-PSO (see Multi-objective particle comparator, 180, 181 swarm optimization (MO-PSO)) complementary rectangular clock NSGAII (see Non-dominated sorting signals, 181 genetic algorithm II (NSGAII)) differential amplifier, 183 Pareto dominance (see Pareto dominance) duty cycle, 182 Circuit simulation layout plot and microphotograph, test AMS, 258 chip, 184 floating FDNC, 42 maximum clock frequency, 180 floating FDNR, 42 measured transient behavior, 185 HSPICE, 24 Monte Carlo simulations, 183 PERL script programming, 24 MOS-transistor, 180 saltation matrices, 245 NW ELL, 181 Circuit synthesis. See Analog circuit synthesis operating clock, 185 CISD. See Cascode with an inductively source test chip, 181, 182 degeneration (CISD) transfer stages, 183 Clocked comparator transient simulation, 181, 182 ADC, 171 transistors N6 and N7, 181 characterization transmission gate, 183 delay time, 177 n and p-MOS transistor, 178 hysteresis, 176 STI, 177 INP and INN, 173 UDSM (see Ultra-deep-sub-micron input voltage difference, 176 (UDSM)) noise source (see Noise) CMs. See Current mirrors (CMs) offset, 176 Comparator circuits power consumption, 177 CINP–CINN, 180 regenerative comparator, 176–177 double-tail and latch-type, 178, 179 CMOS technology, 177–178 power consumption, 180 comparator circuits, 178–180 stacked transistors, 179 Index 311 transconductance, 179 trans-impedance, 62 transistors N2 and N3, 178 types voltage difference, 179 DDCCFA, 80, 81 Constant-bandwidth MCFOA, 80 instrumentation amplifier, 64, 65 SCFOA, 80, 81 non-inverting and inverting amplifiers, 65 VFs, 17–19, 24 VOAs, 65 VOAs (see Voltage mode op-amp (VOA)) Current conveyors (CC) Current mirrors (CMs) building blocks, 62 CCII+, 89 CCI and CCII, 62 current conveyors, 55 MCFOA, 62 hromosomal representation, 11 VOA, 62 nullators and four norators, 10, 15 Current differencing buffer amplifier (CDBA), nullators and norators, 54 77 symbolic notations, 54, 55 Current differencing transconductance synthesis, 11, 16 amplifier (CDTA), 78 two-port network element, 86 Current feedback op-amp (CFOA) Current-mode (CM) AD844 type, 62, 63 band-pass filter, 94 analog circuit design, 61 biquad filters, 72–73 analog divider, MOSFETs, 73 CC (see Current conveyors) A741 type VOA, 62 circuit design, 61 base-emitter voltage and collector current, current outputs, 48, 49 bipolar transistor, 62 defined, TC, 291 biquad filter realizations, 70–73 differential CM biquad CMOS technologies, 79 bandwidth and pole frequency, 50 CMRR and accuracy, 79 building block, 49 constant-bandwidth (see Constant- output OTA (DOTA), 50 bandwidth) transfer functions, 51 current feedback operational amplifier, 79, universal filter, 50, 51 80 VM, 49 encoding, 25, 28 electrical properties, 223 evolution, current conveyors, 62 FTFN (see Four terminal floating nullor floating impedance simulation (see Floating (FTFN)) impedance simulation) HP and BP, 48, 49 forward and reverse bootstrapping, 79 infinite output resistances, 49 IC technology (see Integrated circuits inverse filter, 51–52 (ICs)) low-voltage current controlled current internal circuit and bipolar implementation, conveyor, 300 62, 63 MITEs, 301–302 MOSFET-C, 73–75 nonlinear and linear, 290 Optimization, 26–28 output current, 94 precision rectifier parameters, 49 AD844 type, 75 parasitic capacitance and temperature, 225 output voltage, 75 signal-handling capability, 290 wave, 75 signal processing/signal generating circuits, relaxation oscillator/waveform generator, 61 76 trans-admittance mode, 48 slew rate translinear filters, 299 component-matching, 64 Sinh-characteristics, 63 transconductance stage, 63 D SRCO, 66–67 DAE. See Differential algebraic equation terminal equations, 62 (DAE) 312 Index Deep-sub-micron (DSM) DSH. See Discontinuous shooting (DSH) shallow trench isolation, 177 DSM. See Deep-sub-micron (DSM) twin well process, 177 DTCs. See Dynamic translinear circuits Delay time reduction, supply voltages (DTCs) BER measurements, 189, 190 Dynamic translinear circuits (DTCs), 292 CINP–CINN, 187 Dynamic translinear paradigm CLKIN, 189 capacitor current, 298 conventional circuit, 186 description, 297 conventional comparator, decision time, log-and square-root domain, 298 187, 188 log-domain circuits, 299 distinct operating point, 186 nonlinear building blocks, 299–300 input transistors N2, N3, 185–186 principle, 297, 298 measured power consumption, 190 square-root domain circuits, 299 measurement circuitry, 189 modified latch comparator, 187 on-chip implementation, 189, 190 E rail-rail output, 185 Evolutionary algorithms reset transistors N4 and N5, 186 CFOA (see Current-feedback opamp test chip, 188 (CFOA)) transfer stage, 189 electrical measurements, 24 transistor P0/P1, 186 HSPICE, 24 transistors N0 and N1, 187 vector, 24 UDSM-CMOS technologies, 186 Design automation computational synthesis, CMs (see Current F mirrors (CMs)) FDNR. See Frequency dependent negative mixed-mode (see Mixed-mode) conductance (FDNR) Design techniques FGMOS. See Floating gate MOSFET active RC-filters, 108 (FGMOS) lossy filters Flexible nanometer CMOS low-noise B and T matrices, circuit, 115 amplifiers. See Low noise amplifiers current conveyor based filter, 117, 119 (LNAs) substitution, R2 by Rd3 , 115, 117 Floating gate MOSFET (FGMOS) transfer function, 115, 116 qualities, 301 Design trade-offs, 271 translinear circuits Determinant decision diagrams (DDD), 202 description, 296 Differential algebraic equation (DAE) input and output transistors, 296–297 saltation matrices, 251, 256 MITE, 296 smooth non-autonomous analog circuit, weak and strong inversion, 297 245 Floating GIC switching non-autonomous analog circuit, CCIIΘ 249 CC-networks, 43 time domain analysis, 258 FDNR and FDNC, 41, 42 Digital adjacent channels FI, 42 baseband input spectrum, 127 nullor model, 41, 42 dynamic requirement, 128–129 FTFN implementation, 41 output power density and definitions, 127, GIC, nullor model, 40 128 norators, 40 parameters, 128 theorem, 39 transfer function H( f ), 127 Floating impedance simulation Discontinuous shooting (DSH) FI, 68 extrinsic manifolds, 264 floating frequency dependent negative modulus, spectra, 266 resistance, 68 periodic noise analysis, 267 GPII/GPIC configuration, 68 Index 313 negative, 70 floating impedance (see Floating GIC) negative-valued elements, 68 grounded lossless inductance, 39 VCZ configuration, 69 Generation, grounded capacitors minimum Floating inductance circuits component oscillators FI circuits, 43 CCII/ICCII, 87 gyrator, 44 class I inductance value, 43 B type, 90–91 lossless grounded inductor, FI, 43, 44 state equations, 88, 89 nullator and norator, 44 A type, 88–90 theorem, 43 class II Four terminal floating nullor (FTFN) B type, 92 CCII–, 35 C type, 92–93 CCIIs, 32 D type, 94–95 CFOA, 36 class III CMOS and bipolar implementations B type, 97 biquad filter realization, 39 C type, 97 CCII–, 37 D type, 97 floating current and amplifiers, 37 A type, 95–96 floating nullor, 36 class IV mirrored output port and equation, 38 B type, 100–101 multiple output, 37, 38 A type, 97–100 transconductor, 37 NAM equation, 87 CMOS implementations, 32 NAM expansion, 85 floating inductance circuits (see Floating Op Amp and VCVS, 85 inductance circuits) passive elements, 86 impedance synthesis topology realizations, class IV GIC (see Generalized impedance type A, pathological realization, 102, converter (GIC)) 103 RC elements, 39 type B, pathological realization, 102, and OFA (see Operational floating amplifier 104 (OFA)) VM and CM, 86 OMA, 36 Graph theory, 300 terminal nullors, 35 Grounded capacitors. See Oscillators versatile and building blocks, 32 Frequency dependent negative conductance (FDNR), 68 I Frequency dependent negative resistor (FDNR) ICs. See Integrated circuits (ICs) circuits Inductively source degeneration (ISD), 153, class, oscillators, 91 154 grounded capacitor, 94 Integratable implementations and applications Frequency response in analog signal processing, 121, FDNR (see Frequency dependent negative 290 resistor (FDNR) circuits) Integrated circuits (ICs). See also Comparator oscillation, 87 circuits SRCO (see Single resistance controlled current-mode analog techniques, 61 oscillators (SRCO)) development, 194 FTFN. See Four terminal floating nullor multi-standard LNA, 147, 148 (FTFN) parasitic capacitance, 225 processing and sensing techniques, 218 sensors and modern, 193 G SRCO (see Single resistance controlled Gain-bandwidth (GBW), 135, 136 oscillators (SRCO)) GBW. See Gain-bandwidth (GBW) symbolic nodal analysis (see Symbolic Generalized impedance converter (GIC) nodal analysis) 314 Index Integrated inductors circuit design chip microphotograph, 165 bulk-driven technique, 206–209 cross section, physical structure, 162, 163 CMOS process, 201–202 Pareto extended surface, 272 electrical signal and physical quantities, ISD. See Inductively source degeneration 201 (ISD) floating gate technique, 211–213 self-cascode technique, 209–211 sub-threshold design, 202–206 L supply voltage reduction, 206 LDO. See Low drop-out (LDO) threshold voltage, 202 Log-domain circuits, 299 transfer quality, 201 Low drop-out (LDO), 216, 217 classification, biosensors Low noise challenges, 200–201 PSRR, 64 chemical sensors, 195 slew rates, 64 contacting, 195 Low noise amplifiers (LNAs) high-risk workers, 195 circuit topology, 146 home care monitoring, 195 CMOS technology, 146 invasive and non-invasive, 195 description, 145 minimally invasive, 195 multi-standard, 145–146 rehabilitation, 195 reconfigurable CMOS wireless health, targets, 195, 196 description, 146 wireless hospital network, 195 external switching capacitor, 148–149 DC signal, 216 multi-band, 149–152 devices, use, 194 switchable resonant tank, 146–148 IC processing and sensing techniques, 218 RF front-ends, 145 identification and characterization, sample, state-of-the-art reconfigurable CMOS, 165, 193 167 LDO voltage regulator, 216, 217 two-stage inductive degeneration MEMS, 194 design procedure, 161–162 microanalytes, 193 experimental results, 165 output voltage expression, 217 input impedance, 153–156 photovoltaic cells, 216 layout, packaging and simulation signal processing results, 162–164 neural systems, 213–215 noise factor, 159–161 potentiostats, 215–216 output impedance, 157–159 WBAN, 194 voltage gain, 156–157 wireless networks, 194 Low power Low voltage. See also Amplifiers analog design, 289 analog signal processing applications, 290 implantable and mobile applications, CMOS IC technology, 7 238–239 design current mode filters, 300 Monte-Carlo simulations, 189 mixed signal designs, 289 sensor interface, 223 modified latch, 188 sensor readout circuit, 241 TL circuits, 290 supply voltage, 191 UDSM-CMOS technologies, 186 threshold voltages, 186 uncompensated amplifier, 7 Low-power electronics, biomedical sensors applications artificial retina, 196–197 BioChem Lab-On-A-Chip, 196 M cancer detector, 199 MEMS. See Micro electro mechanical systems general health monitor, 199–200 (MEMS) glucose level monitor, 198 MFB. See Multi-feedback (MFB) organ monitor, 198–199 M.I. See Moderate inversion (M.I.) Index 315 Micro electro mechanical systems (MEMS), Multi-feedback (MFB) 194 PGA, 135–136 MITE. See Multiple-input translinear element single-opamp, 134 (MITE) Multi-objective evolutionary algorithm, Mixed-mode. See also Biquad filters decomposition (MOEA/D) filter and oscillator design, 12 algorithm vector generation, 21–23 negative and positive types, 12 objectives space, 21 stimulation, 252 scalar optimization, 23 unity-gain cells, 12, 16 vector, 21 universal filter, 56 Multi-objective particle swarm optimization VF-CM-VF block, 12 (MO-PSO) Mixer bound limits, 23–24 harmonic, 300, 301 local and global positions, 23 passive current-mode, 122 REP, 24 MNA. See Modified nodal analysis (MNA) Multiple-input translinear element (MITE), Mobile systems. See Low noise amplifiers 296, 301–302 (LNAs) Moderate inversion (M.I.), 202 Modified nodal analysis (MNA), 3, 107 N MOEA/D. See Multi-objective evolutionary NEF. See Noised efficiency factor (NEF) algorithm, decomposition Noise (MOEA/D) BER (see Bit error ratio (BER)) MO-PSO. See Multi-objective particle swarm circuit elements optimization (MO-PSO) MOS transistor, 174 MOSFET shot noise, 174 bulk-driven, 208, 209 thermal/flicker, 174 cut-off frequency, 202 clock cycle, 176 floating gate, 211, 212 Gaussian distribution, 175 higher transconductance efficiency, 202 kickback HSPICE, 24 clock delays, 174 inverting VCCS, 54 positive feedback, 174 low-power circuit design techniques, 202 metastability error, 175 N-channel, cross section, 207 output voltage difference, 175–176 N/P channel, 10 signals nullator and norator, 10 amplitude/time, 173 nullor synthesis, 10, 11 neighboring circuit components, 173 terminal nullor, 33 static transistor inversion, 203 half clock cycle, 174 MOSFET-C SNM, 174 analog divider, 73 Noised efficiency factor (NEF) calculation, analog divider, CFOAs, 73 214 biquad CFOAs, 73 Non-dominated sorting genetic algorithm II electron mobility and threshold (NSGAII) voltage, 74 algorithm 1, 20 LP/BP filter, 73, 74 crowding distance assignment, 20 MOS transistors, translinear circuits nondominated sort, 20, 21 quasiquadratic law, 293 Pareto dominance, 20 saturation, active/strong-inversion mode, Norators 294 admittance matrix, 85 in strong inversion, 294–295 building blocks, 33–34 subthreshold/weak-inversion mode, description, 202 293–294 joined-pairs, 10 in triode, 295–296 nullators (see Nullators) triode, ohmic/linear mode, 294 transistors, 9 316 Index Norators (cont.) O VM (see Voltage mirror) ODE. See Ordinary differential equation voltage and current, 85, 86 (ODE) NSGAII. See Non-dominated sorting genetic OFDM. See Orthogonal-frequency-division- algorithm II (NSGAII) multiplexing (OFDM) Nullators Operational floating amplifier (OFA), 32 CCII+, 86 Operational transconductance amplifiers description, 202 (OTA) infinity-variables, 85 active RC section, 137 input port and norator, 32 GBW account, 136 matrix elements, 85 nullors/pathological elements, 3 norator–CM–VM, 55 OTA-C filters, 4 norator joined-pairs, 10 Operation transresistance amplifier (OTRA), norator pairs, 9, 51 78 and norators (see Norators) Ordinary differential equation (ODE) oscillator I, A type DAE modeling, 250 and CM (see Current mirrors (CMs)) hybrid system, 247 NAM equation, 88 saltation matrix expression, 250, 251, 256 oscillator II, A type, 91 Orthogonal-frequency-division-multiplexing symbols and definitions, 32 (OFDM), 125–126 VF descriptions, 10 Oscillators voltages and current, 85, 86 based circuits, 225 Nullors. See also Analog circuit synthesis circuit designer, 262 analog circuit building blocks (see Analog crystal, 226–227 circuits) external clock signal, 237 based circuit, 117, 119 OTRAs, 8 BJT and Op-Amp, 32 PWM circuit stems, 232 building block realization, 77 sensing range limitations, 229 CCII+, 86 SRCO (see Single resistance controlled FTFN (see Four terminal floating nullor oscillators (SRCO)) (FTFN)) voltage controlled (VCO), 244 NAM expansion, 86 OTA. See Operational transconductance OFA (see Operational floating amplifier amplifiers (OTA) (OFA)) Op-Amp, 117 RC circuits P grounded resistor, 52 PAR. See Peak-to-average ratio (PAR) immittance inverter circuit, 52, 54 Pareto dominance indefinite admittance matrix, 53 definition, optimality, 15 negative conductance, 53 Pareto optimal set/pareto front, 17 noninverting VCCS, 53 Particle swarm optimization (PSO) norator and nullator, 53 canonical algorithm nullor MOSFET and CCs, 54 flowchart, 277–278 VCCS (see Voltage controlled current single performance index, 276 source (VCCS)) velocity determination, 277 switching functions, 110 defined, Pareto optimality, 276 symbolic notation and characterizing design results, 280–281 equations, 32 and discrete search space terminal floating, 77 effect, 278–279 terminal voltages and current, 85, 86 spiral inductor design constraints, 278 VM (see Voltage mirror) technical constraints, 278 Index 317 evolutionary strategy, 276 S features, canonical, 281–282 SC. See Switched capacitor (SC) handling multiple objectives Sensor conditioning circuits description, 279 analog and semi-digital dual-objective, inductor design, alternative method, 224 279–280 robustness vs. environmental noise, 225 ring topology traditional method, 224 design results, 283, 284 types, readouts, 224 niching algorithm, 282–283 capacitive, 225 robustness to parameter variation, electrical properties, 223 283–286 interconnect requirements, readout and PCR. See Polymerase chain reaction (PCR) sensors, 223 Peak-to-average ratio (PAR), 125–126 physical quantity, 223–224 PGA. See Programmable gain amplifier (PGA) resistive, 226 Polymerase chain reaction (PCR), 196, 197 universal sensor interface, 223, 224 PRBS. See Pseudo random bit sequence universal sensor readout circuit (PRBS) circuit analysis and optimization, Programmable gain amplifier (PGA), 135–136 229–238 Pseudo random bit sequence (PRBS) implementation and measurement BER measurement (see Bit error ratio results, 238–241 (BER)) principle, operation, 226–229 CINN and CINP, 185 S.I. See Strong inversion (S.I.) Sigma-delta modulators, 243, 244, 301–302 Signal-to-noise-and-distortion ratio (SNDR) R ADC process, 126 Reconfigurable CMOS description, 123 description, 146 distortion power, 124 external switching capacitor out-of-band blockers (UDdB ), 124 description, 148 Single resistance controlled oscillators (SRCO) multi-standard LNA, multi-band CFOA-GC SRCO, 66 matching network, 148, 150 CFOAs, 66, 77 (see also Current-feedback noise performance and maximum opamp (CFOA)) frequency, 149 CO and FO, 46 multi-band feedback link, 67 coupling input network sizing, 151–152 FO control, 66 drawbacks, 149–150 frequency and slew rates, 66 multi-band matching network, 149, 150 FTFN (see Four terminal floating nullor resonant frequencies, 150 (FTFN)) S21 and NF variation, 151 grounded capacitors and IC switchable resonant tank implementation, 47 Cg effect, 148, 149 op-amp RC sinusoidal oscillators, 46 description, 146–147 oscillator realization, 48 load inductors, 147 single op-amp RC, 46 multi-standard LNA, 147 theorem, 46 Relaxation oscillator/waveform generator Single resistance tunable lossy floating square wave signal, 76 inductance simulation triangular/square wave, 76 grounded elements/terminals, 45 Residual undesired power resistance and inductance, 45 from analog adjacent channels, 130–132 RL impedance, 45 from digital adjacent channels, 127–130 Smart sensor Resistive sensor conditioning circuits, 226 biomedical sensors, applications, 196 Retina prosthesis project, 198 eye, 197 318 Index Smart sensors and integrated microsystems fundamental-matrix numerical (SSIM), 196 computation, 265–266 SNDR. See Signal-to-noise-and-distortion ratio In, Out and Op amplifier, 268 (SNDR) modulus, spectra, 266 SOC. See System-on-chip (SoC) power spectral density, Out node, 267 Software-defined-radio. See Low noise schematic, analog to digital converter, amplifiers (LNAs) 265 Spurious-free-dynamic-range (SFDR) S & H shapes, 266–267 active devices, 123 PA2D and PD2A converters, 244 IM3 power, 123 PLL and VCO, 244 out-band IIP3 value, 123, 124 “saltation” matrices, 245 out-of-filter-band blockers, 124 signal processing, 243 SFDR, 124 time domain periodic algorithms SNDR value, 123 Newton iterative method, 257–258 Square-root domain circuits, 299 ODE and BVP, 257 SRCO. See Single resistance controlled PAC and PNOISE, 256 oscillators (SRCO) SH, 256–257 SSIM. See Smart sensors and integrated Strong inversion (S.I.) microsystems (SSIM) MOSFET, 202 Static translinear circuits (STCs), 292 and W.I., 203–205 Static translinear paradigm Survey on static and dynamic translinear classification, TCs, 292 paradigm configurations, TL loops, 291 applications, 301–302 description, 291 electronic designers, 289 elements, 291 goal, 289 topologies, 291 issues, MOS transistors, 290 translinear circuits log-domain circuits, 299 BJTs (see Bipolar junction transistors nonlinear building blocks, 299–300 (BJTs)) open research lines FGMOS transistors (see Floating gate analog noise generators, 300 MOSFET (FGMOS)) graph theory, 300 MOS transistors, 293–296 noise performance, 300 STCs. See Static translinear circuits (STCs) square root-domain filters, 301 Steady-state simulation of mixed analog/digital translinear loops, 300 circuits principle, 290 AMS (see Analog mixed signal (AMS) square-root domain circuits, 299 simulation) TL loops and circuits, 290 behavioural models, 243 translinear circuits conventional analog tools, 244 BJTs, 292–293 DC analysis, 244 FGMOS transistors, 296–297 extrinsic manifolds MOS transistors, 293–296 DSH analysis, 264 Switched capacitor (SC) AND logic gate, 261 biquad implementation, 136, 137 nominal and petrubed trajectories, description, 136 262–263 frequency dependent gain and phase PA2Ds and PD2As, 260–261 mismatch, 137 fundamental matrix, AMS, 258 PMOS input, 137 implementations, SOC, 243 programmable capacitor arrays, 136 intrinsic manifolds Switched-circuit, 113, 114 false jump, 259 Symbolic analysis, 107 independent scalar equation, 260 Symbolic nodal analysis time domain analysis, 258–259 current mirror arrays (see Current-mode numerical results filter) CLASS-D audio amplifier, 267–269 nullors and pathological elements Index 319 CCI, 3 Translinear circuits (TCs) CFOA description, 5 base-emitter voltage, 62 input impedance and independent gain, bipolar transistor, 62 5 bipolar transistors, 292 MNA (see Modified nodal analysis BJTs, 292–293 (MNA)) defined, 291 OTA (see Operational transconductance dynamic nonlinear building blocks, 290 amplifiers (OTA)) dynamic translinear principle, 296, 297 RC filter, 3, 4 log-domain filters, 299 voltage and current, 3 MOS, 293–297 System-on-chip (SoC), 121, 243, 244 static, 298 STCs and DTCs, 292 topologies, 291 T Translinear (TL) loops TCs. See Translinear circuits (TCs) advantages, 290 Time simulation BJT transistors, 291 AMS, 244 configurations, 291 behavioural models, 243 FGMOS transistors, 297 conventional comparator, 187, 188 nonlinear characteristics, MOS and BJT, mixed mode, 252 292 Monte Carlo, 183 RMS-DC converters, 295 sense amplifier, 180 signal dynamic range, 290 standard deviations, 189 transistor topology, 290 supply voltage, 172, 181 Two-stage inductive degeneration LNA Transistors common-source, 152, 153 analog circuits, 62 dependency, CISD and ISD, 153, 154 bipolar, 62, 292 design procedure BJT (see Bipolar junction transistors programmable load sizing, 161, 162 (BJTs)) systematic steps, 161 CFOA encoding, 15 design requirements, 152 CMs (see Current mirrors (CMs)) experimental results FGMOS, 291 chip microphotograph and test PCB, and ideal inductors, 153 165 input and output stage, 152 reconfiguration, NF and S21 , 165, 166 inversion, level, 203, 204 input impedance lengths and widths, 202 ideal inductors and transistors, 153 low switch-on resistance, 147 resonance frequencies, 154 metal-oxide-semiconductor field-effect, resonant frequency tunning, 155–156 293 S11 parameter, GSM standard, 154, 155 MOS, 163, 289, 290, 293–296 layout, packaging and simulation results M pNF1,2 and M pG1,2 , 153, 161, 162 input/output capacitors, 162–163 N0 and N1, 178 90-nm CMOS technology, 162 N2 and N3, 178 physical structure, inductors and n and p MOS, 178 varactors, 162, 163 node V 2 expression, 230 QFN package, 163 noise sources, 232, 237 simulated performance, 164 NPN and PNP, 292 simulation, NF and S-parameter, 163, P0, P1, P2 and P3, 178 164 resistive and capacitive sensor readout M pNF1,2 andM pG1,2 transistors, 153 configurations, 227, 228 noise factor TL loops, 290, 291 common-source, 153, 160–161 topologies, circuits, 291 defined, 159 transistors P2 and P3, 178 sources, 159 voltage and current, 202 varactor capacitance, 161 320 Index Two-stage inductive degeneration LNA (cont.) Pi-model, 275 output impedance process variables impact, 275 defined, 157–158 spacing, conductors and interlayer input and output coupling network, 159 dielectrics, 272 S22 in WCDMA, 158 spiral, 272, 273 S22 parameter setting, 159, 160 square inductor geometric parameters, stand-alone circuit, 157 273 voltage gain VCCS. See Voltage controlled current source amplification stages, 156 (VCCS) defined, 156–157 VCO. See Voltage controlled oscillator (VCO) S21 vs. frequency, 157, 158 VM. See Voltage mirror (VM) Voltage controlled current source (VCCS) admittance matrices, 52 U floating conductance, 54 Ultra-deep-sub-micron (UDSM) CMOS noninverting FET and CCII–, 52 technology nullor model, 33 cross-coupled inverters, 186 Voltage controlled oscillator (VCO), 244 digital circuits, 178 Voltage mirror (VM) power consumption, 191 description, 86 Universal biquad, current-mode (CM). See NAM, 90 Current-mode (CM) Voltage-mode Universal sensor readout circuits BER vs. CINP, 184 circuit analysis and optimization (see biquad filter, 71–72 Circuit analysis) current-mode, 82 description, 226 Monte Carlo simulations, 183 implementation and measurement results, Voltage mode op-amp (VOA) 238–241 building blocks, 62 principle, operation closed loop gain, 62 ideal response, reset block, 229 functional circuits, 63 output pulse width, 228 slew rates, 63 phase detector, 227–228 SRCOs, 66 pull-down NMOS transistor, 228 sensor readout circuit and sensor configuration, 226, 227 W WBAN. See Wireless body area network V (WBAN) Variability-aware optimization, RF integrated Weak inversion (W.I.) inductors definition, 202 defined, PSO, 272 and S.I., 203–205 design complexity, 271 W.I. See Weak inversion (W.I.) dynamic variations, 271 Wireless body area network (WBAN) lumped scalable models, 272 definition, 194 multi-objective particle swarm (see Particle patient monitoring system, 194 swarm optimization (PSO)) Wireless receivers RF and AMS, 271 analog baseband dynamic range ring topology, PSO requirements (see Analog baseband algorithm, 282–283 dynamic range requirements) design results, 283 analog baseband filter design, 142 robustness to parameter variation, baseband response and residual DR 283–285 measurements sources measurements, 138, 139 capacitance, 274 64-QAM digital channels, 138, 140 physics-based analytical expressions, residual, 139, 140 273 block level partitioning, 121, 122 Index 321 chip micrograph, UHF receiver, 138 SoC solutions, 121 circuit implementation (see Circuit system performance implementation) experimental results, 140, 141 direct-conversion UHF, 121–122 power consumption and area metrics, dynamic range requirements, 142–143 142 RF pre-filtering, 121 two-tone measurement, 142

References (500)

Sánchez-López C, Fernández FV, Tlelo-Cuautle E, Tan SX-D (2011) Pathological element- based active device models and their application to symbolic analysis. IEEE Trans Circuits Syst I Regul pap 58(6):1382-1395
Wang HY, Huang WC, Chiang NH (2010) Symbolic nodal analysis of circuits using patholog- ical elements. IEEE Trans Circuits Syst II Express Briefs 57(11):874-877
Saad RA, Soliman AM (2008) Use of mirror elements in the active device synthesis by admit- tance matrix expansion. IEEE Trans Circuits Syst I Fundam Theory Appl 55(9):2726-2735
Tlelo-Cuautle E, Sánchez-López C, Moro-Frias D (2010) Symbolic analysis of (MO)(I)CCI(II)(III)-based analog circuits. Int J Circuit Theory Appl 38(6):649-659
Tlelo-Cuautle E, Sánchez-López C, Martinez-Romero E, Tan SX-D (2010) Symbolic analysis of analog circuits containing voltage mirrors and current mirrors. Analog Integr Circuits Signal Process 65(1):89-95
Fakhfakh M, Tlelo-Cuautle E, Fernández FV (2012) Design of Analog Circuits through Symbolic Analysis. Bentham Sciences Publishers Ltd., United Arab Emirates
Tlelo-Cuautle E, Martinez-Romero E, Sánchez-López C, Tan SX-D (2010) Symbolic be- havioral modeling of low voltage amplifiers. IEEE international confernce on electrical engineering, computing science and automatic control (CCE), México, pp 510-514
Rodriguez-Chavez S, Tlelo-Cuautle E, Palma-Rodriguez AA, Tan SX-D (2012) Symbolic DDD-based tool for the computation of noise in CMOS analog circuits. International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico
Shi G (2011) A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits. Analog Integr Circuits Signal Process. doi: 10.1007/s10470-011-9773-8
Tan SX-D, Liu X-X, Molinar E, Tlelo-Cuautle E (2012) Parallel symbolic analysis of large analog circuits on GPU platforms. In: VLSI Design, InTech Publisher. Available via InTech- Open Science
Souliotis G, Haritantis I (2008) Current-mode filters based on current mirror arrays. Int J Circuit Theory Appl 36:173-183
Duarte-Villaseñor MA, Tlelo-Cuautle E, Gerardo de la Fraga L (2011) Binary genetic encoding for the synthesis of mixed-mode circuit topologies. Circuits Syst Signal Process. doi:10.1007/s00034-011-9353-2
Martens E, Gielen G (2008) Classification of analog synthesis tools based on their architecture selection mechanisms. Integr VLSI J 41:238-252
Biolek D, Senani R, Biolkova V, Kolka Z (2008) Active elements for analog signal processing: classification, review, and new proposals. Radioengineering 17(4):15-32
Sedra A, Smith KC (1968) The current conveyor: a new circuit building block. Proc IEEE 56:1368-1369
Mobarak M, Onabajo M, Silva-Martinez J, et al (2010) Attenuation-predistortion linearization of CMOS OTAs with digital correction of process variations in OTA-C filter applications. IEEE J Solid State Circuits 45(2):351-367
Abhirup L, Maneesha G (2011) Realizations of grounded negative capacitance using CFOAs. Circuits Syst Signal Process 30(1):143-155
Gupta SS, Bhaskar DR, Senani R, et al (2011) Synthesis of linear VCOs: the state-variable approach. J Circuits Syst Comput 20(4):587-606
Soliman AM (2011) Generation of CFOA, CCII and DVCC based oscillators from passive RLC filter. J Circuits Syst Comput 20(4):621-639
Trejo-Guerra R, Tlelo-Cuautle E, Sánchez-López C, Muñoz-Pacheco JM, Cruz-Hernández C (2010) Realization of multiscroll chaotic attractors by using current-feedback operational amplifiers. Revista Mexicana de Fisica 56(4):268-274
Saad RA, Soliman AM (2010) A new approach for using the pathological mirror elements in the ideal representation of active devices. Int J Circuit Theory Appl 38(2):148-178
Biolek D, Bajer J, Biolkova V, et al (2011) Z copy-controlled gain-current differencing buffered amplifier and its applications. Int J Circuit Theory Appl 39(3):257-274
Sánchez-López C, Martinez-Romero E, Tlelo-Cuautle E (2011) symbolic analysis of OTRAs- Based circuits. J Appl Res Technol 9(1):69-80
Sánchez-López C, Fernández FV, Tlelo-Cuautle E (2010) Generalized admittance matrix models of OTRAs and COAs. Microelectronics J 41(8):502-505
Tlelo-Cuautle E, Duarte-Villaseñor MA, Garcia-Ortega JM, Sánchez-López C (2007) Design- ing SRCOs by combining SPICE and Verilog-A. Int J Electronics 94(4):373-379
Tlelo-Cuautle E (2011) Advances in analog circuits. InTech Publisher. Online Available http://www.intechweb.org/books/show/title/advances-in-analog-circuits
Tlelo-Cuautle E, Torres-Muñoz D, Torres-Papaqui L (2005) On the computational synthesis of CMOS voltage followers. IEICE Trans Fundam Electronics Commun Comput Sci E88- A(12):3479-3484
Carvajal RG, Ramirez-Angulo J, López-Martin A, Torralba A, Galán J, Carlosena A, Muñoz F (2005) The flipped voltage follower: a useful cell for low-voltage low-power circuit design. IEEE Trans Circuits Syst II 52(7):1276-1291
Gupta SS, Senani R (2006) New voltage-model/current-mode universal biquad filter using unity-gain cells. Int J Electronics 93(11):769-775
Sánchez-López C, Castro-Hernandez A, Perez-Trejo A (2008) Experimental verification of the Chua's circuit designed with UGCs. IEICE Electron Express 5(17):657-661
Trejo-Guerra R, Tlelo-Cuautle E, Jiménez-Fuentes JM, Muñoz-Pacheco JM, Sánchez-López C (2011) Multiscroll floating gate based integrated chaotic oscillator. Int J Circuit Theory Appl. doi:10.1002/cta.821
Tlelo-Cuautle E, Guerra-Gómez I, Reyes-Garcia CA, Duarte-Villaseñor MA (2010) Synthesis of analog circuits by genetic algorithms and their optimization by particle swarm optimization. In: Chiong R (ed) Intelligent systems for automated learning and adaptation: emerging trends and applications. Information Science Reference: IGI Global, pp 173-192
Tlelo-Cuautle E, Guerra-Gómez I, Duarte-Villaseñor MA, de la Fraga LG, Flores-Becerra G, Reyes-Salgado G, Reyes-Garcia CA, Rodriguez-Gómez G (2010) Applications of evolutionary algorithms in the design automation of analog integrated circuits. J Appl Sci 10(17):1859-1872
Tlelo-Cuautle E, Guerra-Gómez I, de la Fraga LG, Flores-Becerra G, Polanco-Martagón S, Fakhfakh M, Reyes-Garcia CA, Rodriguez-Gómez G, Reyes-Salgado G (2011) Evolutionary algorithms in the optimal sizing of analog circuits. In: Koeppen M, Schaefer G, Abraham A (eds.) Intelligent computational optimization in engineering: techniques & applications, vol 366. Springer, Hershey, PA, pp 109-138
Deb K, Pratap A, Agarwal S, Meyarivan T (2002) A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans Evol Comput 6(2):182-197
Zhang QF, Li H (2007) MOEA/D: a multiobjective evolutionary algorithm based on decompo- sition. IEEE Trans Evol Comput 11(6):712-731
Polanco-Martagón S, Reyes-Salgado G, Flores-Becerra G, Guerra-Gómez I, Tlelo-Cuautle E, de la Fraga LG, Duarte-Villaseñor MA (2012) Selection of MOSFET sizes by fuzzy sets intersection in the feasible solutions space. J Appl Res Technol 10(2) In press References
Carlin HJ, Youla DC (1961) Network synthesis with negative resistor. Proceeding IRE 49:907-920
Carlin HJ (1964) Singular network elements. IEEE Trans Circuit Theory 11:67-72
Kumar P, Senani R (2002) Bibliography on nullor and their applications in circuit synthesis and design. Analog Integr Circuits Signal Process 33:65-76
Nordholt EH (1982) Extending op-amp capabilities by using a current-source power supply. IEEE Trans Circuits Syst 29:411-412
Steveanson JK (1984) Two-way circuits with inverse transmission properties. Electron Lett 20:965-967
Huijsing JH (1990) Operational floating amplifier. IEE Proc 137:131-136
Senani R (1987) A novel application of four-terminal floating nullor. IEEE Proc 75:1544-1546
Cam U, Kuntman H (1999) CMOS four terminal floating nullor design using a simple approach. Microelectron J 30:1187-1197
Cam U, Toker A, Kuntman H (2000) CMOS FTFN realization based on translinear cells. Electron Lett 36:1255-1256
Cam U, Kuntman H (2000) A new CMOS realisation of a four terminal floating nullor (FTFN). Int J Electron 87:809-817
Alzaher H, Ismail M (2002) A CMOS fully balanced four terminal floating nullor. IEEE Trans CAS-I: Fundam Theory Appl 49:413-424
Mitra SK (1969) Analysis and synthesis of linear networks. John Wiley & Sons, Inc. New York
Senani R (1987) Generation of new two amplifier floating inductors. Electron Lett 23:1202-1203
Higashimura M, Fukui Y (1988) Novel method for realizing higher-order immittance function using current conveyors. IEEE Int Symp CAS 3:2677-2680
Higashimura M, Fukui Y (1988) Realisation of impedance function using current conveyors. Int J Electron 65:223-231
Walter N, Cox Jr, Su KL, Woodland RP (1971) A floating three terminal nullor and the universal impedance converter. IEEE Trans Circuit Theory 18:399-400
Huijsing JH (1993) Design and applications of the operational floating amplifier (OFA): the most universal amplifier. Analog Integr Circuits Signal Process 4:115-129
Mahmood SA, Soliman AM (1998) The differential difference operational floating amplifier: a new block for analog signal processing in MOS technology. IEEE Trans CAS-II: Analog Digital Signal Process 45:148-158
Hanspeter Schmid (2003) Comments on "A CMOS Fully Balanced Four-Terminal Floating Nullor". IEEE Trans CAS-I: Fundam Theory Appl 50:1601
Higashimura M (1991) Realization of current-mode transfer function using four terminal floating nullor. Electron Lett 22:170-171
Normand G (1986) Floating impedance realization using a dual operational mirrored amplifier. Electron Lett 22:521-522
Senani R (1994) On the equivalent form of single op-amp sinusoidal RC oscillators. IEEE Trans CAS-I: Fundam Theory Appl 41:617-624
Huijsing JH, Dekorte J (1977) Monolithic nullor-A universal active network element. IEEE J Solid State Circuits 12:59-64
Tangsrirat W, Unhavanich S, Dumawipata T, Surakampotorn W (2001) FTFN with variable current gain. Electric Electron Technol 1:209-212
Jiraseri-amornkun A, Chipipop B, Surakampontorn W (2001) Novel translinear-based multi- output FTFN. In: Circuits and Systems, ISCAS Sydney, NSW, Australia
Antoniou A (1969) Realization of gyrator using operational amplifier and their use in RC- active-network synthesis. Proc IEE 116:1838-1850
Senani R (1986) On the realization of floating active elements. IEEE Trans CAS 33:323-324
The LO, Yanagisawa Y (1977) Some new lossless floating inductance circuits. Proc IEEE 66:1071-1072
Riordan RHS (1966) Simulated inductors using differential amplifier. Electron Lett 3:50-51
Cabeza R, Carlosena A (1997) Analog universal active device: theory, design, applications. Analog Integr Circuits Signal Process 12:153-168
Cam U, Cicekogulu O, Kuntman H (2001) Novel lossless floating imittance simulator employing only two FTFNs. Analog Integr Circuits Signal Process. 29:233-235; also see ibid Gandhi G (2002) comments on Novel lossless floating imittance simulator employing only two FTFNs. 32:191
Pauker VM (1970) Equivalent networks with nullors for positive immittance inverter. IEEE Trans Circuit Theory 17:642-645
Senani R (1980) New tunable synthetic floating inductors. Electron Lett 16:382-383
Pal K (1980) Novel floating inductance using current conveyor. Electron Lett 17:638-639
Pal K (1981) New inductance and capacitance floating scheme using current conveyor. Electron Lett 17:807-808
Singh V (1981) Active-RC single resistance controlled lossless floating inductance simulation using a single grounded capacitor. Electron Lett 17:920-921
Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E (2010) Generalized admittance matrix models of OTRAs and COAs. Microelectron J 41:502-505
Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E (2011) Pathological element-based active device models and their application to symbolic analysis. IEEE Trans Circuits Syst 1 58:1382-1395
Tlelo-Cuautle E, Duarte-Villasenor MA, Guerra-Gomez I (2008) Automatic synthesis of VFs and VMs by applying genetic algorithms. Circuits Syst Signal Process 27:391-403
Smith KC, Sedra A (1968) The current conveyor-A new circuit building block. Proc IEEE 56:1368-1369
Sedra A, Smith KC (1970) A second-generation current conveyor and its applications. IEEE Trans Circuit Theory CT-17:132-134
Toumazou C, Lidgey FJ (1994) Current feedback op-amps: A blessing in disguise? IEEE Circuits Devices Mag 10:34-37
Fabre A (1992) Gyrator implementation from commercially available transimpedance opera- tional amplifiers. Electron Lett 28:263-264
Soliman AM (1996) Application of the current feedback operational amplifiers. Analog Integr Circuits Signal Process 11:265-302
Lidgey FJ, Hayatleh K (1997) Current-feedback operational amplifiers and applications. Electron Commun Eng J 9:176-182
Senani R (1998) Realization of a class of analog signal processing/signal generation circuits: novel configurations using current feedback op-amps. Frequenz 52:196-206
Gilbert B (1975) Translinear circuits: a proposed classification. Electron Lett 11:14-16
Analog Devices, Linear Products Data Book, Norwood, MA, 1990
Wilson B (1989) Universal conveyor instrumentation amplifier. Electron Lett 25:470-471
Martinez PA, Celma S, Sabadell S (1996) Designing sinusoidal oscillators with current- feedback amplifiers. Int J Electron 80:637-646
Senani R, Singh VK (1996) Synthesis of canonic single-resistance-controlled-oscillators using a single current-feedback-amplifier. IEE Proc Circuits Devices Syst 143:71-72
Nikoloudis S, Psychalinos C (2010) Multiple input single output universal biquad filter with current feedback operational amplifiers. Circuits Syst Signal Process 29:1167-1180
Gupta SS, Senani R (1998) State variable synthesis of single-resistance-controlled grounded capacitor oscillators using only two CFOAs: additional new realizations. IEE Proc Circuits Devices Syst 145:415-418
Bhaskar DR (2003) Realization of second-order sinusoidal oscillator/filters with non- interacting controls using CFAs. FREQUENZ: J Telecommun 57:12-14
Senani R, Gupta SS (1997) Synthesis of single resistance controlled oscillators using CFOAs: simple state variable approach. IEE Proc Circuits Devices Syst 144:104-106
Bhaskar DR, Senani R (2006) New CFOA-based single-element-controlled sinusoidal oscilla- tors. IEEE Trans Instrum Meas 55:2014-2021
Abuelma'atti MT (2011) New two CFOA-based sinusoidal RC oscillators with buffered outlet. Analog Integr Circuits Signal Process 66:475-482
Senani R (1979) Novel active RC circuit for floating inductor simulation. Electron Lett 15:679-680
Senani R (1980) New tunable synthetic floating inductors. Electron Lett 16:382-383
Senani R (1986) On the realization of floating active elements IEEE Trans Circuits Syst 33:323-324
Senani R, Bhaskar DR, Gupta SS, Singh VK (2009) A configuration for realizing floating, linear, voltage-controlled resistance, inductance and FDNC elements. Int J Circuits Theory Appl 37:709-719
Singh VK, Singh AK, Bhaskar DR, Senani R (2005) Novel mixed-mode universal biquads configuration. IEICE Electron Express l2:548-553
Liu, SI, Chen, JJ (1995) Realisation of analogue divider using current feedback amplifiers. IEE Proc Circuits Devices Syst 142:45-48
Mahmoud SA, Soliman AM (1998) Novel MOS-C balanced-input balanced-output filter using the current feedback operational amplifier. Int J Electron 84:479-485
Anwar KA, Abou El-Ela M, Al-Turaigh MA (1995) Current mode precision rectification. Int J Electron 79(6):853-859
Abuelma'atti MT, Al-Shahrani SM (1998) New CFOA-based triangular/square wave generator. Int J Electron 84:583-588
Acar C, Ozoguz S (1999) New versatile building block: current differencing buffered amplifier for analog signal processing filters. Microelectron J 30:157-160
Chen JJ, Tsao HW, Chen CC (1992) Operational transresistance amplifier using CMOS technology. Electron Lett 28:2087-2088
Biolek D (2003) CDTA-building block for current-mode analog signal processing. ECCTD'03. III:397-400
Yuce E, Minaei S (2007) Realisation of various active devices using commercially available AD844s and external resistors. Electron World 113:46-49
Tammam AA, Hayatleh K, Lidgey FJ (2003) High CMRR current-feedback operational amplifier. Int J Electron 90:87-97
Hayatleh K, Tammam AA, Hart BL, Lidgey FJ (2007) A novel current-feedback op-amp exploiting bootstrapping techniques. Int J Electron 94:1157-1170
Mita R, Palumbo G, Pennisi S (2005) Low-voltage high-drive CMOS current feedback Op-amp. IEEE Trans Circuits Syst II 52:317-321
Soliman AM, Awad IA (2005) Fully differential CMOS current feedback operational amplifier. Analog Integr Circuits Signal Process 43:61-69
Catalado GD, Grasso AD, Pennisi S (2007) Two CMOS current feedback operational amplifiers. IEEE Trans Circuits Syst II 54:944-948
Torres-Papaqui L, Tlelo-Cuautle E (2004) Synthesis of CCs and CFOAs by manipulation of VF and CFs. In: Behavioral modeling and simulation conference. Proceedings of the 2004 IEEE International, pp. 92-96
Yuce E (2010) Fully integrable mixed-mode universal biquads with specific application of the CFOA. Int J Electron Commun (AEU) 64:304-309
Gunes EO, Toker A (2002) On the realization of oscillators using state equations. Int J Electron Commun (AEU) 56:1-10
Gupta SS, Senani R (2005) New grounded-capacitor SRCOs using a single differential- difference-complementary-current-feedback-amplifier. IEE Proc Circuits Devices Syst 152:38-48
Yuce E, Minaei S (2008) A modified CFOA and its applications to simulated inductors, capacitance, multipliers, and analog filters. IEEE Trans CAS-I 55:266-275
Smith KC and Sedra AS (1970) Realization of Chua family of new nonlinear network elements using current conveyors. IEEE Trans Circuit Theory 17:137-139
Soliman AM (2009) Generation of oscillators based on grounded capacitor current conveyors with minimum passive components. J Circ Syst Comput 18:857-873
Soliman AM (2011) Generation of the minimum component oscillators from Sallen Key filters. J Circ Syst Comput 20:1165-1183
Bhattacharyya BB, Sundaramurthy M, Swamy MNS (1981) Systematic generation of canonic sinusoidal RC active oscillators. IEE Proc Circ Dev Syst 128:114-126
Celma S, Martinez PA, Carlosena A (1994) Approach to the synthesis of canonic RC-active oscillators using CCII. IEE Proc Circ Dev Syst 141:493-497
Abuelmatti MT (1987) Two minimum components CCII based RC oscillators. IEEE Trans Circ Syst 34:980-981
Svoboda JA (1989) Current conveyors operational amplifiers and nullors. IEE Proc Circ Dev Syst 136:317-322
Budak A, Nay K (1981) Operational amplifier circuits for Wien bridge oscillators. IEEE Trans Circ Syst 28:930-934
Soliman AM, Al-Shamaa MH, Dak Al-Bab M (1988) Active compensation of RC oscillators. Frequenz 42:325-332
Martinez PA, Celma S, Gutierrez I (1995) Wien type oscillators using CCII+. Analog Integr Circ Sig Process 7:139-147
Sedra AS, Smith KC (1970) A second generation current conveyor and its applications. IEEE Trans Circ Theor 132:132-134
Awad IA, Soliman AM (1999) Inverting second generation current conveyors: the missing building blocks, CMOS realizations and applications. Int J Electron 86:413-432
Haigh DG, Clarke TJW, Radmore PM (2006) Symbolic framework for linear active circuits based on port equivalence using limit variables. IEEE Trans Circ Syst I 53:2011-2024
Sanchez-Lopez C, Fernandez FV, Tlelo-Cuautle E, Tan SXD (2011) Pathological element- based active device models and their application to symbolic analysis. IEEE Trans Circ Syst I 58:1382-1395
Saad RA, Soliman AM (2008) Use of mirror elements in the active device synthesis by admittance matrix expansion. IEEE Trans Circ Syst I 55:2726-2735
Soliman AM (2010) Generation of current conveyor based oscillators using nodal admittance matrix expansion. Analog Integr Circ Sig Process 65:43-59
Fongsamut C, Anuntahirunrat K, Kumwachara K, Surakampontorn W (2006) Current- conveyor-based single element controlled and current controlled sinusoidal oscillators. Int J Electron 93:467-478
Director SW, Rohrer RA (1969) The generalized adjoint network and network sensitivities. IEEE Trans Circ Theor 16:318-323
Horng JW (2001) A sinusoidal oscillator using current-controlled current conveyors. Int J Electron 88:659-664
Horng JW, Chang CW, Lee MH (1997) Single-element-controlled sinusoidal oscillators using CCIIs. Int J Electron 83:831-836
Soliman AM (1997) In-sensitive band-pass Filter. Electron Eng 69:18-20
Soliman AM (2011) Generation of oscillators from current mode band-pass filters using single output ICCII. Journal of Active and Passive Electronic Devices 6:251-264
Saad RA, Soliman AM (2008) Generation, modeling, and analysis of CCII-based gyrators using the generalized symbolic framework for linear active circuits. Int J Circ Theor Appl 36:289-309
Soliman AM (1975) Simple sinusoidal active RC oscillators. Int J Electron 39:455-458
Haigh DG, Tan FQ, Papavassiliou C (2005) Systematic synthesis of active-RC circuit building- blocks. Analog Integr Circ Sig Process 43:297-315
Soliman AM (1998) Generation of CCII and CFOA Filters from passivwe RLC filters. Int J Electron 85:293-312
Haigh DG, Clarke TJ, Radmore PM (2006) Symbolic framework for linear active circuits based on port equivalence using limit variables. IEEE Trans Circ Syst I, Regular Papers 53(9):2011-2024
Biolek D, Biolkova V (2011) Modified nodal analysis. In: Fakhfakh M, Tlelo-Cuautle E, Fernandez FV (eds) Design of analog circuits through symbolic analysis. Bentham Science Publisher, United Arab Emirates
Haigh DG, Radmore PM (2006) Admittance models for the nullor using limit variables and their applications to circuit design. IEEE Trans Circ Syst I, Regular Papers 53(10):2214-2223
Haigh DG (2006) A method of transformation from symbolic transfer function to active RC-circuits by admittance matrix expansion. IEEE Trans Circ Syst I, Regular Papers 53(12):2715-2728
Mielke RR (1978) A new signal flowgraph formulation of symbolic network functions. IEEE Trans Circ Theor CT-25(6):334-340
Lin P-M (1991) Symbolic network analysis.Elsevier Amsterdam
Rodanski BS, Hassoun M (2003) Symbolic analysis. In: Chen, WK (ed) The circuits and filters handbook, CRC Press, New York
Pierzchala M, Rodanski B (2004) Two-graph stamps for linear controlled sources. In: The international workshop on symbolic analysis and application in circuit design, SMACD. Wroclaw, Poland
Pierzchala M, Fakhfakh M (2011) Tranformation of LC-filters to active RC-circuits via the two-graph method. Microelectronic J 42(8):999-1005
Rodanski B (2002) Extension of the two-graph method for symbolic analysis of circuits with non-admittance elements. In: The international workshop on symbolic analysis and application in circuit design, SMACD, Sinaia, Romania
Pierzchala M, Fakhfakh M (2008) An open environment for calculating expanded symbolic network function. In: The international workshop on symbolic and numerical methods, modelling and application in circuit design, SM2ACD. Erfurt, Germany References
Faria G, Henriksson JA, Stare E, Talmola P (2006) DVB-H: digital broadcast services to handheld devices. Proc IEEE 94(1):194-209
European Information & Communications Technology Industry Association (EICTA): Mobile and Portable DVB-T Radio Access Interface Specification,Version 1.0. Jan 2004
Vejlgaard B, Mopensen P, Knudsen JB (1999) Performance analysis for UMTS downlink receiver with practical aspects. In: Proceedings of IEEE Vehicular Technology Conference, pp 998-1002
Razavi B (1999) CMOS RF Receiver Design for Wireless LAN Applications. In: Proceedings of IEEE Radio and Wireless Conference, pp 275-280
Giannini V, Craninckx J, Baschirotto A (2008) Baseband analog circuits for software defined radio. Springer, Berlin, Germany
Jussila J, Halonen K (2004) Minimization of power dissipation of analog channel-select filter and Nyquist-rate A/D converter in UTRA/FDD. In: Proceedings of ISCAS 2004, pp IV-940-3
Norsworthy J. Broadband tuners for modern systems, [Online]. Available: http:// mobiledevdesign.com/images/archive/0601Norsworthy67.pdf
Sheng S (2009) Mobile television receivers: a free-to-air overview. IEEE Commun Mag 47(9):142-149
Le B, Rondeau TW, Reed JH, Bostian CW (2005) Analog-to-digital converters. IEEE Signal Process Mag 22(6):69-77
Murmann B (2006) Limits on ADC power dissipation. In: Steyaert M, Roermund AHM, Huijsing JHv (eds) Analog circuit design. Springer, Berlin, Germany
Murmann B. ADC performance survey 1997-2010 [Online]. Available: http://www.stanford. edu/ " murmann/adcsurvey.html
Razavi B (1998) Basic concepts in RF design. In: RF microelectronics. Prentice Hall, NJ
Xiao J (2007) CMOS RF Front-end design for terrestrial and mobile digital television systems, Ph.D. dissertation, Dept. Electr. Comput. Eng., Texas A&M Univ., College Station, TX
Antoine P, Bauser P, Beaulaton H, Buchholz M, Carey D, Cassagnes T, Chan TK, Colomines S, Hurley F, Jobling DT, Kearney N, Murphy AC, Rock J, Salle D, Cao-Thong T (2005) A direct-conversion receiver for DVB-H. IEEE J Solid State Circuits 40(12):2536-2546
Womac M, Deiss A, Davis T, Spencer R, Abesingha B, Hisayasu P (2006) Dual-band single- ended-input direct-conversion DVB-H receiver. In: IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb 2006, pp 610-611
Iizuka K, Kawamura H, Fujiwara T, Kagoshima K, Kawama S, Kijima H, Koutani M, Toyoyama S, Sakuno K (2007) A 184mW fully integrated DVB-H tuner with a linearized variable gain LNA and quadrature mixers using cross-coupled transconductor. IEEE J Solid State Circuits 42(4):862-871
Vassiliou I, Vavelidis K, Bouras S, Kavadias S, Kokolakis Y, Kamoulakos G, Kyranas A, Kapnistis C, Haralabidis N (2006) A 0.18μm CMOS Dual-band direct conversion receiver. In: IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2006, pp 606-607
Kim YJ, Kim JW, Parkhomenko VN, Baek D, Lee JH, Sung EY, Nam L, Park BH (2006) A multi band multi-mode CMOS direct conversion DVB-H tuner. In: IEEE International Solid- State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2006, pp 608-609
Vassiliou I, Vavelidis K, Haralabidis N, Kyranas A, Kokolakis Y, Bouras S, Kamoulakos G, Kapnistis C, Kavadias S, Kanakaris N, Metaxakis E, Kokozidis C, Peyravi H (2008) A 65 nm CMOS multistandard, multiband TV tuner for mobile and multimedia applications. IEEE J Solid State Circuits 43(7):1522-1533
Kuo M-C, Kao S-W, Chen C-H, Hung T-S, Shih Y-S, Yang T-Y, Kuo C-N (2009) A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 μm CMOS. IEEE J Solid State Circuits 44(3):740-750
Cho TB, Chien G, Brianti F, Gray PR (1996) A power-optimized CMOS baseband channel filter and ADC for cordless applications. In: Symposium on VLSI Circuits Digest, June 1996, pp 64-65
Azuma S, Kawama S, Iizuka K, Miyamoto M, Senderowicz D (2002) Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. IEEE J Solid State Circuits 37(3):349-356
Kulkarni R, Kim J, Jeon H-J, Xiao J, Silva-Martinez J (2010) A broadband 470-862 MHz direct conversion CMOS receiver. In: Proceedings of ISCAS, pp 2227-2230
Kulkarni R, Kim J, Jeon H-J, Xiao J, Silva-Martinez J (2012) UHF receiver front-end: imple- mentation and analog baseband design considerations. IEEE Trans VLSI Syst. 20(2):197-210
Adut J, Silva-Martinez J, Rocha-Perez M (2006) A 10.7-MHz sixth-order SC ladder filter in 0.35μm CMOS technology. IEEE Trans Circuits Syst I Reg Papers 53(8):1625-1635
Horlin F, Bourdoux A (2008) Digital compensation for analog front-ends: a new approach to wireless transceiver design. Wiley, New York References
Brandolini M et al (2005) Toward multistandard mobile terminals -Fully integrated receivers requirements and architectures. IEEE Trans Microw Theor Tech 53:1026-1038
Mak PI, Martins RP (2007) Transceiver architecture selection: review, state-of-the-art survey and case study. IEEE Circ Syst Mag, Second Quarter, pp. 6-25. (ISSN: 1531-636X)
Vidojkovic V et al (2004) Fully-integrated DECT/Bluetooth multi-band LNA in 0.18μm CMOS. Proceedings of IEEE international symposium on circuits and systems, pp 565-568
Koolivand Y et al (2005) A new technique for design CMOS LNA for multi-standard receivers. Proc IEEE Int Symp Circ Syst 4:3231-3234
Hashemi H et al (2002) Concurrent multiband low-noise amplifiers-theory, design, and applications. IEEE Trans Microw Theor Tech 50:288-301
Ang C-W et al (2007) A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless Receivers. Proceedings of IEEE international symposium on circuits and systems, pp 2802-2805
Hsieh H-H et al (2008) Gain-enhancement techniques for CMOS folded cascode LNAs at low-voltage operations. IEEE Trans Microw Theor Tech 56(8):1807-1816
Ahola R (2004) A single-chip CMOS transceiver for IEEE 802.11a/b/g wireless LANs. Proc IEEE J Solid State Circ, pp 2250-2258
Li X, Ismail M (2002) Multi-standard CMOS wireless receivers: analysis and design. Kluwer Academic Publishers, New York
Li Z et al (2004) A dual-band CMOS front-end with two gain modes for wireless LAN applications. IEEE J Solid State Circ 39:2069-2073
Wang C-S et al (2005) A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications. Proceedings of IEEE international symposium on circuits and systems (ISCAS), pp 3974-3977
Liscidini A et al (2006) A 0.13μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. IEEE J Solid State Circ 41:981-989
Wu C, Lu L (2006) A 2.9-3.5-GHz tunable low-noise amplifier. Proceedings of the 2006 IEEE silicon monolithic integrated circuits in RF systems (SiRF), pp 206-209
Zhan J-H et al (2006) A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications. Proceedings of IEEE solid-state circuits conference, pp 721-730
Martins M et al (2007) Techniques for dual-band LNA design using cascode switching and inductor magnetic coupling. Proceedings of IEEE international symposium on circuits and systems (ISCAS), pp 1449-1452
Vidojkovic M et al (2007) A broadband, inductorless LNA for multi-standard applications. Proceedings of European conference on circuit theory and design, pp 260-263
Shaeffer D et al (1997) A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J Solid State Circ 32:745-759
Song H et al (2008) A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applica- tions. IEEE Microw Wireless Compon Lett 18:212-214
Tividis Y (2003) Operation and modelling of the MOS transistor, 2nd edn. Oxford Press, New York
Lee TH (2004) The design of CMOS radio-frequency integrated circuits, 2nd edn. Cambrige University Press, Cambridge
Abou-Allam E et al (2001) Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology. IEEE J Solid State Circ 36:1434-1443
Hioe W et al (2004) 0.18μm CMOS Bluetooth analog receiver with -88-dBm sensitivity. IEEE J Solid State Circ 39:374-377
Jarvinen J et al (2004) 2.4-GHz receiver for sensor applications. Proceedings of the European solid-state circuits conference, pp 91-94
Komurasaki H et al (2003) A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications. IEEE J Solid State Circ 38:817-825
Rogin J et al (2003) A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13μm CMOS. IEEE J Solid State Circ 38:2239-2248
Sjoland H et al (2003) A merged CMOS LNA and mixer for a WCDMA receiver. IEEE J Solid State Circ 38:1045-1050
Sivonen P et al (2006) A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13μm CMOS. IEEE J Solid State Circ 41:384-394
Tiebout M et al (2002) LNA design for a fully integrated CMOS single chip UMTS transceiver. Proceedings of the European solid-state circuits conference, pp 835-838
Yang Y-C et al (2006) Reconfigurable SiGe low-noise amplifiers with variable miller capaci- tance. IEEE Trans Circ Syst 53:2567-2577
Andreani P et al (2001) Noise optimization of an inductively degenerated CMOS low noise amplifier. IEEE Trans Circ Syst II: Analog and Digit Signal Process 48:835-841
Hsiao C-L et al (2003) A 1V fully differential CMOS LNA for 2.4GHZ application. Proceedings of the 2003 international symposium on circuits and systems (ISCAS), vol 1, pp 245-248
Cha C-Y et al (2002) A 5.2GHz LNA in 0.35μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. Proceedings of the European solid-state circuits conference, pp 339-342
Cha C-Y et al (2003) A 5.2-GHz LNA in 0.35μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. IEEE J Solid State Circ 38:669-672
Dupuis O et al (2005) 24GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors. Proceedings of the European solid-state circuits conference, pp 89-92
Fujimoto R et al (2002) A 7-GHz 1.8-dB NF CMOS low-noise amplifier. IEEE J Solid State Circ 37:852-856
Goo J-S et al (2002) A noise optimization technique for integrated low-noise amplifiers. IEEE J Solid State Circ 37:994-1002
Han K et al (2005) Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier. IEEE J Solid State Circ 40:726-735
Linten D et al (2004) A 5 GHz fully integrated ESD-protected low-noise amplifier in 90nm RF CMOS. Proceedings of the European solid-state circuits conference, pp 291-294
Linten D et al (2005) A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. IEEE J Solid State Circ 40:1434-1442
White JF (2004) High frequency techniques -An introduction to RF and microwave engineer- ing. Wiley, Hoboken
Everard J (2001) Fundamentals of RF circuit design with low noise oscillators. Wiley, Chichester
Leenaerts D et al (2001) Circuit design for RF transceivers. Kluwer Academic Publishers, Boston
Stenman A-K (2001) Some design aspects on RF CMOS LNAs and mixers. PhD thesis, Lund University
Fu C-T et al (2007) A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistan- dard wireless receiver. Proceedings of IEEE radio frequency integrated circuits symposium, pp 65-68
Wu C-R et al (2006) A 2.9-3.5-GHz tunable low-noise amplifier. Topical meeting on silicon monolithic integrated circuits in RF systems, pp 206-209
Kao S-W et al (2005) A low-power dual-band WLAN CMOS receiver. Proceedings of Asian solid-state circuits conference, pp 397-400
Tzeng F et al (2008) A multiband inductor-reuse CMOS low-noise amplifier. IEEE Trans Circ Syst II: Express Briefs 55:209-213
Sandner C, Clara M, Santner A, Hartnig T, Kuttner F (2005) A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13μm Digital CMOS, IEEE proceedings of design, automation and test in Europe conference and exhibition (DATE'05), vol 3, pp 223-226
Uyttenhove K, Steyaert M (2001) A CMOS 6-bit, 1 GHz ADC for IF Sampling Applications, IEEE MTT-S international microwave symposium digest, vol 3, pp 2131-2134, May 2001
Park S, Palaskas Y, Flynn MP (2006) A 4GS/s 4b Flash ADC in 0.18μm CMOS, IEEE International Solid-State Circuits Conference, pp 570-571, Feb 2006
Paulus C, Blüthgen H-M, Löw M, Sicheneder E, Brüls N, Courtois A, Tiebout M, Thewes R (2004) A 4GS/s 6b Flash ADC in 0.13μm CMOS, Digest of symposium on VLSI circuits, pp 420-423, June 2004
Klar H (1996) Integrierte Digitale Schaltungen MOS/BICMOS. Springer, Berlin
Veendrick HJM (1980) The behaviour of flip-flops used as synchronizers and prediction of their failure rate. IEEE J Solid State Circ 15(2):169-176
Gregorian R (1999) Introduction to CMOS Op-amps and comparators. Wiley, New York
Figueiredo PM, Vital JC (2006) Kickback noise reduction techniques for CMOS latched comparators. IEEE Trans Circ Syst II 53(7):541-545
Lohstroh J (1983) Worst-case static noise margin criteria for logic circuits and their mathemat- ical equivalence. IEEE J Solid State Circ 18(6):803-807
Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid State Circ 22(5):748-754
Bhavnagarwala AJ, Tang X, Meindl JD (2001) The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J Solid State Circ 36(4):658-665
Weinrichter H, Hlawatsch F (1991) Stochastische Grundlagen nachrichtentechnischer Signale. Springer, New York
Nikoozadeh A, Murmann B (2006) An analysis of latch comparator offset due to load capacitor mismatch. IEEE Trans Circ Syst II 53(12):1398-1402
Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J Solid State Circ 24(5):1433-1440
Lakshmikumar KR, Hadaway RA, Copeland MA (1986) Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J Solid State Circ sc- 21(6):1057-1066
Schneider K, Zimmermann H (2006) Highly sensitive optical receivers. Springer, Berlin
Kobayashi T, Nogami K, Shirotori T, Fujimoto Y (1993) A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J Solid State Circ 28(4):523-527
Wicht B, Nirschl T, Schmitt-Landsiedel D (2004) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid State Circ 39(7):1148-1158
Schinkel D, Mensink E, Klumpernik E, van Tuijl E , Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18ps setup + hold time. IEEE international solid-state circuits conference, pp 314-315, Feb 2007
Annema A-J, Nauta B, van Langevelde R, Tuinhout H (2005) Analog circuits in ultra-deep- submicron CMOS. IEEE J Solid State Circ 40(1):132-143
Goll B, Zimmermann H (2007) A 0.12μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6GHz. IEEE international solid-state circuits conference, pp 316-317, Feb 2007
Goll B, Zimmermann H (2009) A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans Circ Syst II 56(11):810-814
Wang J (2008) Electrochemical glucose biosensors. Chem Rev 108:814-825
Islam AB, Islam SK, Rahman T (Dec. 2009) A Vertically Aligned Carbon Nanofiber (VACNF) based amperometric glucose sensor, Proceedings of the International Semiconductor Device Research Symposium (ISDRS 2009),College Park, MD, USA
Zhang M, Haider MR, Huque MA, Adeeb MA, Rahman S, Islam SK (Mar. 2007) A low- power sensor signal processing circuit for implantable biosensor applications. Smart Mater Struct 16:525-530
Baker DA, Gough DA (1995) A continuous, implantable lactate sensor. Anal Chem 67(9):1536-1540
Jeevarajan AS, Vani S, Taylor TD, Anderson MM (2002) Continuous pH monitoring in a perfused bioreactor system using an optical pH sensor. Biotechnol Bioeng 78(4):467-472
Star A, Han T-R, Joshi V, Gabriel J-C, Gruner G (Nov. 2004) Nanoelectronics carbon dioxide sensors. Adv Mater 16(22):2049-2052
Liu W, Vichienchom K, Clements M, DeMarco S, Hughes C, McGucken E, Humayun MS, Juan E, Weiland JD, Greenberg R (2000) A neuro-stimulus chip with telemetry unit for retinal prosthetic device. IEEE J Solid State Circ 35:1487-1497
Zierhofer CM, Hochmair-Desoyer IJ, Hochmair ES (1995) Electronic design of a cochlear implant for multichannel high-rate pulsatile stimulation strategies. IEEE Trans Rehabil Eng 3:112-116
Heetderks WJ (1988) RF powering of millimiter-and submillimeter-sized neural prosthetic implants. IEEE Trans Biomed Eng 35:323-327
Lenaerts B, Puers R (2007) An inductive power link for a wireless endoscope. Biosens Bioelectron 22:1390-1395
Guanying M, Guozheng Y, Xiu H (2007) Power transmission for gastrointestinal microsystems using inductive coupling. Physiol Meas 28:N9-N18
Sarpeshkar R (2010) Ultra low power bioelectronics: fundamentals, biomedical applications, and bio-inspired systems Cambridge University Press edition 1 Feb 22
Mandal S, Zhak S, Sarpeshkar R (2009) A bio-inspired active radio-frequency silicon cochlea. IEEE J Solid State Circ 44(6):1814-1828
Wee KH Turicchia L, Sarpeshkar R (2008) An analog integrated-circuit vocal tract. IEEE Transactions on Biomedical Circuits and Systems 2(4):316-327
Yang H, Sarpeshkar R (2006) A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications. IEEE Trans Circ Syst I 53(11):2349-2356
Grayson ACR, Shawgo RS, Johnson AM, Flynn NT, Yawen LI, Cima MJ, Langer R (Jan. 2004) A BioMEMS review: MEMS technology for physiologically integrated devices. Proceedings of the IEEE 92(1):6-21
Salwa Mostafa, Ida Lee, Syed K. Islam, Sazia A. Eliza, Gajendra Shekhawat, Vinayak P. Dravid, Fahmida S. (2011) Tulip, integrated MOSFET-embedded cantilever based biosensor characteristic for detection of anthrax simulant. IEEE Electron Dev Lett 32(2):408-410
Abdel-Aty-Zohdy HS (2008) Bio-inspired adaptive integrated information processing, IEEE National Aerospace and Electronics Conference (NAECON) 114-122
Milenkovic A, Otto C, Jovanov E (2006) Wireless sensor networks for personal health monitoring: issues and an implementation. Comput Comm 29:2521-2533
Joseph D (ed) (2000) In: handbook The biomedical engineering. CRC Press, Bronzino 21. Top targets for wireless health and mhealth. available online at https://www. wirelesshealthstrategies.com/targets.html
Daniel Mark, Stefan Haeberle, Günter Roth, Felix von Stetten, Roland Zengerle (2010) Microfluidic lab-on-a-chip platforms: requirements, characteristics and applications Chem Soc Rev 39:1153-1182
Wang J (2001) Glucose biosensors: 40 years of advances and challenges Electroanalysis 13:983-988
Elliot McGucken (1998) Multiple unit artificial retina chipset to aid the visually impaired and enhanced holed-emitter CMOS phototransistors. Ph. D. Dissertation, University of North Carolina at Chapel Hill
Schwiebert L, Gupta SKS and Weinmann J (2001) Research challenges in wireless networks of biomedical sensors, ACM, New York, USA
Cancer facts and figures (2011) available online at http://www.cancer.org/acs/groups/content/ @epidemiologysurveilance/documents/document/acspc-029771.pdf
Serdijn WA, Van Der Woerd AC, Roermund AHM, Davidse J (1995) Design principles for low- voltage low-power analog integrated circuits. Analog Integrated Circuits and Signal Processing 8:115-120
Nordholt EH (1983) Design of high-performance negative-feedback amplifier. Elsevier, Ams- terdam
Toumazou C, Lidgey FJ, Haigh DW (1990) Analogue IC design: the current-mode approach, Peter Peregrinus, London
Toumazou C, Hughes JB, Banersby NC (1993) Switched currents. An analogue technique for digital technology, Peter Peregrinus, London
Toumazou C, Battersby NC (May 1993) Switched-transcondcutance techniques: a new approach for tunable precision analogue sample-data signal processing. Proc IEEE ISCAS, Chicago
Bult K, Geelen GJGM (Dec. 1990) A fast-settling CMOS Opamp for SC circuits with 90-dB DC gain. IEEE J Solid State Circ 25(6):1379-1384
You F (1996) Low voltage analog circuit design. Ph. D. thesis, Texas A&M University, College Station, TX 77843, USA
Laker KR, Sansen WMC (1994) Design of analog integrated circuits and systems, McGraw- Hill. Inc., New York
Eschauzier RGH and Huijsing JH (1995) Frequency compensation techniques for low-power operational amplifiers,Kluwer MA, Boston
Iwai H (March 1999) CMOS technology -year 2010 and beyond, IEEE J Solid State Circ 34(3):357-366
Li EH and Ng HC (Nov. 1991) Parameter sensitivity of narrow channel MOSFET's, IEEE Electron Dev Lett 12(11):608-610
Yan S, Sanchez-Sinencio E (Feb. 2000) Low voltage analog circuit design techniques: a tutorial, invited paper in IEICE Trans Analog Integr Circ and Syst E00-A(2):1-17
Chee YH (2006) Ultra low power transmitter for wireless sensor networks. Ph. D. Dissertation, Dept of Electrical Engineering and Computer Science, University of California, Berkeley, Spring
Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr Circ Sig Process 8:83-114
Binkley DM, Blalock BJ, Rochelle JM (2006) Optimizing drain current, inversion level, and channel length in analog CMOS design. Analog Integr Circ Sig Process 47:137-163
Holleman J, Zhang F, Otis B (2011) Ultra low power circuit design for wireless neural interfaces Springer, New York
Harrison RR, Charles C (Jun 2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid State Circ 38(6):8
Guzinski A, Bialko M, Matheau JC (Sep 1987) Body driven differential amplifier for application in continuous time active-C filter. Proceedings of the European Conference on Circuit Theory and Design (ECCTD'87) 315-320 Paris, France
Blalock BJ, Allen PE, Rincon-Mora GAR (July 1998) Designing 1-V Op amps using standard digital CMOS technology IEEE Trans Circ Syst II 45:769-780
Chatterjee S, Tsividis Y, Kinget P (Sep 2004) A 0.5-V bulk-input fully differential operational transconductance amplifier Proceedings of the 30th European Solid-State Circuits Conference 147-150 Leuven, Belgium
Gray PR and Meyer RG (1984) Analysis and design of analog integratedcircuits. EWiley, New York
Rodr'iguez-V'azquez A and S'anchez-Sinencio E (eds) (Nov 1995) Special issue on low- voltage and low power analog and mixed-signal circuits and systems. IEEE Trans Circ Syst 42(11):825
Haider MR, Zhu K, Islam SK, Yuan S and Mahfouz M (2011) Phase noise optimization of a selfcascode VCO by changing the capacitor ratio and substrate bias. IEEE Radio and Wireless Symposium, Jan
Sackinger E, Guggenbuhl W (Dec. 1988) An analog trimming circuit based on a floating-gate device. IEEE J Solid State Circ 23(6):1437-1440
Mehrvarz HR, Kwok CY (Aug. 1996) A novel multi-input floating-gate MOS four-quadrant analog multiplier, IEEE J Solid State Circ 31(8):1123-1131
Yin L, Embabi SHK, S'anchez-Sinencio E (1997) A floating gate MOSFET D/A converter IEEE Proc ISCAS'97 1:409-412
Thomsen A and Brooke MA (Jan. 1993) A programmable piecewise linear large-signal CMOS amplifier, IEEE J Solid State Circ 28(1):84-89
Yu C-G and Geiger RL (1993) Very low voltage operational amplifier using floating gate MOSFETs, IEEE Proc ISCAS'93 2:1152-1155
Ramirez-Angulo J, Choi SC, Gonzalez-Altamirano G (Nov. 1995) Low-voltage circuits build- ing blocks using multiple-input floating-gate transistors. IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications 42(11):971-974
Yan S and Sanchez-Sinencio E (Feb. 2000) Low voltage analog circuit design techniques: a tutorial, IEICE Transactions on Analog Integrated Circuits and Systems E00-A (2): 1-17
Harrison RR, Charles C (Jun 2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid State Circ 38(6):958-965
Holleman J, Zhang F, Otis B (2011) Ultra low power circuit design for wireless neural interfaces. Springer, New York
Ahmadi MM, Jullien GA (July 2009) Current-mirror-based potentiostats for three-electrode amperometric electrochemical sensors. IEEE Trans Circ Syst 56(7):1339-1348
Hasan SMR (May 2007) Stability analysis and novel compensation of CMOS current-feedback potentiostat circuit for electrochemical sensors. IEEE Sensors Journal 7(5):814-824
Narula HS, Harris JG (April 2006) A time-based VLSI potentiostat for ion current measure- ments. IEEE Sensors Journal 6(2):239-247
Islam SK and Haider MR (2010) Sensors and low power signal processing. Springer, New York
Williams CB and R.B. Yates (June 1995) Analysis of a micro-electric generator for microsys- tems The 8th international conference on solid-state sensors and actuators. Stockholm, Sweden
Wu GH, Datar RH, Hansen KM, Thundat T, Cote RJ, Majumdar A (2001) Bioassay of prostate- specific antigen (PSA) using microcantilever Nat Biotechnol 19:856-60
Lu JH-L, Inerowicz M, Joo S, Kwon J-K, Jung B (2011) A low-power, wide-dynamic-range semi-digital universal sensor readout circuit using pulsewidth modulation. IEEE Sensors J doi: 10.1109/JSEN.2010.2085430
Stangel K, Kohnsberg S, Hammerschmidt D el al (2001) A programmable intraocular CMOS pressure sensor system implant. IEEE J Solid State Circ, soi:10.1109/4.933466
Chiang CT, Wang CS, Huang YC (2007) A CMOS integrated capacitance-to-frequency converter with digital compensation circuit designed for sensor interface applications. Proc IEEE Sensors, doi:10.1109/ICSENS.2007.4388561
Bruschi P, Navamini D. (2007) A current-mode, dual slope, integrated capacitance-to-pulse duration converter. IEEE J Solid State Circ, doi:10.1109/JSSC.2007.903102
Bruschi P, Navarrini D, Barillaro G et al (2004) A precise capacitance-to-pulse width converter for integrated sensors. Analog Integrated Circuits and Signal Processing, doi:10.1023/B: ALOG.0000038288.41566.0f
Toth FN, Meiyer GCM, Kerkvliet HMM (1995) Ultra-linear, low-cost measurement system for multi-electrode pF-range capacitors. Proc IMTC '95, doi:10.1109/IMTC.1995.515370
Goes FMLV, Meijer MGC (1996) A novel low-cost capacitive sensor interface. IEEE Trans Instrum Meas, doi:10.1109/19.492782
Krummenacher F (1985) A high-resolution capacitance-to-frequency converter. IEEE J Solid State Circ, doi:10.1109/JSSC.1985.1052366
Wolffenbuttel R, Regtien P (1987) Capacitance-to-phase angle conversion for the detection of extremely small capacities. IEEE Trans Instrum Meas, IM-36:868-872
Ignjatovic Z, Bocko MF (2005) An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter. IEEE Sensors J, doi:10.1109/JSEN.2004. 841453
De Marcellis A, Depari A, Ferri G et al (2008) A CMOS integrable oscillator-based front end for high-dynamic-range resistive sensors. IEEE Trans Instrum Meas, doi:10.1109/TIM.2008. 922075
Grassi M, Malcovati P, Baschirotto A (2007) A 141-dB dynamic range CMOS gas-sensor interface circuit without calibration with 16-bit digital output word. IEEE J Solid State Circ, doi:10.1109/JSSC.2007.899087
Razavi B (2001) Design of analog CMOS integrated circuits, 1st edn. McGraw-Hill, New York
Razavi B (2001) Design of integrated circuits for optical communications. McGraw-Hill, New York
Horak G, Bilas V, Vasi D (2008) Noise analysis of the pulse-width modulator for quasi-digital sensors. Proc IMTC '08, doi:10.1109/IMTC.2008.4547124
Mason A, Chavan AV, Wise KD (2007) A mixed-voltage sensor readout circuit with on-chip calibration and built-in self-test. IEEE Sensors J, doi:10.1109/JSEN.2007.897957
Heidary A, Meijer GCM (2008) Features and design constraints for an optimized SC front-end circuit for capacitive sensors with a wide dynamic range. IEEE J Solid State Circ, doi:10.1109/ JSSC.2008.922390
2008) Data Sheet, Universal Transducer Interface UTI. Smartec, http://www.smartec-sensors. com/en/products/uti-interface-en.html
Katuri KC, Asrani S, Ramasubramanian MK (2008) Intraocular pressure monitoring sensors. IEEE Sensors J, doi:10.1109/JSEN.2007.912539
Mason A, Yazdi N, Chavan AV et al (1998) A generic multielement microsystem for portable wireless applications. IEEE Proceedings, doi:10.1109/5.704279
Lemmerhirt DF, Wise KD (2006) Chip-scale integration of data-gathering microsystems. IEEE Proceedings, doi:10.1109/JPROC.2006.873619
Gielen G, Rutenbar R (2000) Computer-aided design of analog and mixed-signal integrated circuits. Proc IEEE 88(12):1825-1854
Hasan M, Shen H-H, Allee D, Pennell M (2000) A behavioral model of a 1.8-v flash a/d converter based on device parameters. IEEE Trans Comput Aided Des Integrated Circ Syst 19(1):69 -82
Malcovati P, Brigati S, Francesconi F, Maloberti F, Cusinato P, Baschirotto A (2003) Behavioral modeling of switched-capacitor sigma-delta modulators. IEEE Trans Circ Syst Fund Theor Appl 50(3):352-364
Chen K, Zhang W, Yu Z (2009) Behavioral model of wide band sigma-delta modulators for wlan application. In: New Trends in Information and Service Science, 2009. NISS '09. International Conference on, 30 2009-July 2 2009, pp 597-602
Brambilla A, Premoli A (2001) Rigorous event-driven (red) analysis of large-scale nonlinear rc circuits. IEEE Trans Circ Syst Fund Theor Appl 48(8):938-946
Yun G, Ning P, Zaiwang D (2009) Mixed-signal modeling and analysis for a digital rf direct sampling mixer. In: 2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC, 2009, pp 623-627
Leblebici YS, Kang S (1993) Illiads: a fast timing and reliability simulator for digital mos circuits. IEEE Trans Comput Aided Des 12:1387-1402
Resve A, Brian A, Antao A, Singh J (1996) Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans Comput Aided Des Integrated Circ Syst 15(1):68-82
Okumura M, Sugawara T, Tanimoto H (1990) An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations. IEEE Trans Comput Aided Des Integrated Circ Syst 9:225-235
Telichevesky R, Kundert K, White J (1996) Efficient ac and noise analysis of two-tone rf circuits. In: DAC, 1996, pp 292-297
Brambilla A, Gruosso G, Redaelli MA, Storti-Gajani G, Caviglia D (2010) Improved small sig- nal analysis for circuits working in periodic steady state. IEEE Trans Circ Syst I 57(2):427-437
Kim J, Jones KD, Horowitz M (2007) Variable domain transformation for linear pac analysis of mixed-signal systems. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2007, pp 887-894
Hiskens I, Pai M (2000) Trajectory sensitivity analysis of hybrid systems. IEEE Trans Circ Syst Fund Theor Appl 47(2):204-220
Giaouris D, Banerjee S, Zahawi B, Pickert V (2007) Control of fast scale bifurcations in power- factor correction converters. IEEE Trans Circ Syst Express Briefs 54(9):805-809
Giaouris D, Banerjee S, Zahawi B, Pickert V (2008) Stability analysis of the continuous- conduction-mode buck converter via filippov's method. IEEE Trans Circ Syst Regular Papers 55(4):1084-1096
Di Bernardo M, Budd C, Champneys A, Kowalczyk P (2008) Piecewise-smooth dynamical systems, theory and applications. Springer, London
Bizzarri F, Brambilla A, Gajani G.S. Steady state computation and noise analysis of analog mixed signal circuits. IEEE Trans Circ Syst I: Fundam Theory
Okumura M, Tanimoto H (1997) A time-domain method for numerical noise analysis of oscillators. In: Design automation conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, January 28-31 1997, pp 477-482
Okumura M, Tanimoto H, Itakura T, Sugawara T (1993) Numerical noise analysis for nonlinear circuits with a periodic large signal excitation including cyclostationary noise sources. IEEE Trans Circ Syst Fund Theor Appl [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] 40(9):581-590
Brambilla A, Gruosso G, Redaelli AM, Storti Gajani G (2010) Periodic noise analysis of elec- tric circuits: artifacts, singularities and a numerical method. J Circ Theor Appl 38(7):689-708
Aprille T, Trick T (1972) Steady-state analysis of nonlinear circuits with periodic inputs. Proc IEEE 60:108-114
Brambilla A, Gruosso G, Storti Gajani G (2010) Fssa: fast steady-state algorithm for the analysis of mixed analog/digital circuits. IEEE Trans CAD 29(4):528-537
Farkas M (1994) Periodic motions. Springer, New York
Bizzarri F, Brambilla A, Gajani G (2011) Phase noise simulation in analog mixed signal circuits: an application to pulse energy oscillators. IEEE Trans Circ Syst Express Briefs 58(3):154-158
International Technology Roadmap for Semiconductors, http://public.itrs.net
Chan HHY, ZZilic Z Modeling layout effects for sensitivity-based analog circuit optimization. In: Proceedings of ISQED'2005, pp 390-395
Kuo C.-C, Lee M.-J, Liu C.-N, Huang C.-J (2009) Fast statistical analysis of process variation effects using accurate pll behavioral models. IEEE Trans Circ Syst-I, Regulas papers 56(6):1160-1172
Sapatnekar SS (2011) Ovecoming variations in nanometer-scale technlogies. IEEE Transac- tions on Emerging and Selected Topics in Cicuits an Systems 1(1):5-18
Elie Maricau, Georges Gielen (2011) Computer-aided analog circuit design for reliability in nanometer CMOS. IEEE Transactions on Emerging and Selected Topics in Cicuits an Systems 1(1):50-58
Shah D, Siva K, Girishankar G, Nagaaj NS (2006) Optimizing interconnect for performance in standard cell library. In: Proceedings of IEEE Asian Pacific Conference on Circuits and Systems. doi: 10.1109/APCCAS.2006.342397
Bi Y, Siva K, Schilders WHA (2007) Effects of manufacturing variability on integrated passive components. In: Proceedings of IEEE ProRISC workshop on Circuits, Systems and Signal Processing, Veldhoven (NL) Nov 2007 ISBN 978-90-73461-49-9
Bi Y, Siva K, Schilders WHA (2008) Process variation aware modeling of interconnect capacitance. In: Proceedings of IEEE ProRISC workshop on Circuits, Systems and Signal Processing, Veldhoven STW, Veldhoven (NL) Nov 2008
Nieuwoudt A, Massoud Y (2006) Variability-aware multilevel integrated spiral inductor synthesis. IEEE Trans Comput Aided Des Integrated Circ Syst 25(12):2613-2625
Schmedt BD, Gielen G (2003) WATSON: design space boundary exploration and model generation for analog and RFIC design. IEEE Trans Comput Aided Des Integrated Circ Syst 22(2):213-224
Mohan S, Hershenson M, Boyd S, Lee T (1999) Simple accurate expressions for planar spiral inductances. IEEE J Solid State Circ 34(10):1419-1424
Goudos SK, Sahalos JN (2006) Microwave absorber optimal design using multi-objective parti- cle swarm optimization Microw Optic Technol Lett 48(8):1553-1558 doi: 10.1002/mop.21727
Hu X, Eberhart R (2002) Multiobjective optimization using dynamic neighborhood particle swarm optimization. Proc 22 Congr Evol Comput 2:1677-1681 doi: 10.1109/CEC.22.14494
Coello CAC, Pulido GT, Lechuga MS (2004) Handling multiple objectives with particle swarm optimization. IEEE Trans Evolut Comput 8(3):256-279 doi: 10.1109/TEVC.24. 826067
Li X (2010) Niching without niching parameters: particle swarm optimization using a ring topology. IEEE Trans Evolut Comput 14(1):150-169
Allstot DJ, Choi K, Park J (2003) Parasitic-aware optimization of CMOS RF circuits. Kluwer Academic Publishers, ISBN 1-4020-7399-2
Park M, Kim CH, Kim CS, et al (1999) Frequency-dependent series resistance of monolithic spiral inductors. IEEE Microwave Guided Lett 9(12):514-516
Murphy Olive H (2005) Advanced physical modelling of multilayer inductors for CMOS RF front-end applications. PhD Thesis, University College Cork -National University of Ireland
Patrick Yue C, Simon Wong S (1999) Design strategy of on-chip inductors for highly integrated RF systems. Invited Paper in Proceedings of the 1999 Design Automation Conference 982-987
Marler RT, Arora JS (2004) Survey of multi-objective optimization methods for engineering. Struct Multidiscip Optim 26:369-395 doi: 10.17/s158-3-0368-6
Daneshyari M, Yen GG (2011) Cultural-based multiobjective particle swarm optimization. IEEE Trans Syst Man Cybern 41(2):553-567 doi: 10.1109/TSMCB.2010.2068046
Li X (2004) Better spread and convergence: particle swarm multiobjective optimization using the maximin fitness function. In: Deb K et al. (eds) Genetic and evolutionary computation - GECCO 24, LNCS, Springer, Berlin/Heidelberg. doi: 10.17/978-3-540-24854-5 11
Kennedy J, Eberhart R (1995) Particle swarm optimization. Proc IEEE Int ConfNeural Netw 4:1942-1948 doi: 10.1109/ICNN.1995.488968
Kennedy J, Eberhart RC, Shi Y (2001) Swarm intelligence. Morgan Kaufmann, San Fran- cisco, CA
Evers GI, Ben Ghalia M (2009) Regrouping particle swarm optimization: a new global optimization algorithm with improved performance consistency across benchmarks. Proc IEEE Int Conf Syst Man Cybern 3901-3908 doi: 10.1109/ICSMC.2009.5346625
Abido M (2010) Multiobjective particle swarm optimization with nondominated local and global sets. Natural Computing 9:747-766 doi: 10.17/s11047-9-9171-7
Lechuga SM, Rowe JE (2002) Particle swarm optimization and fitness sharing to solve multi- objective optimization problems. Proceedings of 25 IEEE Congr Evol Comput 2:1204-1211 doi: 10.1109/CEC.25.1554827
Pires ES, Oliveira PM, Machado JT (2005) Multi-objective MaxiMin sorting scheme. In: Coello CC, Aguirre AH, Eckart Z (eds) Evolutionary multi-criterion optimization, LNCS, Springer, Berlin/Heidelberg doi: 10.17/978-3-540-31880-4 12
R. Vargas-Bernal ( )
Departamento de Ingeniería en Materiales, Instituto Tecnológico Superior de Irapuato, Carretera Irapuato-Silao Km. 12.5, Irapuato, Guanajuato, C.P. 36821, Mexico e-mail: [email protected] C.A. De La Cruz Blas Departamento de Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra, Campus Arrosadía, Pamplona, Navarra, España, C.P. 31006, Spain e-mail: [email protected] E. Tlelo-Cuautle (ed.), Integrated Circuits for Analog Signal Processing, DOI 10.1007/978-1-4614-1383-7 13, © Springer Science+Business Media New York 2013 289 Although the companding technique permits the design of filters featuring small distortion levels, large signal-to-noise ratios, low supply voltages, and wide bandwidths, it may also give rise to externally-nonlinear behavior. The occurrence of unwanted limit-cycle behavior in log-domain filters is reported in [107] and investigated in [67]. The appearance of multiple operating points in such filters is discussed in [105]. So far, these nonlinear phenomena have been reported only in log-domain filters and more recently in instantaneously digital companding [55,78].
But the square root-domain filters may also suffer from external nonlinearity. In
a fully-differential class-AB second-order SRD filter is designed, and then modified according to a standard linear IC design technique, i.e. any pair of equal- value capacitors, each connected between a node and ground, is replaced with a single half-sized floating capacitor, placed between those nodes. This saves IC area, but may induce zero-input limit cycle behavior under particular conditions describe in [104].
13.5 Applications This section is devoted to describe the applications that can be implemented by TL principle, but are not described in the previous sections: square-root circuits [1, 2, 14, 18, 21-23, 26, 27, 29, 33, 40, 49, 69, 73], squarer/divider circuits [1, 3, 17, 21, 22, 25, 33, 36, 39, 40, 57, 64, 72, 103], multiplier/divider circuits [1, 7, 19, 25, 26, 33, 36, 39, 57, 59, 72, 73], squaring circuits [2, 14, 16, 28, 29, 36, 69], geometric mean circuits [2, 3, 6, 7, 14, 17, 21, 22, 25, 26, 29, 36, 39, 40, 60, 70, 72, 73, 79, 83, 99], differentiators [6-8, 14, 20], integrators [4, 6, 15, 26, 31, 34, 45, 48, 51, 67, 70, 73, 83, 84, 86, 88, 90, 94, 96-98], filters low pass, high pass, band pass, all pass, notch, low pass notch, high pass notch, sinh, tanh, log-domain, square-root, wave, anti-aliasing, and adaptive filters) [4, 6-8, 14, 16, 18-25, 27, 28, 31, 32, 34, 35, 37, 38, 40, 43- 45,48-52,55,56,64,65,67,69-76,78,81-83,85-90,92,94-98,103,104], oscillators [11,14,16,22,27,29,43,46,47,80,91], multipliers [4,9,14,16,20,42,58,73], RMS- DC converters [2,3,16,17,69], modulators [33], harmonic mixers [10], phase shifters [41], sine/cosine synthesizers [13, 43, 63], fuzzy logic controllers [61, 77], artificial neural networks [61, 93], cryptography systems [5], chaotic analog noise generators [5,11,46,47,67,91], programmable gain current amplifiers [12,59,62,68,77,89,101], current conveyors [13], ΣΔ A/D converters [30, 77], frequency multipliers [41, 60, 63], exponential function converters [42,54], group-delay equalizers [44,48], divider circuits [53, 69, 83, 89], sensors [53, 66], RMS detectors [64], 2-D vector-magnitude circuits [69], 2-D vector-normalization circuits [69], defuzzifiers [77], one-quadrant multiply-reciprocal circuits [79], etc. Some of these cells are used as building blocks of the above applications. FGMOS retain a long time the injected charge in the gate and then weighted volt- age addition at the input terminals is a direct consequence. Such qualities provide attractive characteristics as accuracy, high-speed, and compactness. MITEs have specific applications [3,6,19,69,71,75,77,79,88] such as weighted average circuits References
Menekay S et al (2009) Novel high-precision current-mode circuits based on the mos- translinear principle. AEU-Int J Electron Commun 63(11):992-997
Kaewdang K et al (2009) A translinear-based true RMS-to-DC converter using only NPN BJTs. AEU-Int J Electron Commun 63(4):472-477
Farshidi E et al (2008) A 1.2 V current-mode true RMS-DC converter based on the floating gate MOS translinear principle. Microelectron J 39(2):293-298
Tola AT et al (2008) Current mode high-frequency KHN filter employing differential class ab log domain integrator. AEU-Int J Electron Commun 63(7):600-608
Díaz-Méndez A et al (2009) Chaotic noise MOS generator based on logistic map. Microelec- tron J 40(3):638-640
Farshidi E (2010) Synthesis of class-AB log-domain filters based on nonlinear transconduc- tance. Microelectron J 41(5):266-276
Ip HMD et al (2009) A 19 nW analogue CMOS log-domain 6th-order bessel filter without E-minus cells. Microelectron J, 40(8):1170-1174
Kircay A et al (2006) Novel first-order differential Class-AB log-domain allpass filters. AEU- Int J Electron Commun 60(10):705-712
Shepherd L et al (2005) Weak inversion ISFETs for ultra-low power biochemical sensing and real-time analysis. Sens Actuators B Chem 107(1):468-473
Wu Y et al (2002) A SiGe HBT translinear harmonic mixer. Analog Integ Circuits Signal Process 31(1):65-67
Odame K et al (2009) Implementing the Lorenz oscillator with translinear elements. Analog Integr Circuits Signal Process 59(1):31-41
Tadić N et al (2011) A BJT translinear loop based optoelectronic integrated circuit with variable transimpedance for optical storage systems. Analog Integr Circuits Signal Process 66(2):293-298
Kumngern M et al (2010) Electronically tunable multiphase sinusoidal oscillator using translinear current conveyors. Analog Integr Circuits Signal Process 65(2):327-334
Loizos DN et al (2008) A translinear sige bicmos current-controlled oscillator with 80 Hz-800 MHz tuning range. Analog Integr Circuits Signal Process 57(1-2):107-115
Vlassis S et al (2004) A square-root domain differentiator circuit. Analog Integr Circuits Signal Process 40(1):53-59
López-Martín AJ et al (2004) Very low voltage mos translinear loops based on flipped voltage followers. Analog Integr Circuits Signal Process 40(1):71-74
López-Martín AJ Carlosena A (2003) A 1.5 V current-mode CMOS RMS-to-DC converter. Analog Integr Circuits Signal Process 36(1-2):137-143
Yu G-J et al (2005) Design of current-mode square-root domain band-pass filter with reduced voltage. Analog Integr Circuits Signal Process 44(3):239-250
López-Martín AJ et al (2004) A 1 V micropower FGMOS Class AB log-domain filter. Analog Integr Circuits Signal Process 41(2-3):137-145
Vlassis S et al (2002) A novel log-domain differentiator. Analog Integr Circuits Signal Process 32(3):285-287
Eskiyerli M et al (2000) "Square root domain" filter design and performance. Analog Integr Circuits Signal Process 22(2-3):231-243
López-Martín AJ et al (2001) Systematic design of companding systems by component substitution. Analog Integr Circuits Signal Process 28(1):91-106
Yu G-J et al (2005) Design of square-root domain filters. Analog Integr Circuits Signal Process 43(1):49-59
Kircay A et al (2009) A new 5th-order differential type Class-AB log-domain elliptic lowpass filter for video frequency applications. Analog Integr Circuits Signal Process 60(3):221-229
De la Cruz-Blas CA et al (2004) Low-voltage CMOS nonlinear transconductors and their application to companding current-mode filters. Analog Integr Circuits Signal Process 38(2-3):137-147
Psychalinos C et al (2002) A high performance square-root domain integrator. Analog Integr Circuits Signal Process 32(1):97-101
Özoguz S et al (2006) Novel approximate square-root domain all-pass filter with application to multiphase oscillators. Analog Integr Circuits Signal Process 46(3):297-301
Grech I et al (2003) Low-power log-domain CMOS filter bank for 2-D sound source localization. Analog Integr Circuits Signal Process 36(1-2):99-117
Mohammed KO et al (2005) A tunable square root domain oscillator. Analog Integr Circuits Signal Process 43(1):91-95
Serra-Graells F (2003) 1 V all-MOS Σ A/D converters in the log-domain. Analog Integr Circuits Signal Process 35(1):47-57
Shah NA et al (2009) Log-domain synthesis of nth order universal filter. Analog Integr Circuits Signal Process 59(3):309-315
Mulder J et al (2000) Dynamic translinear circuits-An overview. Analog Integr Circuits Signal Process 22(2-3):111-126
Menekay S et al (2009) Novel high-precision current-mode multipler/divider. Analog Integr Circuits Signal Process 60(3):237-248
Leung VW et al (2000) Analysis and compensation of log-domain biquadratic filter re- sponse deviations due to transistor nonidealities. Analog Integr Circuits Signal Process 22(2-3):147-162
Edwards RT et al (2000) Synthesis of log-domain filters from first-order building blocks. Analog Integr Circuits Signal Process 22(2-3):177-186
López-Martín AJ et al (2001) Current-mode multiplier/divider circuits based on the MOS translinear principle. Analog Integr Circuits Signal Process 28(3):265-278
Masmoudi D et al (2000) A new current-mode synthesis method for dynamic translinear filters and its applications in hearing instruments. Analog Integr Circuits Signal Process 22(2-3):221-229
Shoemaker P (2005) A methodology for long time constant log-domain filters in CMOS. Analog Integr Circuits Signal Process 42(2):161-178
Lopez-Martin AJ et al (2011) Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions. Analog Integr Circuits Signal Process 66(2):299-302
López-Martín AJ, Carlosena A (2002) 1.
V CMOS companding filter. Electron Lett 38(22):1346-1348
Lin TY et al (2002) Translinear sinusoidal frequency tripler. Electron Lett 38(10):441-442
Kao C-H et al (2005) Low-voltage low-power current mode exponential circuit. IEE Proc Circuits Devices Syst 152(6):633-635
Prommee P et al (2010) High-frequency log-domain current-mode multiphase sinusoidal oscillator. IET Circ Device Syst 4(5):440-448
Teplechuk MA et al (2007) Wave realisation of filters and equalisers in log-domain. IET Circuit Devices Syst 1(6):433-443
Ng AEJ et al (2004) Unified matrix method for systematic synthesis of log-domain ladder filters. IEE Proc Circuits Devices Syst 151(4):285-293
Özoguz S (2001) Simple log-domain chaotic oscillator. Electron Lett 37(23):1378-1379
Mahon A et al (2001) Nonlinear dynamics of log-domain circuit. Electron Lett 37(15):929-930
Cuypers C et al (2005) General synthesis of complex analogue filters. IEE Proc Circuits Devices Syst 152(1):7-15
De La Cruz-Blas CA et al (2004) 1.5 V tunable square-root domain filter. Electron Lett 40(4):213-214
Fragoulis N (2010) Universal log-domain biquad. Electron Lett 46(7):487-488
Frey DR et al (2009) Unifying perspective on log-domain filter synthesis. Electron Lett 45(17):861-863
Georgiou P et al (2009) Chemical log-domain filter. Electron Lett 45(8):391-392
Juffali W et al (2010) ISFET based urea creatinine translinear sensor. Electron Lett 46(11):746-748
Kao CH et al (2005) Low-voltage exponential function converter. IEE Proc Circuits Devices Syst 152(5):485-487
Krishnapura N et al (2000) Simplified technique for syllabic companding in log-domain filters. Electron Lett 36(15):1257-1259
Teplechuk MA et al (2006) Approximation of arbitrary complex filter responses and their realisation in log domain. IEE Proc Circuits Devices Syst, 153(6):583-590
De La Cruz-Blas CA et al (2003) 1.5 V four-quadrant CMOS current multiplier/divider. Electron Lett 39(5):434-436
Miguel JMA et al (2011) Fully differential current-mode CMOS triode translinear multiplier. IEEE Trans Circuits Syst II Express Briefs 58(1):21-25
Fernández D et al (2008) A MOSFET-based Wide-dynamic-range translinear element. IEEE Trans Circuits Syst II Express Briefs 55(11):1124-1128
Ilsen D et al (2008) Algebraic and combinatorial algorithms for translinear network synthesis. IEEE Trans Circuits Syst I Regul Pap 55(10):3131-3144
Leñero-Bardallo JA et al (2008) A calibration technique for very low current and compact tunable neuromorphic cells: application to 5-bit 20-nA DACs. IEEE Trans Circuits Syst II Express Briefs 55(6):522-526
De la Cruz-Blas CA et al (2007) A ±0.75-V compact CMOS Class-AB current-mode expo- nential variable gain amplifier. IEEE Trans Circuits Syst II Express Briefs 54(12):1042-1046
Abuelma'atti MT (2005) A translinear circuit for sinusoidal frequency division. IEEE Trans Instrum Meas 54(1):10-14
Yin Q et al (2005) A translinear rms detector for embedded test of RF ICs. IEEE Trans Instrum Meas 54(5):1708-1714
Serra-Graells F et al (2005) Low-voltage cmos subthreshold log-domain filtering. IEEE Trans Circuits Syst I Regul Pap 52(10):2090-2100
Shepherd LM et al (2005) A biochemical translinear principle with weak inversion ISFETs. IEEE Trans Circuits Syst I Regul Pap 52(12):2614-2619
Ascoli A et al (2005) Nonlinear dynamics of first-and second-order log-domain circuits. IIEEE Trans Circuits Syst I Regul Pap 52(7):1372-1381
Senani R et al (2004) A new floating current-controlled positive resistance using mixed translinear cells. IEEE Trans Circuits Syst II Express Briefs 51(7):374-377
Minch BA (2004) Synthesis of static and dynamic multiple-input translinear element networks. IEEE Trans Circuits Syst I Regul Pap 51(2):409-421
Fox RM et al (2004) Differential log-domain filters with high-gain common-mode feedback. IEEE Trans Circuits Syst I Regul Pap 51(2):254-263
Minch BA (2003) Construction and transformation of multiple-input translinear element networks. IEEE Trans Circuits Syst I Fundam Theory Appl 50(12):1530-1537
De la Cruz-Blas CA et al (2003) 1.5-V MOS translinear loops with improved dynamic range and their applications to current-mode signal processing. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50(12):918-927
Psychalinos C et al (2002) A systematic design procedure for square-root-domain circuits based on the signal flow graph approach. IEEE Trans Circuits Syst I Fundam Theory Appl 49(12):1702-1712
Psychalinos C et al (2002) On the exact realization of log-domain elliptic filters using the signal flow graph approach. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(12):770-774
Minch BA (2001) Multiple-input translinear element log-domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(1):29-36
Mulder J et al (2001) A generalized class of dynamic translinear circuits. IEEE Trans Circuits Systems II: Analog Digit Signal Process 48(5):501-504
Ramírez-Angulo J et al (2001) MITE circuits: the continuous-time counterpart to switched- capacitor circuits. IEEE Trans Circuits Systems II: Analog Digit Signal Process 48(1):45-55
Frey D et al (2001) Syllabic-companding log domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(4):329-339
Minch BA. et al (2001) Multiple-input translinear element networks. IEEE Trans Circuits Syst II: Analog Digit Signal Process 48(1):20-28
Chan WP et al (2010) An integrated isfets instrumentation system in standard CMOS technology. IEEE J Solid-State Circuits, 45(9):1923-1934
Kircay A et al (2008) Differential type Class-AB second-order log-domain notch filter. IEEE Trans Circuits Syst I Regul Pap 55(5):1203-1212
Psychalinos C (2008) Low-voltage log-domain complex filters. IEEE Trans Circuits Syst I Regul Pap 55(11):3404-3412
Katsiamis AG et al (2008) Insights and advances on the design of CMOS sinh companding filters. IEEE Trans Circuits Syst I Regul Pap 55(9):2539-2550
López-Martín AJ et al (2005) 1.2-V 5-μW Class-AB CMOS log-domain integrator with multidecade tuning. IEEE Trans Circuits Syst II Express Briefs 52(10):665-668
Kontogiannopoulos N et al (2005) Log-domain filtering by simulating the topology of passive prototypes. IEEE Trans Circuits Syst I Regul Pap 52(10):2043-2054
Psychalinos C et al (2004) Log-domain wave filters. IEEE Trans Circuits Syst II Express Briefs 51(6):299-306
Fragoulis N et al (2004) Modular log-domain filters realized using wave port terminators. IEEE Trans Circuits Syst I Regul Pap 51(11):2235-2244
Rodríguez-Villegas E et al (2004) A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion. IEEE J Solid-State Circuits 39(1):256-259
Serra-Graells F et al (2004) A true-1-V 300-μW CMOS-Subthreshold log-domain hearing- aid-on-chip. IEEE J Solid-State Circuits 39(8):1271-1281
Baki RA et al (2003) A low-power 5-70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications. IEEE J Solid- State Circuits 38(2):205-215
Özoguz S et al (2003) On the realization of NPN-only log-domain chaotic oscillators. IEEE Trans Circuits Syst I Fundam Theory Appl 50(2):291-294
Drakakis EM et al (2003) Operational DC constraints for a Class-A, third-order, ob- server canonical-form log-domain filter. IEEE Trans Circuits Syst I Fundam Theory Appl 50(10):1337-1342
Serrano-Gotarredona T et al (2003) Log-domain implementation of complex dynamics reaction-diffusion neural networks. IEEE Trans Neural Netw 14(5):1337-1355
Baki RA et al (2003) Distortion Analysis of high-frequency log-domain filters using volterra series. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50(1):1-11
Drakakis EM et al (2003) Spectral impact of the modulation index upon internal log-domain currents. IEEE Trans Circuits Syst I Fundam Theory Appl 50(10):1343-1347
Ng AEJ et al (2002) Direct noise analysis of log-domain filters. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(2):101-109
El-Gamal MN et al (2002) A 1.2-V N-P-N-only integrator for log-domain filtering. IEEE Trans Circuits Syst II: Analog Digit Signal Process 49(4):257-265
Python D et al (2001) A micropower Class-AB CMOS log-domain filter for DECT applications. IEEE J Solid-State Circuits 36(7):1067-1075
Minch BA (2008) MOS translinear principle for all inversion levels. IEEE Trans Circuits Syst II Express Briefs 55(2):121-125
Diepstraten FM et al (2001) Dynamic behavior of dynamic translinear circuits: the linear time- varying approximation. IEEE Trans Circuits Syst I Fundam Theory Appl 48(11):1333-1337
Seevinck E et al (2000) CMOS translinear circuits for minimum supply voltage. IEEE Trans Circuits Syst II: Analog Digit Signal Process 47(12):1560-1564
Minch BA et al (1996) Translinear circuits using subthreshold floating-gate MOS transistors. Analog Integr Circ Signal Process 9(2):167-179
De La Cruz-Blas CA et al (2005) 1.5-V square-root domain second-order filter with on-chip tuning. IEEE Trans Circuits Syst I Regul Pap 52(10):1996-2006
De La Cruz-Blas CA et al (2011) Limit cycle behavior in a Class-AB second-order square root domain filter. Analog Integr Circ Signal Process 68(8):175-181
Fox RM et al (1999) Multiple operating points in a cmos log-domain filter. IEEE Trans Circuits Syst II: Analog Digit Signal Process 46(6):705-710
Frey DR (1996) Exponential state space filters: a generic current mode design strategy. IEEE Trans Circuits Syst I Fundam Theory Appl 43(1):34-42
Ferrer E et al (1999) Limit-cycle oscillations in a log-domain based filter. IEEE Trans Circuits Syst II: Analog Digit Signal Process 46(6):832-836
Vargas-Bernal R et al (2000) Identifying translinear loops in the circuit topology. In: Proceedings of the IEEE ISCAS, vol 2. Geneva, pp. 585-588
Vargas-Bernal R (2002) Prediction of multiple dc operating points in a CMOS log-domain filter. In: Proceedings of the IEEE Latin-American CAS Tour. Puebla, pp. 70-73

About the author

daf dafd

Papers

Followers

314

View all papers from daf dafdarrow_forward

Integrated circuits for analog signal process

Sign up for access to the world's latest research

AbstractAI

Related papers

References (500)

Related papers

Related topics

Abstract
AI