Translinear Signal Processing Circuits in Standard CMOS FPAA

Translinear Signal Processing Circuits in Standard CMOS FPAA Luis Martínez-Alvarado, Jordi Madrenas and Daniel Fernández. Electronic Engineering Department. Universitat Politécnica de Catalunya Jordi Girona 1-3, 08034 Barcelona, Spain. Email: [email protected] Abstract—In this paper, the implementation of signal process- ing circuits on a novel translinear Field-Programmable Analog CAL_C Array (FPAA) testchip is reported. The FPAA testchip is based in_north in_west SM TE on a 0.35-micron, fully CMOS translinear element, which is the C_BUS out COL core block of a reconfigurable analog cell. The FPAA embeds a DIODE CTL REG in PCS PCM CTL out 5 × 5 cell array. As implementation examples, a four-quadrant in_north 7 C in_west B SM G_BUS TE out TE multiplier with five decade dynamic range and a programmable GATE IB1 CAL_B TE CTL EN E IB2 fourth-order low-pass filter with up to 7 M Hz bandwidth have PCS CTL in_north out EP in_west M EP been mapped on the translinear FPAA. 14 cells have been used SM E_BUS TE 6−bit 6 out EMI CAL_C for the four-quadrant multiplier while 18 cells were needed for /EP CTL 8 the fourth-order low-pass filter. 8 8 calib out CTL CAL PCS PCAP Index Terms—Mixed-signal, Field Programmable Analog Ar- 7 CTL EN 7−bit MODE PCAP 7 8 ray, Translinear Cell, Log-domain Filter, Four-Quadrant Multi- TE REG REG REG REG REG plier COL GATE EMI PCS CAL data bus 8 I. I NTRODUCTION Whenever the design constraints can be fulfilled, Field- Figure 1. Block diagram of the Reconfigurable Translinear Cell Programmable Analog Arrays (FPAA) highly attractive for (RTC) [2] prototyping and low volume products as a fast and cost- effective alternative to mixed-signal full-custom design. ket [13]. This kind of devices already was reported in the FPAAs basically consist of an array of configurable analog late 90’s [14]. blocks and they can be classified in several types depending on their operation mode, being either continuous-time or discrete- In analog VLSI, the translinear approach [15] provides time and either voltage-mode or current-mode. Continuous- compact and fast implementation of such basic blocks, being time devices can be implemented by means of translinear very suitable when using bipolar transistor; however, the MOS elements [1, 2], transconductors [3], current integrators [4] transistor exhibits an exponential characteristic only in weak or current conveyors [5], while discrete-time implementations inversion, which severely limits speed. may use switched capacitor topologies [6, 7] or switched In order to enhance the frequency limitations of translinear current circuits. The FPAAs can be configured for applications circuits in standard CMOS technology, a new translinear cell such as filtering [8], neural networks [9], industrial con- as a reconfigurable analog block in a FPAA was proposed trol [10], signal processing [11], V-F converters and aerospace in [2, 16]. Some of the most common basic operations in communications [12], among others. FPAA are filtering and non-linear functions, e.g., products and Since the 1990’s, FPAAs have received the designers atten- divisions. tion because this type of devices provides flexibility in analog This paper aims to the application of an FPAA as a circuit system design, similar to FPGA (Field-Programmable reconfigurable signal processing element. The reconfigurable Gate Arrays) in the digital domain. However, because of translinear cell architecture is described in section II. Section scalability issues and the more reduced modularity of analog III shows the mapping of a four-quadrant multiplier and a blocks compared to digital counterparts, the development of fourth order low-pass filter in the FPAA. Finally the simulation reconfigurable analog hardware has been progressing very results for the multiplier and filter are presented in section IV. slowly. Current FPAAs have struggled to establish a solid II. R ECONFIGURABLE T RANSLINEAR C ELL market base, but they have been plagued by poor performance A RCHITECTURE and a lack of general functionality. Therefore, the FPAAs have not been as well accepted as FPGAs have. Recently, mixed- Fig. 1 shows the proposed RTC block diagram. The signal devices that integrate a microcontroller and some analog translinear cell contains the translinear element (TE) [16], and digital components that typically surround it constitute a Programmable Current Mirror (PCM) block, 6 and 7-bit an embedded system called PSoC (Programmable System- Programmable Current Sources (PCS 6-bit) and (PCS 7- on-Chip), and have been successfully introduced in the mar- bit) blocks, a Programmable CAPacitor (PCAP) block, three 978-1-4244-5091-6/09/$25.00 ©2009 IEEE 715  Iu Iz1+ Iz1- Ix- Iu Ix+ Iz2+ Iz2- Ix- Iy+ Ix+ Iy- C C C C C C C C C C C C B B B B B B B B B B B B IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB1 IB2 IB2 IB2 IB2 IB2 IB2 IB2 IB2 IB2 IB2 IB2 IB2 E E E E E E E E E E E E Vref Vref Vref Figure 2. Four-quadrant multiplier schematic − Io Io+ Switch Matrices (SM), a configuration memory (REG), con- figuration switches and an additional MOS transistor. Iy+ Iz 1+ C C The main block is the TE, based on a wide dynamic B ranges fully CMOS-compatible circuit presented in [16, 17]. TE1 TE4 B The programmable current mirror can be configured to scale E E input currents by 3, 2, 1, 1/2 and 1/3 times. The range of RTC[0][0] Vref RTC[0][1] RTC[0][2] RTC[0][3] RTC[0][4] input and output currents of the mirror must be close to the Iu Ix − Ix + dynamic range of the translinear element. The 6 and 7-bit pro- C C − C Iz 1 C grammable current sources provide the two biasing currents to B B B the translinear element, in fact the 7-bit current source can be TE2 TE6 TE5 TE3 B configured as a general bias source with three different ranges, E E E E PCS1 from 0 to 10 nA, 1 µA and 100 µA. The programmable Vref capacitor is needed for log-domain filters applications. This RTC[1][1] RTC[1][3] RTC[1][4] RTC[1][0] RTC[1[2] capacitor can be tunable in a range of 1.25 − 2.5 pF . Despite Iy − this programmability is limited, cutoff frequency is usually C C Iz 2 + set by means of transconductance in translinear circuits (see B B TE10 eq. 2). The switch matrices provide interconnection among TE7 cells and the configuration switches configure the translinear E E Vref cell, both by means of configuration memories. The MOS RTC[2][0] RTC[2][1] RTC[2][2] RTC[2][3] RTC[2][4] transistor in Fig 1 is an alternative to provide an emitter- Iu Ix − Ix+ follower connection forcing the collector current, using the C C C Iz 2− C Enz-Punzenberger (EP) configuration [18]. B TE8 TE12 B B TE9 TE11 B The RTC has 7 different forms to be configured: 1) as pure E E E E TE, 2) TE with EP connection, 3) as bias current source cell, 4) Vref PCS2 as bias current source with a programmable capacitor, 5) as a current mirror cell, 6) as current mirror with a programmable RTC[3][0] RTC[3][1] RTC[3][2] RTC[3][3] RTC[3][4] capacitor and finally 7) as pure programmable capacitor cell. The developed FPAA testchip contains a 5 × 5 RTC array, Figure 3. Four-quadrant multiplier mapping details on this testchip and layout can be found in [2]. These cells can be connected and configured as desired to form a specific circuit. For the interconnects, four rails in each row Where Ix+ , Ix− , Iy+ and Iy− are the differential inputs, Iu is + − + − and column are provided, and every RTC is connected to the a bias current source, Io+ = Iz1 + Iz2 and Io− = Iz2 + Iz1 are rail of corresponding row and column via switch matrices. the differential outputs. The translinear elements from T E1 to T E6 show the classic topology of a two-quadrant multiplier, III. A PPLICATION E XAMPLES M APPING and the working principle can be found on [19]. To sketch In Fig. 2 a four-quadrant multiplier schematic is depicted. the four-quadrant multiplier, two topologies of two-quadrant Applying the translinear principle [19], where in a closed loop multiplier were cascaded. the product of clockwise currents is equal to the product of Fig. 3 depicts the mapping of the four-quadrant multiplier in counterclockwise current, we obtain: a 4 × 5 slice of the FPAA. To implement this circuit 14 cells were needed, 10 of them configured as translinear elements, 2 (Ix+ − Ix− ) (Iy + − Iy − ) cells with EP connection and 2 more cells operating as bias Io+ − Io− = (1) current sources (Iu ). The dotted lines show the interconnectiv- Iu 716  Iin Ib Ib Iout C C C C C C Vref B B B B B B Vref TE1 TE2 TE3 TE2n E E C1 E ... E TE2n+1 E Cn E TE2n+2 Input Stage 1st Stage nth stage Output Stage Figure 4. nth-order low-pass filter schematic ity among RTCs by means of switch matrices. The RTCs must be distributed in such a way that inherent circuit symmetry is preserved. Special care should be taken with the switch placement, otherwise an asymmetrical RTC mapping causes different voltage drop on the rails, due to the number of serial Figure 5. Four-quadrant translinear multiplier DC response at connected switches, producing mismatch among RTCs. different tuning currents Ix = Ix+ − Ix− : −10 µA, −6 µA, −2 µA, Following the same procedure, a fourth-order low-pass filter 2 µA, 6 µA and 10 µA was mapped, where 18 cells were used to configure the FPAA, 5 of them as translinear elements, 5 cells with EP connection, 4 cells operating as bias current sources (Ib ) and 4 more cells operating as bias current sources (Ib ) with programmable capacitor (Ci ). Fig. 4 shows the general nth- order low-pass filter schematic. The input stage is a translinear element with EP connection, the next stages define the filter order, each i-stage provides a pole by means of capacitor Ci that is placed between T E2i and T E2i+1 to ground. The output stage is a simple translinear element. The pole frequency of each filter stage is given by, gm2i fci = (2) 2πCi Where gm2i is the transconductance of the translinear ele- ment 2i and Ci is the capacitance that provides the dominant pole at each stage i. With these two parameters the translinear filter can be tuned to a specific cut-off frequency. Figure 6. Four-quadrant translinear multiplier log-scale DC response simulation at different tuning currents Ix = Ix+ − Ix− : 10 µA, 1 µA, IV. A PPLICATION E XAMPLES R ESULTS 100 nA, 10 nA, 1 nA This section presents simulation results for the four-quadrant multiplier and the fourth-order low-pass filter at transistor level, taking into account the parasitics effects. Simulation results were obtained with Spectre and the programming of the RTC registers was optimized by means of a functional description in Verilog of these digital elements and mixed- signal simulation to achieve short simulation times. A. Four-Quadrant Multiplier In Fig. 5 the DC characteristic of the four-quadrant translin- ear multiplier at different tuning currents is depicted. The para- metric analysis shows the different curves with a differential input Ix = Ix+ − Ix− : −10 µA, −6 µA, −2 µA, 2 µA, 6 µA and 10 µA. Fig. 6 shows the log-scale linearity in five decades with a differential input Ix = Ix+ −Ix− : 10 µA, 1 µA, 100 nA, 10 nA and 1 nA. Fig. 7 shows the multiplier transient response using a con- stant of 5 µA bias added to a 1 M Hz sine wave of 2.5 µApp Figure 7. Transient response of the four-quadrant translinear multi- plier with opposite phase in each input Ix+ and Ix− . Input Iy+ is 717  ACKNOWLEDGMENT This work has been partially funded by the Spanish Ministry of Science and Innovation project TEC2008-06028/TEC. Luis Martinez-Alvarado holds research fellowships supported by the Catalan Department of Universities, Research and Infor- mation Society (DURSI) and the European Social Fund (ESF). R EFERENCES [1] D. Abramson, J. Gray, S. Subramanian, and P. Hasler, “A field- programmable analog array using translinear elements,” System-on- Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on, pp. 425–428, July 2005. [2] D. Fernandez, J. Madrenas, P. Michalik, and D. Kapusta, “A reconfig- urable translinear cell architecture for CMOS field-programmable analog arrays,” Electronics, Circuits and Systems, 2008. ICECS 2008. 15th Figure 8. Fourth-order low-pass filter. Frequency Response at differ- IEEE International Conference on, pp. 1034–1037, 31 2008-Sept. 3 ent tuning currents. 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