A Translinear, Log-Domain FPAA on Standard CMOS Technology

490 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 A Translinear, Log-Domain FPAA on Standard CMOS Technology Daniel Fernández, Luís Martínez-Alvarado, and Jordi Madrenas, Member, IEEE Abstract—A field-programmable analog array (FPAA) using a of primitives necessary to implement any system (amplifiers, standard-CMOS wide-dynamic-range translinear element (TE) multipliers, filters, sample & hold, etc.), the strong influence of is introduced. The FPAA configurable analog blocks (CABs) input and output impedance in the design, which makes mod- are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear ularity much more complex than in digital circuits, and, since and log-domain circuit design. The interfacing is provided by in analog design the signal does not regenerate, for each addi- an I/O programmable cell, which allows for easier connectivity tional processing block, some degree of distortion and/or noise between the signal-processing core and the external circuitry. As is introduced in the signal. Due to those reasons, it is not sur- a proof-of-concept, a 5 5 RTC FPAA testchip was implemented in 0.35- m CMOS technology. A set of various circuit primitives, prising that FPAAs have not obtained the commercial success of such as one- and four-quadrant multipliers, an Euclidean distance FPGAs. However, recently, triggered by the current dominating operator and a fourth-order log-domain filter, were mapped on system-on-chip (SoC) trend, a new interest has awakened in the the chip in order to demonstrate the versatility of the approach. field of analog reconfigurable circuits as part of larger field-pro- FPAA bandwidth reaches 20 MHz with a power consumption of grammable mixed-signal arrays, in many cases, driven by the 30 W/TE and precision errors below 3%. need of integrating sensor and actuator signal conditioning or Index Terms—Analog signal processing, CMOS, field-pro- for integrated power-management applications [2]–[4]. grammable analog array (FPAA), log-domain, low power, reconfigurable circuits, translinear. FPAA and general-purpose analog reconfigurable circuits can be classified in discrete time or continuous time. Discrete-time FPAAs are based on switched-capacitor techniques [5]–[7], I. INTRODUCTION switched currents [8], or in different kinds of pulse width modulation (PWM) conversion of the analog signal [9], [10]. IELD-PROGRAMMABLE analog arrays (FPAAs) are a F type of reconfigurable integrated circuits capable of im- plementing a wide variety of analog signal-processing functions Common limitations of discrete-time FPAAs are bandwidth and noise (both due to the switching nature of the signals). Continuous-time FPAAs are based on operational amplifiers [1]. Like FPGAs, their digital counterparts, FPAAs were cre- [11], techniques [1], [12]–[14], current conveyors ated with the purpose of reducing the design and test cycles in a [15], [16], in translinear loops [17], [18], or in combinations fast-growing market more and more driven by the requirements of some of those [19], [20]. Continuous-time FPAAs usually of fast prototyping and cost reduction. have higher bandwidth than discrete-time ones; however, it is The success of FPGAs relies on the high degree of standard- more difficult to obtain a good programmability under wide ization that the digital design has, allowing the implementa- bandwidth or dynamic range. It should be noted that each type tion of almost any operation with only the interconnection of a of FPAA is suitable for implementing one kind or another of few different types of simple library blocks. Unfortunately, this analog signal-processing primitives, so there is no clear advan- standardization does not occur in the FPAA analog domain for tage of one type over the other nor an easy way to compare four main reasons: the different physical nature of the signals their relative performances in a wide scenario of applications. to deal with current, voltage, and frequency, etc., the wide type Given their characteristics and constraints, translinear-based FPAAs exhibit interesting features. From the design viewpoint, Manuscript received November 21, 2010; revised June 09, 2011; accepted September 12, 2011. Date of publication November 07, 2011; date of current loops of translinear devices can be easily analyzed since the version January 27, 2012. This paper was recommended by Associate Editor product of the clockwise currents has to be equal to the product Darrin Young. This work was supported in part by the Spanish Ministry of Edu- of counterclockwise currents, as a result from the Kirchhoff cation and Science under Project TEC2008-06028/TEC and the European Social Fund (ESF). The work of L. Martínez-Alvarado was supported by the Catalan voltage law application [21]. This means that, for instance, the Department of Universities, Research and Information Society (DURSI) and the product and division operations can be very easily implemented ESF through a research fellowship. with translinear devices. Because of the exponential I–V charac- D. Fernández is with Baolab Microsystems, Institut Politècnic del Campus de Terrassa-Mod. TR25, 08220 Terrassa, Spain (e-mail: [email protected]). teristic in translinear designs, node voltages are logarithmically L. Martínez-Alvarado is with the Basic Science Department, Mexicali In- compressed, so this enables the potential for higher bandwidth, stitute of Technology, B.C. 21396, México (e-mail: luis.arturo.martinez@upc. and implementation of tunable wide-dynamic-range filters or edu). J. Madrenas is with the Advanced Hardware Architectures group, Electronic multiple-input power series synthesis circuits are quite efficient. Engineering Department, Universitat Politècnica de Catalunya (UPC), 08034 Unfortunately, CMOS-based translinear loops have limitations Barcelona, Spain (e-mail: [email protected]). in terms of dynamic range, precision, and bandwidth because it Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. is required that the MOS transistor operates in the weak inver- Digital Object Identifier 10.1109/JSSC.2011.2170597 sion region, and this implies low currents and wide transistors, 0018-9200/$26.00 © 2011 IEEE FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 491 Fig. 1. Wide-dynamic-range translinear element operation principle. Input/output terminals (E; B; C ) are named after bipolar transistors as an analogy. resulting in high parasitic capacitances and therefore slow de- vices. Also, the so-called MOS translinear circuits have been Fig. 2. Wide-dynamic-range translinear element circuit schematic. Note the proposed [22]. They use the square characteristic of the MOS bulk-source connection of all nMOS transistors resulting from the P-well-based manufacturing process. transistor in strong inversion, but the achieved voltage compres- sion is not as good as in native logarithmic translinear loops. Recently, a new type of CMOS wide-dynamic-range translinear specifically, voltage followers and , biased by dc current element was proposed by the authors in order to overcome those sources and , drive and , with a and limitations [23], [24]. Using this translinear element as a main voltage drop, respectively. operates as a transconductor, block, the specification and design of a reconfigurable cell [25], is mirrored by the pair and it is driven to the [26] to be used as a key building block of a larger FPAA was gate. Thus, besides following the input voltage, is further performed. Finally, a proof-of-concept 5 5 FPAA testchip was increased by the incoming current copy. This way, since designed, manufactured, and tested. rises with the input voltage, is increasingly predis- In this paper, we present the characteristics and results of this torted, achieving the desired form of Fig. 1 characteristic. On FPAA by revisiting and demonstrating the wide-dynamic-range the other hand, transistors to are used to compensate translinear element characteristic in Section II, the reconfig- for the additional current injected in the terminal by , so urable cell and the FPAA in Section III, and the experimental and currents are equalized. This allows using stacked results and applications in Section IV. translinear topologies in the circuits mapped on the FPAA. A. TE Characteristic Analysis II. WIDE-DYNAMIC-RANGE TRANSLINEAR ELEMENT The exponential characteristic of a MOS transistor operating The core element of the FPAA is the wide-dynamic-range in weak inversion (also known as subthreshold) mode is translinear element introduced in [23] and [24]. Its purpose is to extend the exponential characteristic of the MOS transistor weak-inversion region to the moderate and strong inversion re- (1) gions, so translinear loops can be implemented in CMOS tech- nology without the bandwidth and dynamic range limitations where is the MOS drain current, represents the specific associated with the use of very wide transistors biased with very current that indicates the transition between weak and strong small currents. inversion, is its gate–source voltage, is the threshold The basic operation principle of the wide-dynamic-range voltage, is the thermal voltage, and is the slope due to the translinear element is depicted in Fig. 1. Using the analogy bulk effect [27]. with a translinear device as the bipolar transistor, and assuming The weak inversion model holds for . As common-emitter configuration, is the control terminal of approaches , the exponential shape progressively saturates the translinear element, the common terminal, and the in the so-called moderate inversion region and in the strong in- output terminal. The idea behind the proposed architecture is version region, for , it becomes the classic square to generate a predistortion voltage function of the difference characteristic between the control voltage and the common voltage and apply it to the gate of the output transistor in order to (2) compensate for its loss of transconductance outside its weak inversion region, thus expanding its exponential-characteristic range. provided carrier velocity saturation is not reached, where is The schematic of the proposed translinear element (TE) is the large-signal transconductance or transfer parameter. It is shown in Fig. 2. In this circuit, transistor is the output worth noticing that, since all of the source terminals of both transistor that provides the output current, while the remaining pMOS and nMOS transistors of the circuit are bulk-connected, components produce the input voltage predistortion. More (1) and (2) have been accordingly simplified. 492 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 The TE large-signal operation is difficult to analytically model because the MOS transistors of this circuit operate together in weak, moderate, and strong inversion regions, with different combinations along the input voltage range of interest. Thus, classic weak or strong inversion models of (1) and (2), despite being useful to provide tuning directions [23], can only be used to partially explain the complex circuit behavior. In the Appendix, a complete analysis that demonstrates the goodness of the proposed predistortion circuit using the EKV model [28] is provided. This model continuously interpolates the weak, moderate, and strong inversion regions, so it guaran- tees accurate results. As obtained in (32) of the Appendix, under the indicated conditions, the output current of transistor is Fig. 3. Inversion coefficient ofM M , and M . Transistor sizes and biasings , are the same as indicated in Table II. (3) TABLE I OPERATING REGION FOR THE MAIN TE TRANSISTORS where is in the absence of predistortion and the pre- distortion gate voltage is (4) and and are characteristic, which can be seen also in the figure, with some (5) distortion at high input voltage. Table I reflects the input voltage range for different operation The predistortion grows exponentially, compensating for the regions of transistors , , and , obtained from Fig. 3. output MOS loss of transconductance as its gate voltage in- For , the operating region is the same in the whole input creases. To finish the TE characteristic analysis, let us analyze voltage range of interest. Depending on circuit parameters, the the operating mode of the transistors. In order to place the oper- operation regions range could change but the example shown in- ation region, the Inversion Coefficient is defined as the drain dicates the trends of the transistors that compose the exponential current normalized to the specific current function approximation. (6) B. Stability and Small-Signal Analysis Despite the additional nodes inserted between the input and It is commonly considered that the moderate inversion region output MOS, the TE exhibits good dynamic behavior. All in- of a MOS transistor spans one order of magnitude below and ternal nodes are low-resistance nodes, since all of them are as- above the MOS specific current , i.e., for . sociated with a low resistance, i.e., with a transconductance, as As explained before, transistors , , and play a opposed to the much higher resistance of a MOS output con- major role for the predistortion of gate voltage. Fig. 3 ductance. This can be easily verified inspecting Fig. 2, where shows , , and as a function of the input voltage , all internal nodes are either connected to a MOS source or to for typical parameters. The two horizontal lines of the figure a diode-connected MOS. In both cases, the node ends up con- divide the three operation regions. Since is constant, nected to a MOS transconductance. for all of the input voltage range, and it is not Since all internal nodes are apparently low-resistance, their represented in the figure. It can be observed that, for increasing associated poles are expected to be located at high frequen- values, starts in strong inversion and falls down to cies, normally beyond the unity-gain frequency. Therefore, weak inversion, contrary to and . This means that, for they should not produce significant phase degradation, thus low input voltage values, when the output MOS transistor approaching single-transistor dynamics. However, this asser- operates in weak inversion, drop is more or less constant tion holds whenever the low-resistance condition is valid and and thus . As enters moderate and weak associated parasitic capacitances are limited to the normal node inversion, is progressively reduced, increasing faster values. than , as it has been previously analyzed. Thus, the behavior The small-signal equivalent circuit is depicted in Fig. 4(a). No of and explains the adjustment of exponential output load is included, assuming is biased with an ideal FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 493 Fig. 4. (a) Small-signal model of the TE. The top follower-amplifier chain is associated with M , while the bottom chain is associated with M . (b) Voltage- follower stage model. current source. The circuit has been compacted by combining where denotes the parallel combination of node resistance some of the small-circuit elements as follows: and parasitic capacitances (9) A pole-zero transfer function is obtained. If and , zero and pole will almost cancel out. On the con- trary, as grows or product is reduced, pole and zero are splitted, thus producing phase reduction in between. For the follower-amplifier chain, node has a high product since depends on output con- (7) ductances. Regarding , this capacitance can be limited to the range of because despite the fact that is a where is the bulk-well capacitance and the other parameters common-source stage, its voltage gain is kept low due to follow the usual naming convention. the diode-connected . Thus, the Miller effect on The full analysis of this circuit leads to a long expression can be neglected. Therefore, the pole-zero pair can be kept that is difficult to deal with. Thus, in order to make feasible sufficiently close to prevent large phase shifts. Furthermore, a hand analysis that provides circuit insight, some simplifica- the poles of both follower and common-source amplifier are tions are taken, yet an effort is made to preserve the circuit high-frequency because of the associated low resistances. This main properties. First, node has been grounded. Second, the allows to consider that the current source of Fig. 4(a) frequency effects due to the current mirrors are neglected, al- is not frequency-dependent for the bandwidth of interest. Thus, though the loading effect of is considered because of its and frequency effects can be neglected for relevance. Third, it is possible to take advantage of the circuit the chain. similarity, since both input voltage followers are connected to The only effect of the chain on chain is thus a change common-source voltage gain stages. in the follower voltage gain which, contrary to the conventional In Fig. 4(a), two processing chains are clearly shown, the voltage follower, becomes larger than one because of the pre- upper being associated with follower-amplifier chain and distortion stage: the lower with . Both chains have almost the same topology. There are, however, two significant differences: 1) the follower- (10) amplifier chain associated with is loaded by the diode-con- nected transistor while follower-amplifier output is a The dynamic behavior of the chain voltage follower is high-resistance node if voltage gain is to be provided and 2) different to the because of two differences stated before: 1) the controlled current source [ in Fig. 4(a)] in the upper since is assumed to be high-resistance loaded, the voltage chain center that arises from the current mirror. As gain of the common-source stage becomes high and the Miller input voltage grows, increasing is mirrored and injected into effect produces a significant increase in the input impedance, gate node, subtracting to and significantly reducing thus loading with higher capacitance the follower stage and 2) bias current. when input voltage rises, as increases, the biasing in Let us consider the follower stage of the chains. In Fig. 4(b), decreases, thus reducing the value of the follower transconduc- a simplified circuit, applicable to both chains, is shown. Ana- tance. lyzing the circuit, we have Adapting (9) to the case of chain follower, taking into account the dc gain change due to predistortion, we obtain (8) (11) 494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 TABLE II SIZING AND BIASING OF THE TRANSLINEAR ELEMENT where (12) Now, in (11) the pole and zero become splitted due to the reduction (increase) of and to the increase of contributed by combined with the Miller effect. Further- Fig. 5. Measurement of the wide-dynamic-range translinear element I –V characteristic. The figure also shows the simulated characteristic of a MOS more, the pole value is reduced and it approaches the output transistor with the same size as M and best-fit of purely exponential charac- dominant pole frequency because it becomes a large resistance teristics for comparison purposes, along with the zero-bias currents I and the node. This is not the case of the zero because of its dependence normalized transconductances g . also on . All together, this produces a peaking effect around the dom- inant pole in the transfer function which may lead to un- RTC architecture is shown in Fig. 6. It has been designed to stability. This is the reason why capacitor has been intro- be placed in a column/row-ordered regular matrix, in which duced. increases the capacitance between the input and the the column/row ( and ) selection bits and the signal bus, gate and, provided it is sufficiently large, it leads to a reduc- composed of four horizontal and four vertical signal paths, are tion in both pole and zero frequencies, but faster for the zero, shared among the cells belonging to the same row and column, thus becoming closer again and approaching cancellation. With respectively. All other buses are shared among all the cells in , the TE shows good stability behavior under all operating the matrix, and to address a particular cell, the row/column ( conditions, as will be seen in Section IV. and ) selection bits are used. This simple approach is adequate for small and mid-sized FPAA matrices, however for big FPAA C. TE Implementation a different approach, such as multilevel routing on the signal Transistor sizing for the 3.3-V 0.35- m AMIS paths, should be used instead. P-well-based CMOS technology is summarized in Table II. For This RTC is composed of six main blocks, namely: other technologies, sizing can be easily done with the template • the wide-dynamic-range TE; reported in [23], where the impact of each circuit parameter • the programmable current source (PCS), which operates as on the translinear element – characteristic is shown. The calibration of the TE biasing currents and and also as dynamics of the translinear element can be tuned by means of stand-alone pMOS/nMOS current source; capacitor . This capacitor introduces a degree of freedom to • the programmable current mirror (PCM), which allows for provide stability in closed-loop configurations and its value can the selection of several commonly-used current gain fac- be estimated with parametric ac simulations. tors and allows inversion of the input/output current signs; A measurement of the translinear element character- • the programmable capacitor (PCAP), required to perform istic is depicted in Fig. 5, along with a simulation of the output log-domain filtering or implement dynamic-translinear transistor characteristic and best fits of purely exponential loops; functions. The text in the figure also indicates the zero-bias cur- • the switch matrix (SM), which allows both connecting the rents and the transconductances normalized to the drain or RTC to the different bus signal paths and also rerouting collector current, for both the MOS transistor in weak inversion them in case of bus congestion; and the translinear element. Depending on the maximum distor- • the configuration Registers (REG), which store the 51 bits tion tolerated by the end application, dynamic range is extended necessary to configure the RTC blocks. by two or three decades to near the 1-mA maximum current that In the cell, there is also a certain number of additional tran- can drain with the given supply voltage. The measurement sistors and transmission gates vital to implement basic biasing was taken with the translinear element embedded in the FPAA, topologies used on translinear circuits (such as the Enz-Punzen- so it encompasses the effect of the FPAA parasitics. berger connection [29]) and the calibration mode, required to allow a fine tuning of the TE characteristic. Also, in order to III. FPAA ARCHITECTURE reduce the number of bits (and thus the area) required to im- The FPAA architecture is based on a coarse-grained approach plement the configuration registers, some of them were shared in which a single computational analog block (CAB), namely among different blocks of the RTC; therefore, it is generally the reconfigurable translinear cell (RTC) [25], provides all of not possible to use all of the blocks inside a single RTC at the the circuitry required to build dynamic translinear loops. The same time. However, the architecture was designed in order to FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 495 Fig. 6. RTC architecture. The graph depicts the main blocks of the RTC, such as the TE, the three SMs, the PCAP, the PCM, the two PCSs, the various configuration registers (REG), and some additional circuitry. allow simultaneous use of those blocks which implement to- used. Current buffers were designed using scaled current mirrors gether the most commonly used topologies in translinear de- and switches, the VI converter using an opamp-based Howland sign, such as the PCM and the PCAP or the PCS and the PCAP. circuit (as reported in [30]) and the IV converter using an opamp Note also that, for increased versatility, the TE itself can be used and a resistor. The operational amplifiers used in the converters as an adjustable bipolar transistor by means of its calibration have more than 100 MHz bandwidth and rail-to-rail character- currents, providing, for example, other current-mirror ratios not istics, and they are based on the input transconductor reported provided by the PCM or even additional circuit topologies, such in [31] and the output stage reported in [32]. as, simple transconductors or differential pairs. The FPAA was implemented in a 0.35- m P-well based Besides the RTC, the FPAA also contains additional blocks CMOS technology. It includes a 5 5 matrix of RTCs (taking to perform biasing, RTC addressing and programming, and I/O 0.9 mm of circuit area), 10 I/O cells around two sides of the buffering. The I/O cell purpose is to connect some signal bus FPAA (0.30 mm of circuit area), a biasing and decoupling lines to the outside world, one for each row and column, and block (37120 m ), and the programming logic (69230 m ). perform the following operations: The supply voltage is 3.3 V. The power consumption of the • Self-disable if the signal line is not assigned as I/O. RTC is between 0 and 189 W, depending on the operating • Pass gate, to connect electrically the signal line to the inte- mode, and between 0 and 1 mW for the I/O cell, depending grated circuit pads. heavily on the external load conditions and operating mode. A • Current input buffer, to allow entering the FPAA with microphotograph of the FPAA is shown in Fig. 7, pointing out higher currents than the ones inside the translinear loops. its main blocks. • Current output buffers, to allow exiting the FPAA with higher currents than the ones inside the translinear loops. IV. EXPERIMENTAL RESULTS • Voltage-to-current converter (VI), to allow entering the To validate the proposed FPAA, different application circuits FPAA directly with a voltage signal. were physically mapped onto the translinear array and exper- • Current-to-voltage converter (IV), to allow exiting the imental measurements were extracted. We present first the re- FPAA directly with a voltage signal. sults of the TE alone, then a one-quadrant multiplier applica- Those operations ease the FPAA interfacing with discrete com- tion, a four-quadrant one, a Euclidean distance operator, and, ponents. The purpose of the current buffers are, for example, finally, a log-domain filter. These circuits have been chosen to driving the higher parasitic capacitances between the discrete characterize the FPAA because they are either part of the basic components interconnections, and the purpose of the VI and IV set of analog primitives extensively used in signal processing converters is to be able to connect the FPAA to voltage signals, or communication systems or they have proven to be helpful in since in the discrete world the voltage-mode design is widely pointing out nonlinearities in the FPAA operation. 496 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 Fig. 9. One-quadrant translinear multiplier circuit schematic. I and I are the input currents, I is the output, I the unitary current, and V a voltage bias. Fig. 7. Microphotograph of the FPAA. The main blocks are pointed out. Shown 2 area is 1400 m 1100 m. Fig. 10. Measurements, in log-scale, of the one-quadrant translinear multiplier implemented on the FPAA. The measurement shows the output current I versus the input current I for different values of I . Unitary current I was set to 800 nA. Fig. 8. Measurement of the relative I output current dispersion, with and without calibration, between the 25 TEs of a single FPAA for different output current levels. A. Stand-Alone TE As noted before, Fig. 5 shows the – characteristic of the TE inside the FPAA and, for comparison, the simulated characteristic of the output transistor and the best-fit of purely exponential characteristics. As can be seen, the dynamic range is extended between two and three decades thanks to the predistortion effect discussed in Section II. Fig. 8 shows the dispersion of the output current measured among the 25 translinear elements of a single FPAA, with and without calibration provided by the PCSs. Note that the calibra- tion allows reducing the dispersion by a factor of almost 10 in most of the range. Above 10 A, the dispersion increases sig- Fig. 11. Measurements of the one-quadrant multiplier ac response for different nificantly, because in this region the circuit behavior is mainly gain conditions. The unitary current I was set to 800 nA. controlled by the current comparator formed by and , and current comparators are known to be prone to mismatch. Anyway, the mismatch peak is located around 60 A and, as de- not likely introduce any additional significant error on the final picted in Fig. 5, in this region the deviation from the purely ex- application. Static power consumption of the RTC configured as ponential characteristic is significative, thus the mismatch will stand-alone TE is 30 W. FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 497 Fig. 12. Four-quadrant translinear multiplier circuit schematic. B. One-Quadrant Multiplier Fig. 9 shows a schematic of a one-quadrant translinear multi- plier implemented on the FPAA. The circuit can be analyzed by applying the translinear principle, which states that the product of currents flowing through the collectors of clockwise-oriented translinear elements is equal to the product of counterclockwise ones, resulting in (13) where and are the input currents, is a bias current source (often referred as unitary current), and is the output. In Fig. 10, a measurement of the one-quadrant multiplier output current is plotted versus the input current for some values of . In all cases, the unitary current is kept at 800 nA by means of a PCS and the I/O cells were configured as pass-gates. As depicted in the figure, the multiplier shows a correct behavior up to five decades of current range. Fig. 11 shows the ac response of the multiplier with an unitary current 800 nA and for four different gain conditions, which re- veals an almost constant 3-dB bandwidth independent of the gain. The maximum multiplier bandwidth was also measured, reaching 20 MHz for a 10- A unitary current. Static power consumption without inputs reaches 275 W. The total harmonic distortion (THD) of the multiplier was measured by means of a spectrum analyzer and a signal gener- ator. The input IO cells were configured as VI converters and the output as IV converter, all with a conversion gain of 10 mV A. This IO arrangement allowed a direct interface with the mea- suring instruments. The input voltage was biased with a 200-mV (equivalent to 20 A) dc voltage, while was set to a 140-mVpp 10-kHz sine wave with a 200-mV dc bias. Due to limitations in our test equipment, only large-signal distortion could be measured, reaching a THD 57 dB. The noise floor Fig. 13. Mapping of the four-quadrant translinear multiplier of Fig. 12 on the was below the harmonics of the output signal, however, due to FPAA. Dotted lines represent the interconnections between different RTCs. the translinear nature of the FPAA, noise is nonstationary and biasing-dependent (see [33]) and thus difficult to quantify with standard measurement setups. where , , and are the differential input currents, C. Four-Quadrant Multiplier is the unitary current, and and are the differential output current. The working principle is based on the cascading Fig. 12 shows a four-quadrant translinear multiplier circuit of two two-quadrant multipliers [21] (the first one formed by the schematic. By applying the translinear principle, the following TEs to and the second one formed by the TEs transfer function is obtained: to ). The complete schematic of the multiplier can be mapped on (14) the FPAA with the arrangement shown in Fig. 13. As can be 498 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 Fig. 16. Euclidean distance operator circuit schematic. Fig. 14. Steady-state measurements of the four-quadrant multiplier imple- mented in the FPAA. The figure shows the differential output current I versus the differential input current I for different values of the input current I . I was set to 9.6 A. Fig. 17. Measurement of the output characteristic of the Euclidean distance operator. Fig. 15. Transient measurement of the four-quadrant multiplier implemented in the FPAA. The figure shows the differential input voltages in the top (a 1-MHz, 125-mVpp sine wave and a 100-kHz, 200-mVpp triangle wave) and the differ- ential output voltage in the bottom. seen, its implementation requires 14 of the 25 available RTCs. Dotted lines represent the interconnections among different RTCs. Measurements indicate that different routing intercon- nection resistances between TE emitters of different RTCs can increase the distortion of the circuits implemented with the FPAA. These nonuniform resistances cause different voltage drops on the TE emitters of the circuit, introducing signal-de- Fig. 18. Contour plot of the measurement shown in Fig. 17. pendent distortion terms on the circuit transfer characteristic. It is recommended that the mapping of the circuit is done as symmetrical as possible to prevent signal degradation due to plots, which is in agreement with the statistical measurement of this effect. Future RTC designs based on this TE may include Fig. 8. two TEs placed together in a single RTC to effectively avoid Fig. 15 shows a waveform measurement of the four-quad- this problem. rant multiplier mapped on Fig. 13. I/O cells were configured as Steady-state measurements of the multiplier’s performance voltage to current converters on the four inputs ( , , are shown in Fig. 14, where the differential output current and ) and as current to voltage converters on the two outputs is plotted versus the input current for an of 10, 6, 2, ( and ), all with a conversion gain of 10 mV A. 2, , 6, and 10 A. The unitary current was set to 9.6 A. Unitary current was set to 9.6 A (equivalent to 96 mV) and dc Numerical analysis indicates that the relative error measured bias of the two input signals to 15 A (equivalent to 150 mV). with respect to the theoretical value of (14) is below 3% in all As the measurement shows, the FPAA correctly multiplies the FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 499 Fig. 19. Schematic of the fourth-order log-domain low-pass filter implemented on the FPAA. 100 kHz, 200 mVpp triangle wave by the 1 MHz, 125 mVpp sine wave to yield the 150 mVpp modulated wave. Additional measurements indicate that the deviation from the theoretical expected 130 mVpp output amplitude is systematic and fre- quency-independent and mainly due to offset in the VI and IV converters. Contrary to the RTCs, the I/O cells do not feature any calibration capabilities to compensate for systematic errors. Power consumption is 584 W for the FPAA RTC core. D. Euclidean Distance Operator A one-quadrant Euclidean distance operator was also imple- mented on the FPAA. This operator takes two input currents ( and ) to give an output current equal to (15) The translinear circuit schematic can be seen in Fig. 16. It can be interpreted as two one-quadrant multipliers ( and ), with both their inputs equal and with their current outputs added and injected back as unitary currents. For the circuit mapping, three cells were used as PCMs to get an output current and to inject it back as unitary currents in the multipliers, eight were used as translinear elements and two as SM elements. Also, five I/O cells were used as current buffers to drive and sensing the input and output currents. A measurement of the output characteristic versus the two in- puts is depicted in the 3-D plot of Fig. 17, and a contour plot is shown in Fig. 18. Theoretically, the output current should follow the shape of an inverted cone and the contour plot that of equally-spaced circles; however, a small distortion can be seen for low values of and due to the limited output resistance of the current buffers on the I/O cells. Static power consump- tion without inputs is 733 W, from which more than 500 W belong to the current mirrors alone. Fig. 20. Mapping of the fourth-order log-domain low-pass filter on the FPAA. 2 The figure shows the 5 5 core of the FPAA and the I/O cells. Dotted lines E. Log-Domain Filter represent the interconnections between different RTCs. Fig. 19 shows a fourth-order log-domain low-pass filter cir- cuit schematic implemented on the FPAA. The log-domain filter can be interpreted as a logarithmic compressor , an expo- capacitance values. Note that the filter can be easily tuned by nential expander and a chain of TEs and current source modifying either the unitary currents or the filter capacitances. pairs with a capacitor in between, each pair creating a pole at The schematic was mapped on the FPAA as depicted in Fig. 20. It took 18 of the 25 available RTCs, ten of them config- (16) ured as TEs. I/O cells configured as VI and IV converters were used to allow interfacing in voltage mode. Also, two additional where is the normalized transconductance in units, as I/O cells were configured as pass-gates to provide the reference it appears in Fig. 5, are the tuning currents, and are the voltage . 500 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 characteristic little changed despite the decrease on the cutoff frequency. A simple cascode transistor on the PCM and PCS outputs proved to be very helpful in removing this parasitic pole because it significantly increased the output impedance of those blocks (thus reducing the capacitance seen on the TE collectors) while giving a voltage-clamp functionality to those heavy parasitic nodes. Simulated results of the same filter for 800 nA with and without the cascode-transistor improvement can be seen in Fig. 22, along with the theoretical zero-pole response of the filter. It can be seen that the PCS and PCM cascoding also allows for a much better matching between the circuit character- istic and the theoretical zero-pole response expected from (16). Power consumption depends on the biasing currents which set the filter bandwidth, and has a minimum value of 300 W. Fig. 21. Measurement for different I currents of the fourth-order log-domain low-pass filter implemented in the FPAA. The filter capacitance was set to C = V. CONCLUSION 2.5 pF. We have presented a field-programmable analog array (FPAA) based on a wide-dynamic-range TE capable of ex- tending the exponential characteristic of the MOS transistor far beyond the weak inversion region, thus providing more than five decades of useful operating range. The TE circuit has been ana- lyzed by means of the EKV model and in small-signal analysis. The results explain the excellent exponential approximation of the proposed circuit. The proposed FPAA core architecture, based on the RTC, allows for an efficient, compact, and pro- grammable implementation of the main translinear primitives. Also, the proposed interfacing I/O architecture provides all of the functionality and versatility required in most reference environments. The implemented FPAA testchip, that contains a 5 5 array of RTCs, has shown full functionality and very good performance. The logarithmic-compressed nature of the sig- nals routed among RTCs, inherent to its translinear operation, Fig. 22. Measurement and simulations of the filter for I = 800 nA. The and the higher current handling capabilities of the wide-dy- plot shows the measured characteristic, the simulated one, the same simulation but adding cascode stage at the output of the PCM and PCS blocks, and the namic-range TE outside the weak-inversion region, have theoretical zero-pole characteristic of the filter according to (16). provided a good tolerance to the parasitic capacitances routing of the whole FPAA. Two architecture limitations have been identified, such as the routing resistance of the emitter connec- Fig. 21 shows the filter transfer characteristics with the pro- tion, which can be avoided in most cases by using a symmetrical grammable capacitors set to 2.5 pF and different values routing or placing two emitter-connected TEs on a single RTC, of the currents. DC bias of the input signal was set to 1 A. and the parasitic capacitances effect of the PCM and PCS on Despite the good filter tunability thanks to the PCSs, distortions the filter characteristic, which can be greatly reduced by adding on the transfer characteristic shape can be observed, along with a cascode transistor at their outputs. a limited stopband attenuation. Also, the measured bandwidths In order to demonstrate this performance and the approach differ from those expected from (16). The limited stopband at- versatility, several application circuits extensively used in signal tenuation could be explained as a parasitic signal coupling due processing or communication systems have been mapped and to the layout interconnection capacitances. For the distortion on experimentally verified. In particular, an analog multiplier (both the filter’s characteristic and the bandwidth errors, additional one and four-quadrant configurations), an Euclidean distance simulations indicated that they were due to the heavy capaci- operator, and a tunable log-domain filter have been mapped tance load introduced by the output transistors of the PCM and and experimental measures have been reported. Despite the un- PCS. Besides lowering the cutoff frequency, those parasitics avoidable performance reduction due to programmability ad- also introduced an unwanted dominant pole at lower frequen- dition, the translinear approach allow circuits to reach band- cies, thus distorting the whole ac characteristic of the filter. This widths up to 20 MHz with a power consumption of 30 W/TE unwanted pole behaves almost like the filter poles, that is, it ex- and precision errors below 3%. Despite that, as discussed in hibits frequency dependence on the tuning current . This ef- the introduction, a direct comparison among different FPAA ar- fect can also be seen in Fig. 21, where the unwanted pole moves chitectures and their figures-of-merit is not possible, Table III along the filter poles, leaving the distortion of the overall Bode shows the main characteristics of different FPAAs reported in FERNÁNDEZ et al.: TRANSLINEAR, LOG-DOMAIN FPAA ON STANDARD CMOS TECHNOLOGY 501 TABLE III COMPARISON AMONG FPAA DESIGNS : Bandwidth decreases to 3 MHz in filter applications. : Distortion/noise of the core signal-processing element only. : See the exact dissipated power on each application example in Section IV. : On specific applications. the literature. A quick look allows to position this design in the • As previously indicated, no body effect is modeled since small-area, low-power, mid-frequency application space. all sources are tied to bulks. • Equal threshold voltage for all nMOS transistors. APPENDIX The output of voltage follower, using the EKV model of (17), is In order to provide more insight into the internal TE opera- tion, the EKV model [28] has been applied. This model interpo- (18) lates in a single closed expression the weak and strong inversion MOS regions, providing also good approximation for the hard where is a constant voltage defined by the bias current as to model moderate-inversion region. A simple form of the main EKV expression for the MOS drain current, assuming satura- (19) tion, is (17) From (17) and (18), becomes (20) where represents the specific current and is the so-called large-signal transconductance or transfer parameter. It The output MOS gate voltage holds almost the same form can be easily shown that, for , i.e., for strong inversion, of (18) (17) asymptotically converges to (2). Also, for the weak-inver- sion condition , (17) approaches (1). In the following, the large-signal behavior of the TE circuit (21) of Fig. 2 is studied with the EKV model, applying the following assumptions and constraints in order to simplify the analysis. However, now , so depends on the current • No channel modulation (Early effect) is considered for any difference between the bias current and , which is injected transistor. Since all nodes are connected to either a tran- to the node by means of mirror . Thus, besides sistor source or a diode-connected transistor, a low the proportional dependence on , smaller reduces in turn resistance is connected to each node. Thus, all nodes are , creating an additional term . This voltage increment low-resistance, thus influence can be safely neglected is responsible for the predistortion. Equation (21) can be in first order. The only exception is the output node . If rewritten in form (22) to explicitly represent . necessary, the correction factor could be appended to the output drain current expression. (22) • Ideal unity-gain current mirrors, with no mismatch, and ideal current sources are assumed. where, as in (19), is a constant voltage defined by the bias • All transistors operate in saturation. current and is in absence of predistortion • The current correction compensation network is ignored and is set to zero. This simplifies the analysis while (23) preserving the result generality. 502 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 The predistortion term applied to gate voltage is other current is applied to their sources. In this case, (19) and (23) simplify to (24) (30) Notice that for , is almost null. Since both Also, general of (20) is simplified for weak inversion to and follow and transistors , , and have been sized to guarantee in (25) in the absence of predistortion (31) voltage, when is in weak inversion for low drain current, is necessarily in weak inversion also, as shown in Applying (31) and (30) to (29) and changing form with (22) results in (25) As a consequence, when is in the weak inversion region, it does not receive significant predistortion, which is not needed (32) because of the exponential characteristic in that region. As approaches , progressively grows faster and faster in where (24). In the limit it tends to infinity. Thus, this is a suitable func- tion to compensate for the progressive saturation of the ex- (33) ponential characteristic. Applying now (17) to , and replacing (21), the output As expected in weak inversion [see (1)], (32) exhibits output MOS drain current for all operation regions is finally obtained current exponential growth with input voltage in the absence in of predistortion. However, the exponent now contains a second voltage term controlled by the predistortion . This predis- tortion voltage in turn grows exponentially with , as shown in (33). This progressive boosting explains the compensation of the slope reduction as it enters into the moderate and strong inversion regions. (26) ACKNOWLEDGMENT where has been defined in (20). Again, the output current The authors would like to thank M.Sc. students P. Michalik behavior can be analyzed as a function of the predistortion cur- and D. Kapusta for their outstanding work developing the RTC. rent . For , assuming weak inversion for and The authors also express their acknowledgement to the anony- thus , (26) can be approximated to mous reviewers for helpful suggestions that contributed to im- proving the paper quality. (27) REFERENCES and the two first terms of the Taylor series for the root function [1] E. Lee and P. Gulak, “A CMOS field-programmable analog array,” of are taken as IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1860–1867, Dec. 1991. [2] “Programmable System-on-Chip.” [Online]. Available: http://www. cypress.com/?id=1353 [3] “Dynamically Programmable Analog Signal Processing.” [Online]. (28) Available: http://www.anadigm.com [4] “SmartFusion Mixed-Signal FPGAs.” [Online]. Available: http:// www.actel.com/products/SmartFusion/default.aspx Substituting into (27), we have [5] H. Kutuk and S.-M. Kang, “A field-programmable analog array (FPAA) using switched-capacitor techniques,” in Proc. IEEE ISCAS , 1996, vol. 4, pp. 41–44. [6] S. Koneru, E. Lee, and C. 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Fernandez, “Translinear Catalunya (UPC), Barcelona, Spain, in 1986 and signal processing circuits in standard CMOS FPAA,” in Proc. 16th 1991, respectively. IEEE Int. Conf. Electron., Circuits Syst., 2009, pp. 715–718. He is currently an Associate Professor with the [27] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on Department of Electronic Engineering, UPC. He has weak inversion operations,” IEEE J. Solid-State Circuits, vol. SSC-12, participated in several European projects and coordi- no. 3, pp. 224–231, Mar. 1977. nated four Spanish national research projects as well [28] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling. as several contracts with companies. Currently he New York: Wiley, 2006. coordinates two national projects on MEMS-on-chip [29] M. Punzenberger and C. Enz, “A new 1.2 V BiCMOS log-domain in- and microsensor bio-inspired signal processing. He tegrator for companding current-mode filters,” in Proc. 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