A CMOS continuous-time field programmable analog array

A CMOS Continuous-Time Field Programmable Analog Array C.A. Looby and C. Lyden National Microelectronics Research Centre, University College, Cork, Ireland E-mail: [email protected], [email protected] Abstract encountered with FPGAs. Apart from the usual challenges inherent in analog IC design (such as meeting linearity, noise and bandwidth A circuit design for a Field Programmable Analog Array is presented specifications subject to process and environmental variations), the which improves accuracy and repeatability compared to previous FPAA has two additional obstacles: designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to imple-  The configurable routing should not affect the accuracy of the ment the user's chosen circuit. The configurable connections are instantiated circuit realised by CMOS switches and a new innovation is that these are  The analog blocks must provide a variety of useful pro- either buffered or nulled to cancel parasitic error. The function grammable functions blocks are Op-Amps combined with passive networks which al- low programmable transfer functions with accuracy insensitive to To date, general purpose FPAAs have tackled these problems variations in process parameters and environment. The intended using transconductor[3, 4] or switched-capacitor techniques[5, 6]. application area is the rapid development of analog circuits which This paper describes a routing method that achieves wide band- are presently prototyped by PCBs stuffed with Op-Amp and passive width due to continuous-time operation. It offers accurate signal components. The concept has been demonstrated on a CMOS IC transfer without calibration since the routing is nulled and the func- and the resulting performance shows the feasibility of this approach tion accuracy is limited only by device matching. to general purpose FPAA technology. Section 2 details the routing elements used to configure the FPAA. The Function Blocks used in the FPAA are described in Section 3 in- cluding how their advantages in terms of accuracy and programma- 1 Introduction bility is achieved. In Section 4, we discuss the overall architecture of a demonstrator FPAA using the elements already discussed. The The trend in modern hardware development of increasing integration results for the Function Blocks are presented in Section 5. and decreasing design turnaround time leads to the widespread adap- tion of field programmable devices[1]. While the bulk of electronic circuitry now consists of digital logic, there will also commonly be 2 Routing elements a portion which interfaces to the analog sensors and actuators that the real world necessitates. In general, the FPAA gets its configurability from the routing net- The development of the analog portion requires field pro- work which allows the user to control how signals flow through the grammable devices to avoid large Non-Recurring Engineer- available analog resources. ing(NRE) costs and to reduce turnaround time[2]. The digital cir- Firstly, CMOS switches are chosen for the routing mechanism be- cuitry has used FPGAs to improve flexibility and reduce project cause they are easy to configure digitally and have a simple dominant duration. The field programmable analog devices would need to R parasitic, the ON-resistance on [7]. This swamps any parasitics of offer ease-of-use and flexibility benefits similar to those of FPGAs. There are fundamental difficulties in realising a versatile and use- any OFF switches attached to the same node at the sub-1 MHz signal frequencies we address. ful Field Programmable Analog Array(FPAA) over and above those The problem of accurate FPAA operation is to eliminate error R due to current flow in the on of the switches routing the signal between the diverse source and load impedances of active Function Blocks. As an example, consider when the pass-switch approach is used for routing among the Function Blocks, as shown in Figure 1. The switch connects a source of finite impedance to a load of finite  Function Block Function Block Ron Ron i In In #1 #2 Out Ron Vout1 Vin2 Force Out Zout Zin Sense Ron Figure 1: Illustration of the switch Ron problem Figure 2: Buffer & Force-Sense nodes impedance. These impedances will differ depending on the config- impedance loads down to 5kΩ because the Op-Amp gain ensures uration. The signal transfer to Function Block 2 is given by: negligible source resistance. Minimum size switches with their large Ron can be employed V 2 =V Z in in out1 Z +R +Z out on in when buffered and the benefits are not only in layout area but par- asitic capacitance and crosstalk. The node buffers are designed to The switch ON-resistance(Ron) is dependent on voltage, tempera- have excess bandwidth compared to any other elements in the signal ture and process variables. Therefore the transfer function of the flow to ensure that they do not limit performance. node corresponds to a voltage and configuration dependent loss. Prior solutions adopt transconductor[3] and switched- capacitor[5, 6] techniques to achieve a routing node with a well 3 Programmed Function Blocks defined transfer function. In standard IC technology, it is difficult to build-in precision analog The switched capacitor approach transmits signals as charge which is not subject to loss due to Ron . However since it oper- circuitry because component parameters are subject to process vari- ations. While design methodologies such as switched-capacitor and ates on sampled signals, the need for anti-aliasing filters constrains master-slave-control circuits have circumvented this problem, they the bandwidth. The accuracy of the transfer function depends on the are suited to signal processing rather than a general purpose FPAA. ratio of capacitors. Therefore this design method takes advantage To achieve accurate transfer functions with standard IC processes, of the matching devices available in IC technology. it is necessary to use ratios of passive device values, rather than The transconductor approach[4, 8] is a continuous time one and the absolute values alone, as the controlling parameter. The suite the transconductor is part of the transfer function. As such, there is no loss due to Ron but the voltage range is limited by transconductor of Function Blocks proposed here all use Op-Amps under passive device feedback to achieve this. Programmable parameters can be linearity while the overall transfer function depends on active de- obtained by appropriate use of passive and switch networks. vice transconductance and passive device impedance, the product of An example of such a function is signal addition. In Figure 3, which is unlikely to be controlled in a given process or environment. one signal is given a fixed gain and combined in a programmable We have combined the benefits of both switched-capacitor and ratio with another signal. It uses an R-2R CMOS DAC with 5 bits transconductor methods which are: resolution designed to achieve 8 bit linearity.  The function accuracy depends on device ratios. Va+  Signals are continuous time. 10K 50K  The routing has its Ron nulled. Vb+ Continuous-time voltage signals are routed using CMOS pass- 5K 5K 5K 5K switches into high-impedance internal nodes. These nodes are the 10K 10K 10K 10K 10K 10K inputs of unity-gain amplifiers. An Op-Amp with unity closed Vo loop gain(Figure 2) will maximise linear voltage range and input impedance while its low output impedance means it is insensitive to loading. It eliminates current flow in the pass-switches, the main cause of inaccuracy in the internal nodes. For external signals, it is desirable that the buffer also be output- Figure 3: Programmable Adder and Gain Block switched so that each buffer can be fully switched to every route available. Otherwise redundant buffers would cause inefficient All the usual analog layout precautions were rigorously applied FPAA utilisation. By putting the output switches inside the feedback to this block design. The resistors of the R-2R DAC must match loop as in Figure 2, output switching is provided. to eight bits. To achieve this, Gate Poly is used as it has very low Even though this reintroduces current flow in the Ron of the voltage and temperature coefficients compared to other integrated Force switch, the redundant Sense switch means that the error is not resistor materials. The Poly sticks were deliberately designed as seen at the output. It is now possible to configure pins to be inputs non-minimum width to ensure repeatability at the expense of extra or buffered outputs. This Force-Sense approach is suitable for low area. Dummy resistors were also used to combat etching effects so that every active resistor has identical neighbourhood. To ensure Analog I/O uniformity the DAC switches are replicated rather than geometri- cally scaled. The Op-Amp input devices are arranged as a common + + centroid to minimise random input offset. + - The second function is subtraction which can be configured with integration, comparison or fixed gain(Figure 4). The DAC used this time is a resistor string type, because this is more suitable for voltage-mode operation than the R-2R ladder. The ratio of + + C - + Vi 20K Vo Analog I/O Din Reset Dout Routing/Programming Control Vp 500 500 500 Configuration/Parameter Shift-Register R1 R2 Rstring R32 CLK Load Figure 4: Programmable Subtractor Block Figure 5: Structure of Demonstrator FPAA subtraction as well as the integration time constant is programmed by these two DACs. The Subtractor Function Block can act as a The switch boxes and Function Blocks were individually de- window comparator function simply by opening the switch in the signed as described in the previous sections. The overall layout feedback path. As with the Programmable Adder Block, thorough of the IC was automatically Placed and Routed(PAR) with some attention to detail was applied at the layout phase of the Subtractor manual intervention. This manual intervention consisted of guiding Block to ensure the resistor matching. the placement of critical analog blocks and constraining the width, The Subtractor uses two different elements, resistors and capac- spacing and length of the analog signals, which was possible using itors. Because only the resistors match to each other, the time con- Mentor ICgraph version A.4. The automatic PAR completed the stant is unavoidably dependent on the process capacitance. However routing of the configuration bits which was considered non-critical this effect can be compensated using the programmable gain. The and too laborious for manual methods. critical matching between the two channels is assured however. 4 Demonstrator FPAA IC The Configuration Routing Elements and Function Blocks discussed above have been combined in a Demonstrator FPAA IC. The FPAA has an array of four Function Blocks, structured(Figure 5) as a 2x2 arrangement of the Adder and Subtractor modules. A crossbar network using multiplexer switch boxes allows all inputs and outputs of the Function Block array to routed. The multiplexers consist of 8 switches and connect to buffered nodes. The external analog interface is comprised of six pins which connect to Force-Sense nodes in the crossbar network. The Demonstrator FPAA IC(Figure 6) is fabricated in a 2.4m N-WELL double-Poly CMOS process provided by Europractice[9] and occupies an area of 36mm2 in total. Power dissipation is 15mW and the design is core limited, having 29 I/O pins. The configuration data is transferred serially as 118 bits and the Figure 6: Microphoto of Demonstrator FPAA configuration register is double buffered. This allows in-service reconfiguration. Safe power-up is ensured by the reset. Devices can be daisy-chained and partially reconfigured. The configuration A large part of the layout area is occupied by interconnect area stream has a read-back facility. The switch controls are differential and there is potential for compressing the layout significantly so that to minimise crosstalk and common-mode effects. more Function Blocks could be accommodated. 5 Results x2/3 Set x1/3 x1 Gain x20 The Signal Adder circuit achieves 8 bit linearity as shown by Fig- x5 x2 Meas. ures 7 and 8. Resolution is 5 bits and the measurements are within Gain one-eighth of an LSB. This equates to the same monotonicity as 10 dB LSBs 0 0.5 -10 0.2 -20 0.1 0 -30 -0.1 -40 -0.2 1e2 1e3 1e4 1e5 1e6 freq (hertz) -0.5 Figure 9: Adder: Gain Response 0 3 6 9 12 15 18 21 24 27 30 Code (bits) Gain RC=1 RC=2 RC=4 Figure 7: Adder: Integral Non-Linearity dB RC=8 RC=16 50 40 LSBs 30 0.5 20 10 0.2 0 0.1 -10 0 -20 -0.1 -0.2 -30 1e2 1e3 1e4 1e5 freq (hertz) -0.5 0 3 6 9 12 15 18 21 24 27 Figure 10: Subtractor: Common Response Code (Bits) Figure 8: Adder: Differential Non-Linearity Gain Ratio=1 Ratio=2 Ratio=4 Ratio=8 an 8-bit accurate DAC would show at the transitions of the fifth bit. dB Ratio=16 Offset is 10mV when adding both channels equally. The design 24 approaches 1 MHz bandwidth(Figure 9) independent of the ampli- 21 fying factor. Compensation matches the gain setting for constant 18 bandwidth. 15 However the Op-Amp in the case of the Subtractor only has a 12 capacitive load and the dynamics are improved by having a lower 9 drive output, relative to the Adder circuit. The common-mode 6 gain response with various time-constant(RC) settings is shown in 3 Figure 10. Figure 11 depicts the relative gain response of either 0 channel with different gain ratios relative to the other. -3 The Adder and Subtractor Function Blocks are examples of suit- 1e2 1e3 1e4 1e5 able elements for the function array of an FPAA. The diversity freq (hertz) and versatility of further Function Blocks has to be balanced with the unused layout area they occupy if the user doesn' t achieve full Figure 11: Subtractor: Relative Response utilisation.  The two examples above, when arranged in a crossbar network [4] E.K.F. Lee and P.G. Gulak, “A Transconductor-Based Field- of switch-buffers, are capable of implementing a large number of Programmable Analog Array”, 1995 IEEE ISSCC Digest of Tech- the glue circuits which combine signals linearly. The switch-buffer nical Papers, pp. 198–199, Feb. 1995. allows the programmable connection of Function Blocks. Accu- [5] H.W. Klein, “Circuit development using EPAC technology: an racy can be maintained to an 8-bit level, sufficient for most target analog FPGA”, Proceedings of the SPIE - The International So- applications. ciety for Optical Engineering, vol.2607, pp. 136–44, 1995. The results demonstrate that our architecture produces satisfac- tory performance in spite of the use of a low-cost, low complexity [6] A. Bratt and I. Macbeth, “Design and implementation of a Field- Programmable Analogue Array”, Proceedings of the 1996 ACM technology. This work has established a lower bound for the ex- pected performance of FPAAs using our architecture and does not SIGDA 4th International Symposium on Field-Programmable require any advanced fabrication steps. Gate Arrays, pp88–93, Feb. 11–13, 1996. However, by taking advantage of the lower parasitics, greater [7] S. Chang, B. Hayes-Gill and C. Paull, “Implementation of a device complexity and higher density offered by modern, fine- Multi-function Signal Detection Block for a Field Programmable geometry processes, this type of FPAA could offer superior perfor- Analogue Array using Mietec 2:4m CMOS Process and Mentor mance and sufficient resources for a wide variety of analog circuit Graphics Software Version 8.2”, 1994 4th Eurochip Workshop development. For example, a submicron BiCMOS implementation on VLSI design training, pp. 226–231, Oct 17–19, 1994. could be expected to offer increased bandwidth up to 20MHz and [8] P. Chow, P. Chow and P.G. Gulak, “A Field-Programmable 50 Function Blocks within similar die area. Mixed-Analog-Digital Array”, Proceedings of the 1995 ACM SIGDA 3rd International Symposium on Field-Programmable Gate Arrays, pp104–109, Feb. 1995. 6 Conclusion [9] Mietec-Alcatel, 2:4m CMOS Standard Cells Design manual, The essential functional elements of an FPAA have been described. Rel. S2SM 2.0.0, 1989. After identifying accurate configuration and precision transfer func- tions as the major barriers to implementing the FPAA, the extent to which previously published FPAAs cope with these design chal- lenges have been summarised. The Op-Amp and programmable passive network have been pro- posed as the solution to the programmable parameter circuit for a general purpose FPAA. The buffered switch has been examined as a way of eliminating the configuration error due to ON-resistance Ron . By demonstrating the complete concept on a small scale with an inexpensive technology, this FPAA when migrated to a small- geometry process is shown to have real potential. Measurement results show the feasibility of this approach to realising a general purpose Field Programmable Analog Array. Acknowledgements The authors would like to thank Europractice for IC fabrication.We are indebted to our colleagues John Doyle, Aidan Keady, Kevin Rowley and Sverre Lidholm for various reviews. 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