A High-Frequency Field-Programmable Analog Array (FPAA) Part 2: Applications

Analog Integrated Circuits and Signal Processing, 17, 157±169 (1998) # 1998 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. A High-Frequency Field-Programmable Analog Array (FPAA) Part 2: Applications EDMUND PIERZCHALA AND MAREK A. PERKOWSKI Department of Electrical Engineering, Portland State University, Portland, OR 97207-0751 [email protected], [email protected] Received August 2, 1996; Accepted November 10, 1997 Abstract. This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without signi®cantly limiting the class of circuits it can implement. Key Words: programmable circuit, analog signal processing, ®lter, phase-locked loop (PLL), multi-valued logic, fuzzy logic 1. Introduction for matrix operations in real time. Finally, Section 5 shows how FPAA can be used to implement multi- A companion paper [24] presents an FPAA archi- valued and fuzzy logic functions. tecture based on primarily local signal interconnections and a simple analog signal proces- 2. Linear Filters sing cell design. The purpose of this paper is to demonstrate that architecture limitations for the sake Fig. 1 shows an electrical schematic of an eighth- of high-frequency performance do not substantially order elliptic band-pass ®lter realized as an OTA-C1 limit the ¯exibility of the FPAA, as measured by the ladder. This schematic results from the so-called number of different classes of circuits that can be OTA-C simulation [25] of an RLC prototype based on implemented in it. the design presented in [29]. This is a voltage-mode A wide variety of circuits from different classes circuit, since each OTA takes a voltage signal as input, have been selected in order to demonstrate that a and although it produces a current signal, this current carefully designed FPAA architecture can accommo- is always turned into voltage, either by the integrating date them all. This is not to say that one FPAA circuit operation of a capacitor, or by another OTA with a would suf®ce for all such applications. Rather, a feedback connection, which is equivalent to a resistor. family of circuits based on a common architecture This is so because eventually each signal created in would be used. For instance, one design might be used this circuit is fed to some OTA (which can accept only to implement linear ®lters, adaptive ®lters, etc., voltage-mode signals at the input), or is connected to another one to implement matrix operations, arti®cial the output terminals, which also require a voltage- neural networks, yet another one for fuzzy logic. The mode signal. This circuit, and other voltage-mode selection of applications in this paper serves to circuits, can be realized in an equivalent current-mode demonstrate how a single architecture can be used form in the structure of the FPAA discussed here in [24]. across many application domains. The network of the ®lter seems to exhibit little The paper is organized as follows. Section 2 regularity, or locality of connections. Both can be presents linear ®lters. Section 3 shows examples of appreciated best when the graph of connections of nonlinear circuits, such as rank ®lter and phase-locked the ®lter is drawn (Fig. 2). Each pair of wires carries loop (PLL). Section 4 presents examples of circuits one differential signal, and it is represented as a single 158 E. Pierzchala and M. Perkowski Fig. 1. Eighth-order elliptic band-pass, fully-differential, ladder OTA-C ®lter. vertex of the graph. Each OTA is represented as a to comprise the entire ®lter, as shown in Fig. 3b. directed edge of the graph. The graph reveals Dashed lines indicate unused parts of the structure. regularity which leads to a number of different Instead of voltage-mode cells (OTA-C), current- realizations based on regular, locally-only intercon- mode cells of the FPAA can be used. The pattern of nected structures. One way of deriving a regular connections is independent of the mode of signals structure for the circuit is by grouping all edges (voltage or current), therefore the same arrangement coming into a given vertex as a single unit. For of cells (Fig. 3b) can be used to map the ®lter into the instance, OTAs 3a-c can be collected together as in FPAA. Each cell works in integrating mode, except Fig. 3a, forming a ``cell'' with four inputs and one cell 6, which realizes ``in®nite'' gain (60 dB in the output.2 Eleven such ``cells'' can be connected locally presented FPAA). Cells 1 and 10 realize lossy Fig. 2. Graph of connections of the ladder ®lter.  (FPAA) Part 2: Applications 159 can be easily mapped, too. Since every transfer function can be realized as a cascade of biquads, which can be then put one next to each other in the array, the device provides a way of realizing continuous-time ®lters by means of local signal interconnections only. 3. Nonlinear Signal Processing 3.1. Rank Filter A rank ®lter [17] can be implemented with only local interconnections. Fig. 5a shows a block diagram of a single cell of the rank ®lter, and Fig. 5b demonstrates its mapping into the structure of the FPAA. Two FPAA cells are necessary to implement one cell of the rank ®lter. The left-hand cell in Fig. 5b implements the left-hand part of the rank ®lter cell, the right-hand cellÐthe right-hand part. The reader should have no trouble identifying functions performed by each cell in Fig. 5b. A required number of such cells can be easily placed next to each other to realize the rank ®lter circuit. Fig. 6 shows simulated response of the rank ®lter. 3.2. PLL The multiplier in the cell can also work as a phase detector. A VCO can be implemented as shown in [24]. A suitable connection of the two blocks, plus a low-pass ®lter, implements a PLL (Figs. 7 and 8). Modulation, demodulation [7], and other functions performed by PLLs can be realized in the FPAA. Fig. 3. (a) A single ``cell'' of the ladder ®lter. (b) Locally-only interconnected topology of the ladder ®lter. 3.3. Other Nonlinear Applications integrators, all othersÐlossless. All the signal interconnections are local, directly between neigh- With the multiplier and the clipping circuits it is bors. Input and output terminals are on the sides of the possible to implement a variety of important nonlinear structure in Fig. 3b, and the circuit can be placed in the signal-processing blocks. The multiplier can be corner of the FPAA for easy routing of the input and directly used as a balanced modulator/demodulator output. Fig. 4 shows simulated frequency response of or controlled ampli®er. Full wave recti®cation can be the ®lter.3 implemented using nonlinear characteristics of the Most of the ladder ®lters of practical importance clipping blocks [24]. By combining the latter with can be mapped into the structure of the presented low-pass ®ltration and controlled gain one can device in a similar way. Second-order (biquad) ®lters implement automatic gain control (AGC). 160 E. Pierzchala and M. Perkowski Fig. 4. Frequency response of the ladder ®lter. 4. Matrix Operations Processor matrix is produced by a ``local'' group of cells along a diagonal global signal line. However, to distribute the 4.1. Tracking a Matrix Product input signals and to collect the result signals, global connections are necessary. Each diagonal output Fig. 9 shows the structure of a matrix product tracking line is used to sum elementary products aij bjk , circuit. It takes two time-varying matrices j ˆ 1; . . . ; n, comprising the product element cik . A…t† ˆ ‰aij …t†Š and B…t† ˆ ‰bij …t†Š, both 3  3, and It is instructive to note that the ``globality'' of creates their product C…t† ˆ A…t†
B…t† (a factor of 3 is connections results primarily from the need to required to account for the distribution of each input distribute input signals, and collect the output signals. signal to 3 cells; alternatively the gain of each cell Creation of each matrix product is done ``locally'' could be increased). Each element cij …t† of the product (although using global signal lines). What is important Fig. 5. Analog rank ®lter cell.  (FPAA) Part 2: Applications 161 Fig. 6. Analog rank ®lter operation. Initial conditions: 1.5, 2.0, 1.2, 0.0, 5.0 also, is that global lines are used here only at the 4.3. Tracking the Solution of a Linear ``terminals'' of the circuit, i.e. for the input and output Programming Problem signals. Global lines are not involved in transmitting internal signals. A linear programming problem can be stated as The circuit can be easily scaled for any rectangular follows. Given a set of constraints g…t† ˆ F
x…t† ˆ conformable matrices. ‰g1 …t†; . . . gm …t†Š0  0 (the inequality holds for every element of the vector; F is a rectangular matrix of constraints coef®cients, g is a vector representing individual constraints), minimize the objective func- tion r…x1 ; . . . ; xn † ˆ r
x ˆ r1 x1 ‡ . . . ‡ rn xn , where 4.2. Tracking the Solution of a System of r ˆ ‰r1 ; . . . ; rn Š. Application of the method of Linear Equations steepest descent leads to the system of equations x_ ˆ ÿm
r0 2a
A
diag…g†
U…g† where U…g† denotes Modifying slightly the matrix product tracking circuit, the step function, diag…g† denotes a diagonal matrix one can build a circuit for tracking the solution of a with elements of vector g on the main diagonal, and m system of linear equations. The solution x…t† of the system A…t†
x…t† ˆ b…t† can be found by solving a _ ‡ A…t†
x…t† ÿ b…t† ˆ 0 of differential system x…t† equations provided that matrix A…t† is always positive stable [9]. In many practical cases matrix A will be time-invariant, but it is instructive to see the solution of a more general problem, i.e. with a time-varying matrix A…t†. Fig. 10 shows a circuit solving a system of 3 linear equations with 3 unknowns x1 …t†; . . . ; x3 …t†. The global connections in this circuit carry internal feedback signals, although the distance traveled by these signals is small. This circuit can also be scaled easily to accom- modate larger systems of equations. Fig. 7. PLL implementation. 162 E. Pierzchala and M. Perkowski Fig. 8. PLL simulation results. and a are constants …m ! 0; a ! 1†, [9]. This system circuit, with only matrix F input, can be easily can be solved by the circuit shown in Fig. 11. In the derived. case of linear constraints, matrix A is identical to Fig. 12 shows results of functional simulation of matrix F, nevertheless a more general circuit not the circuit. assuming this equality is shown as an illustration of Like previous examples, this circuit can also be the versatility of the FPAA architecture. A simpli®ed scaled for problems of larger size. Fig. 9. Continuous-time matrix product tracking circuit.  (FPAA) Part 2: Applications 163 Fig. 10. Continuous-time circuit for tracking the solution of a system of linear algebraic equations. 5. Multi-Valued Logic (MVL) and Fuzzy-Logic analog memory (track-and-hold) by cutting off the Processor input signal to the integrator. The applications presented in this section require slightly more complex design of the control block of the FPAA cell than that presented in [24]. Fig. 13 5.1. Galois ®eld 22 operations shows the enhanced control scheme. The control block can select any of the analog blocks' outputs to Figs. 14a and 14b show the tables for addition and be compared with any of the input signals. The multiplication in a Galois ®eld of four elements. Each selection is made using a summer block, which of these operations can be realized by a single cell of operates as an analog multiplexer if only one of the the FPAA, assuming that only two of the cell's inputs weights is non-zero. A programmed constant pro- are used at a time. Addition can be realized as duced by the control block is available for selection in a  b ˆ f …a ‡ b† for a 6ˆ b (Figs. 14c and 14d), and such comparisons. The control block can adjust any of a  b ˆ 0 otherwise. The condition a ˆ b can be the analog parameters of the cell. The core of the detected by the control block. This requires program- control block is a simple digital circuit, programmed ming the weights of one of the input summers to from the outside of the cell. calculate the difference a ÿ b of the input signals, Another modi®cation in the control scheme is that selecting constant 0 for comparison in the control the ampli®er/integrator can be used as a short-term block, and controlling the weights of the other input Fig. 11. Continuous-time circuit for tracking the solution of a linear programming problem. 164 E. Pierzchala and M. Perkowski Fig. 12. Linear programming solver operation. Exact solution: (1.6, 4.05, 0.0), [9]. summer to set them to zero if a ˆ b is detected. orthogonal function over GF(22). Multiplied by a Instead of function f …x† (Fig. 14d) a smooth function constant from GF(22), this function is added to the f1 …x† (Fig. 14e) can be used. This function can be other orthogonal functions. All operations are in realized by adding two characteristics of the clipping GF(22). Fig. 15b shows an example realization of one blocks shown in Fig. 14f. The function of the form of the functions fi . More than one column of cells can shown in Fig. 14d can be realized by providing more be used for the realization of any of the fi 's if clipping blocks in the cell. necessary. Also, it may be convenient to make certain Multiplication a  b in the ®eld (Fig. 14b) can be input variables available on more than one horizontal realized as a  b ˆ ……a ‡ b ÿ 2† mod 3† ‡ 1 for line. An alternative approach, based on providing a 6ˆ 0 and b 6ˆ 0, and a  b ˆ 0 otherwise. The two literals on horizontal lines, or some functions of single conditions for a and b can be tested independently by variables which are convenient for the creation of the comparators in the control block, and upon at least literals, is also possible. In one such approach the one of them being true the input weights of the sum- mer would be turned down to 0. The mod 3 operation can be realized as shown in Figs. 14g and 14h. The control block performs the necessary logic operations. The realizations of GF(22) operations proposed above are similar to the ones presented in [30]. 5.2. Orthogonal Expansion Structures Having de®ned the addition and multiplication in GF(22), we can apply the combinational functions synthesis method based on orthogonal functions proposed in [20]. Fig. 15a shows a block diagram of a structure realizing an arbitrary function of input variables X1 ; X2 ; . . . ; Xm . Each column realizes one Fig. 13. Enhanced control scheme.  (FPAA) Part 2: Applications 165 Fig. 14. GF(22) operations. 166 E. Pierzchala and M. Perkowski operation. Instead of summing over GF(22), max operation is used. 5.4. Other Logics The structure of Fig. 15a can be used for realization of combinational functions with other methods. Such realizations, unlike the ones based on the orthogonal expansions, may not be unique in the presented structure, however due to the availability of addition, multiplication (in the conventional sense), and non- linear operations on signals, some combinational functions may have very ef®cient implementations. Also, the topology of mvl circuits mapped into the FPAA does not have to be constrained to the form shown in Fig. 15. Global vertical and diagonal signal lines can be used, if necessary, to achieve greater ¯exibility of the circuits topologies. Fig. 16 shows a Fig. 15. Orthogonal expansion structures. powers (i.e. multiple products in GF(22)) would be used to create polynomial expansions of mvl functions. 5.3. Post Logic The same structures shown in Fig. 15 can be used for the implementation of Post logic. Each cell can realize min and max operations [24], and literals of the form shown in [24]. Each function fi is realized as in Fig. 15b, except that the cells realize min or identity Fig. 16. Generalized Shannon expansion structure.  (FPAA) Part 2: Applications 167 Finally, the integrator block can be used as a memory element, enabling realization of sequential circuits. Since each cell can realize the identity function, and global connections are available, larger irregular structures, composed of combina- tional and sequential parts can be built in the presented FPAA structure. 5.5. Analog Logics Fuzzy logic and continuous logics (such as Lukasiewicz logic) [15,16] can be realized as well. As an example, let us consider an implementation of a fuzzy logic controller with correlation-product infer- ence [10]. A structure very similar to that of Fig. 15a, shown in Fig. 17a, is used to implement a controller with m input variables and n fuzzy inference rules. Fig. 17b shows details of each rule implementation. A fuzzy membership function is implemented as a trapezoidal transfer function of the kind shown in [24]. Activation values wi are multiplied by centroid values of the fuzzy rules consequents ci , and their areas Ii , yielding two sums computed on two horizontal global lines. The ®nal expression for the defuzzi®ed output variable vk is produced by a two- quadrant divider [9] shown in Fig. 17c. 6. Conclusions A number of circuits from different classes, linear and nonlinear continuous-time, as well as logic, have been shown to map to the structure of the FPAA with predominantly local signal interconnections. This effectively proves that connectivity limitation of the presented architecture does not seriously constrain the range of circuits that can be implemented in the FPAA. Local, and limited global signal interconnec- Fig. 17. Fuzzy controller. tions improve high-frequency operation. Continuous- time, switchless design of the analog processing cell structure for implementations based on generalized allows operation at the speeds near to the limits of a Shannon expansion of mvl functions [20]. Some input given semiconductor technology. variables need to be connected to more than one diagonal line. More general forms of the same kind are possible, based on operators other than 4 used Notes for separation, for instance even vs. odd parity, based 1. Operational transconductance ampli®er and capacitor. on matrix orthogonality [20], which is a general- 2. Vertices 1 and 10 additionally require a feedback connection in ization of the approach presented in [18] and [19] for one of the OTAs to realize lossy integration. All four inputs are two-valued functions. used only in cell 6. 168 E. Pierzchala and M. Perkowski 3. Functional simulation in Saber (Analogy, Inc.) was used. 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He studied pure 16. J. W. Mills, ``Lukasiewicz' Insect: The Role of Continuous- mathematics at the University of Warsaw and arti®cial Valued Logic in a Mobile Robot's Sensors, Control, and Locomotion.'' Proc. IEEE ISMVL, pp. 258±263. intelligence in Polish Academy of Sciences. He has 17. S. Paul, K. HuÈmper, and J. A. Nossek, ``A Simple Analog Rank been on the faculty at the Institute of Automatic Filter.'' Proc. IEEE ISCAS, pp. 121±124, San Diego, CA, 1992. Control, Warsaw University of Technology; 18. M. A. Perkowski, ``A Fundamental Theorem for EXOR Department of Electrical Engineering, University of Circuits.'' Proc. IFIP W.G. 10.5 Workshop on Applications of Minnesota; and is currently a Professor at the the Reed-Muller Expansion in Circuit Design, pp. 52±60, Hamburg, Germany, Sep 1993. Department of Electrical Engineering, Portland State 19. M. A. Perkowski, A. Sarabi, and F. R. Beyl, ``Universal XOR University. His interests are in design automation, Canonical Forms of Switching Functions.'' Proc. IFIP W.G. logic synthesis, machine learning and digital and  (FPAA) Part 2: Applications 169 analog ®eld-programmable gate arrays. He spent the summer of 1994 in Wright Laboratories, Wright- Patterson Air Force Base, working on application of boolean decomposition to machine learning and was a Visiting Professor at the university of Montpellier and Technical University of Eindhoven in 1996. He has consulted for several companies in these areas, and also worked for Cypress Semiconductor Corp. as a programmer and system designer of WARP, the ®rst VHDL compiler for EPLDs. Edmund Pierzchala received his M.S. degree in electronic engineering from Warsaw University of Technology, Warsaw, Poland. He worked as a research assistant and a senior research assistant in the Institute of Biocybernetics and Biomedical Engineering of Polish Academy of Sciences in Warsaw, Poland, and  the Nuclear Research Institute in Swierk, Poland. He is presently completing his Ph.D. degree at the Department of Electrical Engineering of Portland State University, where he also taught a number of undergraduate and graduate courses in EE. His research interests include programmable analog circuits, design automation, analog and mixed-signal circuits design, modeling, and simulation.