A High Performance Radiation-Hard Field Programmable Analog Array

A High Performance Radiation-Hard Field Programmable Analog Array Ji Luo, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang, Kuan-Jung Chung University of Maryland at College Park 2100 Marie Mount Hall, College Park, MD 20742 Phone: (301) 405-0357, fax: (301) 314-9601 Email: {jluo, joey, huanghu, kjchung}@eng.umd.edu, [email protected], Anthony L. Wilson Mission Research Corporation, 5001 Indian School Road NE, Albuquerque NM 87110 E-mail: [email protected] Abstract – While interest, availability and use of An important advantage of digital systems is their FPAAs have grown, FPAAs still have not achieved the immunity to noise. More importantly, the clearly same success as FPGAs in the digital domain. This defined hierarchical decomposition of digital systems results from several factors, including the lack of CAD with well-accepted performance measures makes tools, small circuit density, small bandwidth and layout digital ICs very ease of design over analog systems. dependent noise figures. These factors are all related Many CAD compatible digital system design to each other, making the design of a high methodologies have been developed, which lead to performance FPAA a multi-dimensional problem. A short design cycles and low cost. On the contrary, the critical reason behind these difficulties is the non-ideal analog design process still features a lot of intuitive programming technology, which contributes a large and manual design approaches. So there is a portion of parasitics into the sensitive analog system. substantial need for developing high performance, This paper presents a high performance, radiation reconfigurable analog ICs suitable for CAD hard Laser Field Programmable Analog Array methodologies in order to improve design efficiency. (LFPAA) using LaserLink’ s MakeLink TM technology. This has been the motivation for research in the area of Because of its extremely low resistance, negligible Field Programmable Analog Arrays [3]. parasitic capacitance and full compatibility with commercial CMOS process, MakeLink TM can fully In general, an FPAA is a monolithic collection of reduce these FPAA design concerns and offer a configurable analog building blocks (i.e., CABs), a breakthrough capability in analog array performance. programmable routing network used for passing The proposed LFPAA consists of a 4 x 4 array of signals between CABs, and a block of memory (for Configurable Analog Blocks (CABs) surrounded by SRAM based FPAA) storing configuration data [4]. abundant interconnect resources. There are 16 PAD Alternatively, the circuit topologies may be defined by groups around the chip, and 8 tracks per X/Y channel. other methods such as antifuse technologies. There are Each CAB has 4 input and 4 output pins with internal several FPAA designs in the academic literature and circuit operating in fully differential mode. With some commercial chips exist in the industry. However, appropriate programming, the LFPAA can provide an a general purpose FPAA suitable for high frequency accurate, low-cost and rapid-prototyping analog ASIC applications does not yet appear. This can be due to (1) solution. previous designs are based on bandwidth limited switched-capacitor techniques; (2) most FPAAs use 1. Introductions and Motivation MOS transistor or antifuse based programming switches; and (3) a lack of appropriate CAD tools. In High-density digital integrated circuits have dominated addition to introducing radiation softness, those the semiconductor market, but analog circuits as the switches can bring a large amount of parasitics (Fig. 1) interfacing blocks still play an essential role in today’s into the sensitive analog circuit thus severely complex, high performance systems. After all, the real degrading circuit performance. world is analog. Analog ICs find broad applications including analog filters, oscillators, modulators, pulse This paper presents a high performance, radiation hard shaping circuitry, A/D, D/A converters, Laser Field Programmable Analog Array using telecommunication systems, closed-loop control in LaserLink’s MakeLinkTM technology. Because of its industrial and integrated signal processing circuitry for extremely low resistance, negligible parasitic various sensors. “For every dollar spent on capacitance and full compatibility with commercial microprocessors, another $1.50 is required to create an CMOS processes, MakeLinkTM switches can offer a interface to the rest of the system”[1]. breakthrough capability in analog array performance. 0-7695-2093-6/04 $20.00  2004 IEEE  The organization of the paper is as follows: section 2 standard CMOS processes. Due to their nature, they compares currently available programming are unable to carry large current density and therefore technologies and introduces MakeLinkTM and its cannot be used in analog circuits (Table 1). Ideally we advantages. Section 3 describes the internal CAB wish the programmable switches had the properties of circuitry. Section 4 presents the LFPAA architecture a metal wire. MakeLinkTM is the most promising and the routing problem. At last, a brief conclusion is technology approaching this goal. given and some future work is proposed. The structure of laser MakeLinkTM is schematically C GS C GD illustrated in Fig. 3. [7] C SB C DB Cross-section B Laser beam SiO2/S i3N 4 Upper metal Fig. 1 Intrinsic capacitance of a MOSFET switch (M2) Cross- Section A Link sheet Link sheet 2. Programming Technologies Lower metal (M1) Cross-section A To date, FPAAs have been programmed with SRAM (a) (b ) and antifuse technologies. A SRAM-based FPAA is programmed by loading the configuration from an Fig. 3. Schematics of laser-induced vertical metal link, external source. Each switch (usually a MOS pass (a) top view and (b) cross section A-A' transistor or transmission gate) is controlled by a memory cell. All known FPAAs have used SRAM- The principle of link formation employs the contrast of based interconnect. The big advantage of SRAM material properties between the metal and the technology is its reprogrammability. The surrounding dielectrics SiO2 /Si3 N4 . The IR laser beam disadvantages are volatility, large area cost, high serial passing through the square hole of the upper metal resistance (>1KΩ), large capacitance associate with (M2) frame is impinged on the lower metal (M1) line MOSFET terminals, and low radiation tolerance. with negligible loss of energy in the covering dielectrics. The laser energy is absorbed on the surface of M1 to be resulting in a sharp metal temperature increase. Due to the extremely low thermal conductivity and light absorbency of the dielectrics, the dielectric temperature is not changed so much. In the mean time, metal expansion fractures the surrounding dielectrics along the stress concentration paths and molten metal fills in the crack. At an optimal (a) (b) laser energy and spot size, dielectric cracks can be controlled to initiate from the upper corners of the M1 line and terminate near the inside lower corners of the M2 frame without propagating to the outside of the structure or fracturing the top dielectric passivation. Fig. 4 [7] shows a FIB cross-section view of a vertical laser MakeLinkTM. (c) MakeLinkTM can also be formed laterally for even Fig. 2 (a) Actel’s PLICE antifuse; (b) Quicklogic’s Vialink smaller size. Advantages of Laser MakeLinkTM in the antifuse[6] (c) Actel’s M2M antifuse [5] ; application of programmable devices include: (1) extremely low electrical resistance per link: 2-3 orders Actel’s PLICE (programmable low-impedance circuit smaller than that of an Actel antifuse or a MOSFET element) antifuse, Metal-to-Metal antifuse and switch; (2) high reliability and tolerant to high current Quicklogic’s Vialink antifuse are also well-known density; (3) area efficient: it is a pure metallic link and programming technologies (Fig. 2). They have does not occupy any silicon area; (4) fully compatible relatively smaller resistance and occupy less area, but with commercial CMOS processes; and (5) radiation they still suffer from large parasitics and long-term hard: because no active devices are involved. A reliability issue. All of them are not fully compatible to 0-7695-2093-6/04 $20.00  2004 IEEE  comparison between MakeLinkTM with other antifuse A CAB is usually composed of a few programmable technologies is listed in Table 1. capacitor arrays (PCA), programmable resistor arrays (PRA) (Fig. 5) and an op-amp -like analog unit. This unit is the core and should be a universal analog function block, i.e. we wish easy configurability to implement as many analog functions as possible. The candidate circuitries include traditional op amp [10], operational transconductance amplifier (OTA) [11] and second-generation current conveyor [12]. In our LFPAA, a four-terminal floating nullor (FTFN) combining both voltage and current operation mode Fig. 4. FIB cross section of a vertical MakeLinkTM capabilities is adopted [13]. It has been demonstrated Actel Actel that any active circuit can be realized by FTFN [14]. A MakeLink QuickLogic M2M ONO fully balanced configuration is desired because 1) it Rnominal 0.5 - 5Ω ~25Ω 100-500Ω ~ 80Ω has large output swing; 2) circuit is less susceptible to Cnominal ~0 2.9 fF 7.7 fF 1fF common-mode/coupling noise; and 3) there are no Strong Weak Weak 1-D Weak even-order nonlinearities thus less harmonic distortion EM 1-D metal n+ [15]. The disadvantages are they require a CMFB 2-D metal 1-D metal Robustness silicide diffusion sheet filament filament filament circuit and consume more power. In our CAB design, a Radiation Radiation Radiation Radiation Radiation Fully Balanced Four Terminal Floating Nullor tolerance hard tolerant tolerant tolerant (FBFTFN) is used. CMOS Yes No No No Compatibility Geometry 4X 2.5X 2.5X 1X Size 1x 2x 4x 8x 16x 32x Current ~1mA ~ uA < mA ~ uA density Analog, digital and Digital Digital Applications Digital (a) Mixed-signal Circuit Circuit Circuit 1x 2x 4x 8x 20x 100x Circuit Leakage None 3 nA 10 nA - Current Table 1. Comparison of different antifuse technologies [5, 6, 8] (b) (0.35um CMOS process) PCA PCA PRA 3. Configurable Analog Block Circuitry PRA The functionality that an FPAA can implement is largely determined by the CAB configuration. A good CAB circuitry provides more flexibility and also helps FBFTF achieve high performance for the instantiated system. A major choice when designing an FPAA is whether PRA to operate in discrete-time or continuous-time. PCA PRA Discrete-time approaches, for example, switched- PCA capacitor technique, are well suited to digital control and do not require the use of on-chip tuning circuitry (c) Fig. 5 (a) PCA; (b) PRA; (c) Internal CAB configuration for VLSI implementations of programmable (Red lines are “BUSes”; : Laser MakeLinkTM) components. However, such sampled-data techniques require that input signals be band-limited to at least The FBFTFN (Fig. 6) features a highly symmetric two- one half of the sampling frequency and hence anti- stage op amp structure. Two same class AB rail-to-rail aliasing and reconstruction filters must be used. This (Vss + Vovn to VDD – Vovp) output stages provide requirement significantly limits the bandwidth of large output current driving capability with low discrete-time FPAA circuit implementations (usually standby power consumption. The two differential pairs less than 1/10 of the clock rate) [9]. Thus we prefer convert the two differential voltages into two currents continuous-time circuit design for the LFPAA. that are subtracted, converted into a voltage by the 0-7695-2093-6/04 $20.00  2004 IEEE  current source load and amplified. The low impedance Unlike the custom analog IC design, the routing Z terminal (due to compensation feedback) can be used resources in FPAAs are fixed and limited. All for voltage-mode signal operation. On the other hand, connections have to be completed within the horizontal the W terminal associated with high output impedance and vertical channels via Manhattan paths. The FPAA is suitable for providing output current signals. routing architecture not only affects routability but also has significant impact on the performance of the VDDA implemented circuit. Considering the FPAA circuit topology, we proposed an array-based architecture as VBP M5 W=53U MC5 W=53U MC6 W=53U M6 W=53U shown in Fig. 8. MC12 93 M19 M17 L=4U L=4U L=4U L=4U M7 M9 M2M 1C9 M CMFB2 CMFB2 W=66 0 60UW= 4.5UW= W=4.5U W=60U W=66 00 UU W= UU VOPI 40U L= 4U W= 4UL= 5UL= CMFB1 L=5U L= 4U L= 4 4U UL= 12 34 5 6 78 1 23 4 5 67 8 1 23 4 5 6 78 12 3 4 5 67 8 VONI L= M= M= Pad Pad Pad Pad VWN (1,5) (2,5) (3,5) (4,5) VON VONI VOPI VOP VWP VON VOP CC1N I_2 = 20U W = WL= L= 10U R= RSN RSN R= RC1N I_1 = 100U WL== WL= 100U C= C= CMM CMM 20U 10U M20 M1 M2 M3 M4 M10 M22 C onnection 121U 121U C onnec tion C onnec tion M24 C onnect io n Sw itch Switch C hanx(1,4) Switc h B ox VYN VYP VXP VXN VDDA 24UW= W=40U 40UW= W=40U 40UW M15 W=24U W=24U Box Box = Box 24UW= 4UL= L=10U 10UL= L= 10U 10UL= L=4U L= 4U Box Box 4UL= Box M= M= M= M= M = M= M= M= W=53U L= 4U 12 3 4 56 7 8 1 2 3 4 56 7 8 M16 Pad Connect ion CAB C onnection C AB Connection CAB Connec tion CAB C onnection Pad M8 VBN W=4.5U (0,4) B ox (1,4) Box (2,4) Box (3,4) Box (4, 4) Box (5,4) M18 M11 M12 L=5U W=4.5U M= L=5U VSB 4.5UW= W=30U W=30U ISB M= 5UL= L=2U L=2U Connecti on Connec tion Connec tion C onnection M= M= M= 10U Switch C hanx(1,3) Switc h Box B ox Box Box Box Box VSSA 1 2 3 4 5 67 8 1 2 34 5 6 78 Pad Connection CAB C onnection C AB Connec tion CAB Connect io n CAB Connec tion Pad (0,3) Box (1,3) Box (2,3) Box (3,3) B ox (4, 3) Box (5,3) Fig. 6 A CMOS implementation of FBFTFN Connec tion C onnection Connec tion C onnection Swit ch Switch Switch Box Box C hanx(1,2) B ox B ox Box Box Box The outputs of the circuit can be expressed as: [( ) ( )] 12 3 4 56 78 1 23 4 5 67 8 V op = −V on = Ao V yp − V yn − V xp − V xn Pad (0,2) Connection Box CAB (1,2) C onnection Box C AB (2,2) Connec tion Box CAB (3,2) Connect io n B ox CAB (4, 2) Connec tion Pad Box (5,2) with small signal open-loop gain: )( )(r C onnec tion C onnec tion C onnec tion C onnec tion ( ) Swit ch Switch Ao = g rds1 // rds3 // rds5 // rdsc1 ⋅ g + g Chanx(1,1) Box Box Box Box Box Box ds9 rds10 // m1 m9 m10 12 3 4 56 78 1 2 3 4 56 7 8 Combined with the PCAs and PRAs in the CAB, Pad (0,1) Connecti on Box CAB (1,1) C onnection Box C AB (2,1) Connec tion Box CAB (3,1) Connection Box CAB (4, 1) Connec tion Pad Box (5,1) FBFTFN can be configured to implement numerous C onnec tion C onnecti on C onnecti on Connect ion Sw itch Switc h Switc h Box analog functions. Fig. 7 shows two meaningful B ox B ox Box Chanx(1, 0) Box Box Box examples: (1) a fully balanced non-inverting voltage Chany(0, 1) C hany (1, 1) Chany(2,1) Chany(3,1) Chany(4,1) amplifier; (2) a Sallen-Key Bandpass Filter [13]. 12 3 4 56 7 8 12 34 5 6 7 8 12 3 4 56 78 1 2 34 5 67 8 VCM Pad Pad Pad Pad (1,0) (2, 0) (3,0) (4, 0) 100 100 R1 R2 Fig. 8 LFPAA Architecture VIP VXP VOP Vi VXN X Z VON Vo The LFPAA architecture contains a 4X4 CAB array. VIN VYP Y W VWP To accommodate for fully differential circuit VYN VWN operation, each CAB has 8 pins, 4 input pins on the left of the CAB and 4 output pins on the right of the CAB, VCM Each CAB is surrounded by 4 connection boxes. There 100 100 R3 R4 (a) are 8 tracks per horizontal (X)/vertical (Y) channel. 25 VCM switch boxes are uniformly distributed at the vertical and horizontal channel intersections. It has 16 I/O PAD R1 R2 100 100 groups (some reserved PADs are not shown in the 2PF C2 VIP figure), with 8 PADs per group. The left column and R7 2PF R5 C1 100 VXP VOP X Z VXN VON Vo bottom row PADs are for input only; the top row and 100 Vi VCM VYP VWP Y W right column PADs are for output only. This VYN VWN 100 R8 VIN 2PF 100 R6 C3 “prototype” LFPAA architecture does not have 2PF C4 VCM segmentation but it can easily be modified, adding R3 R4 100 100 more CABs, PADs, tracks and/or segmentation scheme (b) to develop into a more versatile structure. Fig 7 (a) A fully balanced non-inverting amplifier (b) A Sallen-Key bandpass filter 4.2 LFPAA Router 4. LFPAA Architecture and Router Similar to FPGA, implementating an analog circuit on 4.1 Architecture FPAA requires appropriate programming of thousands of switches. Obviously this has to be done with the aid 0-7695-2093-6/04 $20.00  2004 IEEE  of a set of supporting CAD tools. Fig. 9 shows a l Direct connections between CAB pins are not simplified FPAA design flow. The end user only allowed; direct connections between PADs and CAB describes a targeted application at a high level of pins are not allowed. abstraction, for analog array, typically using a l Dogleg is not allowed, i.e., CAB pin cannot be acted schematic entry with the IPmodule/CAM (configurable as intermediate vertex to route a net. analog module) library provided by the FPAA manufacturer. Then CAD tools convert this high-level Based on above definition, the LFPAA architecture is description into a programming file, which specifies converted into a highly detailed routing resource graph the state of the switches in the FPAA. (RRG), which contains all the connection and constraints information, by a RRG generator. Then the Circuit router performs routing for an input netlist on RRG. Description The goal of routing is not only to complete all the required connections without congestion, but also to Optimizing & Mapping Circuit into CABs satisfy a set of performance constraints. In digital based on manufacturer provided IPmodule Libs domain, the performance constraints are induced by RC delay which can be counted efficiently with the timing term in cost function, while the performance Placement constraints (tolerable variation of gain, bandwidth, noise etc.) imposed on analog array are too abstract for the routing tools to handle directly, thus they must be Routing converted to a set of routing constraints, or, interconnect parasitic constraints. Once the routing constraints are met, the performance constraints of the Output Routed analog circuit should also be satisfied. The parasitics Circuit that are to be controlled during routing are metal wire resistance, switch resistance, metal wire to ground and Fig. 9 LFPAA Design Flow metal-to-metal capacitance. Among them, parasitic capacitance is the major concern. Those parasitic Due to the inherent nature of analog system, the effects are classified into bounding constraints and technology mapping phase and placement phase might matching constraints and incorporated into a cost have to be done manually and semi-manually. Thus function. Cost function is used as the criteria to routing plays an essential role in FPAA design determine how the connections are made. automation. Our LFPAA router is based on the Pathfinder For LFPAA, the coordinate system is defined in Fig. 7, Negotiated Routing Algorithm [16, 17, 18]. We have from (0, 0) to (5, 5). The four corner positions, (0, 0), finished a routability-driven router for LFPAA. (0, 5), (5, 0), (5, 5), are blank areas. Each X or Y Although it’s called routability-driven, the router in directed channel belongs to the pad or CAB right fact not only resolves the congestion but also tries to below it, or on the left to it, having the same find the “shortest path”. In other words, the coordinates. The legal routing connections are: accumulated parasitics (especially the loading capacitance and serial resistance) are automatically l LHS pads can connect to all the tracks in channel y kept to a near minimum value, along with the wave (0, 1); RHS pads can connect to all the tracks in expansion process. Also, because of the extremely channel y (4, 1). small parasitics associated with MakeLinkTM switch, l Bottom row pads can connect to all the tracks in this router is sufficient for this relatively small-scaled channel x (1, 0); top row pads can connect to all the FPAA. tracks in channel x (1, 4). l Input CAB pins can connect to tracks in the channels 5. Conclusion immediately on the left, top and bottom of the CAB; output CAB pins can connect to tracks in the While interest in, availability and use of FPAAs has channels immediately on the right, top and bottom of grown, FPAAs still cannot achieve the same success as the CAB. FPGAs have in digital domain. This is the result of l Tracks in the horizontal channel can connect to several factors. A critical reason behind these tracks in vertical channel if a switch is available at difficulties is the non-ideal programming technology. the intersection. This paper presents a high performance, radiation hard 0-7695-2093-6/04 $20.00  2004 IEEE  Laser Field Programmable Analog Array using [4] E. Lee, “Field-Programmable Analog Arrays Based on LaserLink’s MakeLinkTM technology. Compared to MOS Transconductors”, Ph.D. dissertation, University of the traditional SRAM based FPAA, LFPAA has the Toronto, 1995 advantages of flexible circuit topology, area efficiency, [5] Actel’s Antifuse Quality and Reliability Guide, radiation hardness and extremely small parasitics. http://www.actel.com Therefore it provides a promising high performance, low cost and fast-prototyping analog ASIC solution. [6] Michael John, Sebastian Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997 We will further investigate the analog performance constraints on analog circuits and their conversion to [7] J. B. Berstein, W. Zhang and Carl H. Nicholas, “Laser routing constraints. Also more work is required to Formed Metallic Connections”, IEEE Trans. on Components, develop large-scale FPAA architectures and function- Packaging, and Manufacturing Technology, Part B., vol. 21, No. 2, May 1998 rich analog IPModule libraries. RT(neti): a linked list storing current routing of net i [8] http://www.quicklogic.com Sort the nets according to their classifications [9] V. Gaudet, “Field-Programmable Analog Arrays: An while (overuse exists && max iteration not exceeded) { Introductory Survey”, University of Toronto, for (all net) { rip-up existing RT(neti) and update p(n); http://www.ee.ualberta.ca/~vgaudet/fpaa/index.html init RT to source; [10] R. Edwards, K. Strohbehn etc., “A Field-Programmable for (all sinks of net i) { Mixed-Signal Array Architecture Using Antifuse Initialize PQ to RT; Interconnects”, ISCAS 2000, May 28-31, 2000 while {no sink found) { dequeue PQ; [11] B. Pankiewicz, M. Wojcikowski etc., “A Field for (all fanout vertices n of node m){ Programmable Array for CMOS Continuous-Time OTA-C If (n not a pin/pad & un-reached) Filter Applications”, IEEE J. of Solid-State Circuits, Vol. 37, add n to PQ & update pathcost(n); No. 2, Feb. 2002 else { (n is a sink) [12] V. Gaudet and G. Gulak, “CMOS Implementation of a add it to a temp sink list; Current Conveyor-Based Field-Programmable Analog } Array”, University of Toronto } if ( more than one sinks found) { [13] H. Alzaher and M. Ismail, “A CMOS Fully Balanced add those sinks and their parents to RT; Four-Terminal Floating Nullor”, IEEE Trans. On circuit & update p(n) only if n is not contained in RT; Systems I: Fundamentals Theory & Applications. Vol. 49, } April 2002 } for (all vertices in path){ [14] H. Carlin, “Singular network element,”IRE Trans. update p(n) only if n is not contained in RT; Circuit Theory, vol. CT-11, pp. 67–72, Mar. 1964. add n to RT(i); } [15] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and } Design of Analog Integrated Circuits, John Wilet & Sons, Update h(n) for all n; } Inc., 2000 [16] L. McMurchie and C. Ebeling, "PathFinder: A Fig. 10 LFPAA Routing Algorithm Negotiation-Based Performance-Driven Router for FPGAs", Proceedings of the 1995 ACM 3rd, pp. 111-117, February References 1995. [1] http://www.us.design-reuse.com/news/news887.html [17] C. Ebeling, L. McMurchie, Scott A. Hauck, and Steven Burns, “Placement and Routing Tools for the Triptych”, [2] M. Ismail and S. Bibyk, “CAD Latches Onto New IEEE Trans. on VLSI Systems, Vol. 3, No. 4, Dec. 1995 Techniques for Analog ICs”, IEEE Circuits and Devices Magazine, Sep. 1991, pp. 11-17 [18] V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic [3] D. R. D’Mello and P. G. Gulak, “Design Approaches to Publishers, 1999 Field-Programmable Analog Integrated Circuits”, Analog Integrated Circuits and Signal Processing, 17, 7-34, 1998 0-7695-2093-6/04 $20.00  2004 IEEE