A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design

Analog Integrated Circuits and Signal Processing, 17, 143±156 (1998) # 1998 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design EDMUND PIERZCHALA AND MAREK A. PERKOWSKI Department of Electrical Engineering, Portland State University, Portland, OR 97207-0751 [email protected], [email protected] Received August 2, 1996; Accepted November 10, 1997 Abstract. The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology. Key Words: programmable circuit, ®eld-programmable analog array (FPAA), current-mode circuit, analog signal processing 1. Introduction Field-Programmable Gate Arrays (FPGAs) have found many applications since they were proposed about a decade ago. FPGAs dramatically shorten design time and allow instantaneous modi®cations and corrections. Their applications range from simple ``glue logic'' functions to complex, dynamically recon®gurable systems. The success of FPGAs is undoubtedly one of motivating factors in the FPAA research. With the current trend which favors digital techniques, analog circuits seem to be left to perform interface functions (such as A/D, D/A converters, anti-alias and smoothing ®lters) or work where digital circuits did not yet achieve satis®able performance (e.g. highfrequency applications). It seems that analog circuits, as more capricious and harder to design, should yield to digital ones. In fact, the picture is not so simple, and the ``digital revolution'' relies heavily on progress in analog circuits in each of its victories [21]. The design complexity of analog front-end and back-end circuits may exceed the complexity of the digital signal processing circuit they work with. As an example one can consider processing of video signals, or any other signals of suf®ciently high bandwidth. In such applications, the sampling frequency is often chosen to be close to the Nyquist frequency, which poses stringent requirements on the anti-aliasing ®lter design, leading to high-order ®lters. Moreover, if high linearity and low noise are desired, one must not only assure high quality of data converters, but also the analog front and back ends. All in all, the analog part of the entire system may easily become as or even more complex than the digital one. At that point one may ask if the implementation of the entire signal processing channel as an analog one would not be a better choice [19]. Analog circuits can perform important signalprocessing functions, such as multiplication and integration, faster, using less power, and on less silicon real estate than their digital counterparts. For these and other reasons, mentioned earlier, analog circuits are rather unlikely to be eliminated entirely from the electronic design, nor to be reduced to some simple, residual form in a predominantly digital design world. Therefore, it is of utmost importance to ease the analog design process. One of the reasons analog design is so much more complex than digital, is that the number of design options and trade-offs it involves is much larger than in the digital realm. Also, analog designers have signi®cantly less freedom in ignoring low-level circuit interaction of high-level blocks in a hierarchical 144 E. Pierzchala and M. Perkowski design. A carefully designed multi-function analog circuit such as an FPAA can successfully address these issues, delivering the full potential of analog circuits to a designer, who may or may not be an analog expert. A number of analog programmable circuits have been reported in the literature. Due to the use of switched capacitor techniques [2], subthreshold MOS operation [10,11], or extensive use of global signal interconnections [12,13], these devices have limited bandwidth and are generally not suitable for highfrequency operation. An extensive review of prior work in FPAAs is presented in [1]. This paper presents results of research aimed at developing programmable analog circuits for highfrequency applications, the ®rst attempt to build such circuits reported in the literature. Preliminary results were presented in [16]. Given that the semiconductor technologies advance rapidly, ``high frequency'' in this paper is not de®ned in terms of numbers, but rather as an attribute of an electronic circuit to operate at, or near to (e.g. within one order of magnitude), the maximum signal frequency supported by a given technology. Using this convention, a 1.2 mm CMOS circuit operating at 30 MHz will classify as a ``highfrequency'' one, while a 100 MHz circuit realized in a 27 GHz bipolar process would rather be considered a low-frequency one. The paper is organized as follows. Section 2 addresses the question of architecture (i.e. pattern of interconnections) most suitable for high-frequency operation. Section 3 describes the design of the analog circuits of a single cell of the FPAA. Section 4 presents the design of the digital control circuit of a single cell. Finally, Section 5 contains conclusions. 2. 2.1. Architecture Background It is well known that the high-frequency performance of an analog circuit built in any speci®c technology depends on the particular circuit techniques used, and the layout. In this section the focus is on these aspects of the design which determine the geometric properties of the programmable device and lead to a particular layout. An FPAA consists of individual signal-processing blocks (cells) and signal interconnections between them. Layout techniques used for traditional (i.e. nonprogrammable) circuits are insuf®cient for programmable devices, as the latter must have redundant interconnections for the sake of programmability. Likewise, most layout (or architectural) techniques developed for digital programmable devices (such as FPGAs or PLDs) are unsuitable for high-frequency FPAAs, because analog circuits cannot tolerate delays, phase errors, and cross talk between signals that digital circuits can. An architecture, or topology, of a programmable device, comprises two elements: the design and the resulting functionality of a single cell, and the pattern of interconnections between cells. What is considered a single cell, is to some degree an arbitrary decision. A cell in one programmable device might be considered a collection of cells, or a ``macro cell,'' in another, giving rise to a hierarchical architecture. It is convenient to think of a single cell as a unit capable of performing some elementary signal processing functions, such as integration or ampli®cation, which can be combined according to the topology of the programmable device in order to realize desired circuit or system function. For instance, if one is interested in realizing linear ®lters, a cell capable of implementing an arbitrary second-order function seems like a reasonable choice. It is assumed in this paper that the cell is autonomous, i.e. it is capable of operation on its own, without the presence of any other cells. Thus a single transistor could not be considered a cell, even though by a suitable interconnection of transistors one can realize a host of circuits. The signal interconnections must connect these cells that need to be connected, while at the same time they must provide adequate isolation between those cells that need to remain disconnected. A ( fully) programmable circuit or device is one that allows changing of its con®guration (pattern of interconnections between cells) as well as functions and parameters of individual cells. A tunable circuit is one that allows programming of parameters only. Fully programmable circuits provide more ¯exibility in programming than tunable ones. For instance, a tunable ®lter allows changing certain of its parameters, such as cut-off frequency or quality factor, whereas a fully programmable one provides the same and the means of implementing different passband con®gurations (band-pass, low-pass, etc.), different (FPAA) Part 1: Design orders, and different approximations (e.g. Chebyshev, elliptic, etc.). 2.2. High-Frequency Architectures There are two architecture schemes diametrically opposed to each other. One is based on providing programmable connections between every pair of cells in the circuit. This approach favors ¯exibility, but also leads to excessively long signal interconnections, which introduce phase errors and cross talk problems detrimental to the circuit operation at high frequencies. The second scheme is based on restricting the interconnection pattern in favor of better highfrequency performance. This paper reports results of research based on the latter approach. Intuitively, restricting the pattern of interconnections should decrease the ¯exibility of the programmable device, measured as the number of different circuit topologies that can be implemented. It turns out however, that this intuition is not necessarily correct. A number of important classes of circuits can be implemented in an FPAA of carefully restricted topology. It is possible because most ``real-world'' circuits have restricted connectivity between components; very rarely is it necessary to connect most (or all) components with most (or all) other components. 2.3. 145 interconnection pattern shown in Fig. 1b, superimposed on that of Fig. 1a but shown separately for clarity, further enables implementation of other circuits, such as matrix operations circuits, equation solvers, programming problem solvers, multi-valued logic and fuzzy logic circuits [17]. 2.4. The Cell Functions and the Control Block This section presents the second element comprising an architecture, namely the functionality of an individual cell. Circuit aspects of the cell design are discussed in Section 3. Locally-Connected vs. Globally-Connected Topology Let us consider a simple pattern of interconnections shown in Fig. 1a. Each cell (represented by a dot in the ®gure) can receive output signals from the four nearest neighbors, and can send its own output signal to the same neighbors. Given adequate functionality of each cell, this restricted topology allows implementation of various important classes of circuits [17], such as ladder and cascade linear ®lters, rank ®lters, modulators, demodulators, PLLs, automatic gain control (AGC). Although a wide variety of applications can be realized in this locally-only interconnected architecture, some circuits require global connections. An Fig. 1. Signal interconnections of the FPAA: (a) local, (b) global. 146 E. Pierzchala and M. Perkowski In the presented FPAA all cells are identical, but cells of different functionality could be used as well. Fig. 2 shows a functional block diagram of an individual cell. The functions and parameters of the cell are determined by the control block, presented in Section 4. The cell works in one of the two modes: passivecontrol mode and active-control mode. In the passivecontrol mode only the analog blocks of the cell perform signal processing functions. The control circuit determines the parameters and con®guration of the analog blocks of the cell, but is otherwise not involved in the signal processing. In the active-control mode, the control circuitry additionally takes part is some signal processing functions. Two important nonlinear circuits are implemented in the active-control mode (see Section 4): min/max-follower and controlled waveform generator (VCO, voltage-controlled oscillator). 2.4.1. Passive-Control Mode. As shown in Fig. 2, analog input signals are connected to two summers. When at least one weight wi is non-zero, a summer implements weighted sum (1). P s
en
w
x t† 1† y t† ˆ ks
i i Pi i i i wi When all the weights wi are zero, the output y t† is also zero. The summers' weights wi are positive or zero, and are programmed independently, i.e. each weight wi for one summer can be different from any other weight wj for the same or the other summer. Each signal can be summed with positive or negative sign, si . Enable bits, eni , allow connecting and Fig. 2. Functional block diagram of the programmable cell. disconnecting a given signal from the summer input, which is a means of programming the interconnection pattern between the cells. Signs and enable bits are programmed independently. The denominator of (1) provides scaling of the output signal dependent on the combined weights. Such scaling is necessary to ensure proper dynamic range of the output signal. The overall gain of each summer is determined by its respective ks . The output signals of the two summers are connected to the multiplier (2). y t† ˆ x1 t†
x2 t† 2† The multiplier also performs important signal processing functions, such as phase detection, balanced modulation and demodulation [7]. If no multiplication is needed, a constant signal, symbolically represented as ``1'' is connected to the second input, instead of the second summer's output. The multiplier output is connected to the ampli®er/ integrator, which performs one of the three functions: ampli®er, lossless integrator, or lossy integrator (3±5). y s† ˆ ki x s† 3† y s† ˆ ki x s† s 4† y s† ˆ ki x s† s‡a 5† The output signal of the ampli®er/integrator is connected to a pair of limiting (clipping) blocks, each of which realizes the basic DC transfer function represented by (6), also illustrated in Fig. 3a. 8 < ÿa if x < ÿa yˆ x if ÿ a  x  a 6† : a if x  a This basic clipping characteristic of each block can be electronically shifted along the vertical and horizontal axis, and the slope of the linear part can be changed, as shown in Fig. 3b. By combining (adding) two clipping characteristics one can obtain a variety of nonlinear DC transfer functions. Some examples are shown in Fig. 3c±h. Such important functions as abs (full-wave recti®er, Fig. 3e), sign (Fig. 3g, shifted along the horizontal axis) and ``fuzzy-membership'' (Fig. 3c, d) are easily implemented. Output signals from the clipping blocks are added together and mirrored for distribution to the neigh- (FPAA) Part 1: Design 147 Fig. 3. Selected DC transfer characteristics of a single cell. boring cells and global signal lines (the signals are in current mode). There is also a ``feedback'' connection inside the cell, which makes the cell output signal available at the input. Some applications of the FPAA require such a connection (see the rank ®lter example [17]). Table 1 summarizes the most important functions realized by a single cell, including ones in the activecontrol-mode. 2.4.2. Active-Control Mode. In the active-control mode, the analog processing part of the cell and the 148 E. Pierzchala and M. Perkowski Table 1. Selected functions of a single cell. P P j w j xj i wi xi P
P 1. y ˆ k
j wj i wi P w x 2. y ˆ k
Pi i i i wi 3. y ˆ kxi xj 4. y ˆ kx2i 5. y ˆ k
min x1 ; . . . ; xn † 6. y ˆ k
max x1 ; . . . ; xn † 1 7. y ˆ k
y1ÿ6
s‡a 8. y ˆ a sign y1ÿ7 † 9. y ˆ b U y1ÿ7 †; U is the step function 10. y ˆ kjy1ÿ7 j 11. y ˆ xi (identity) control block form a feedback system which operates in a way similar to that of a data-path-and-control arrangement found in digital systems. A very complex scheme of this kind would be dif®cult to implement and it might be slow. In the present arrangement each of the input signals (and the output signal) can be compared against the output of the ampli®er/ integrator in order to control the weights and signs of the ®rst summer. The details of the control block implementation are presented in Section 4. 3. Analog Building Blocks Fig. 4 demonstrates the basic analog building block of the cell [3,5,7,8]. In its simplest form the circuit contains only transistors Q1 ±Q4 and the tail current source IB‡ . Current sources IA represent the circuit's input signals. The circuit is fully differential, i.e. both input and output signals are represented by differences of currents in two wires. The sum of currents IA‡ ˆ IA 1 ‡ x† is the positive ``half'' of the input signal, and IAÿ ˆ IA 1 ÿ x†, is its negative ``half.'' The input signal is then IA‡ ÿ IAÿ ˆ IA 1 ‡ x† ÿ IA 1 ÿ x† ˆ 2IA x; x is called modulation index. Likewise, the ‡ ÿ ÿ Iout ˆ IB 1 ‡ y† output signal is the difference Iout ÿ IB 1 ÿ y† ˆ 2IB y. Current gain is determined by the ratio IB =IA and in practice can be tuned over several decades from a fraction of unity to about 10.1 Since there are very little voltage swings (only several hundred mV in the entire linear range of operation), the circuit has very high gain-bandwidth product, close to the fT of the transistors [3]. In the 8 GHz bipolar process used for the implementation of the core of the cell [16] the simulated gain-bandwidth product of this circuit exceeds 6 GHz.2 The DC transfer characteristic of the circuit, shown in Fig. 3a for a gain of 1, exhibits sharp overload points and excellent linearity within entire linear range. The width of the linear part of the characteristic and its slope are determined by the bias currents IA and IB . By adding (subtracting) currents on the input and on the output of the circuit (by additional programmed current sources) one can change the location of the zero of the characteristic, as well as the two clipping (saturation) levels (Fig. 3b). This circuit has many variations; all the remaining analog blocks of the cell either contain one of those variations directly, or are related to one. For instance, including transistors Q5 and Q6 (Fig. 4) allows inverting the signal (negative weight). If another pair of inputs is connected in place of the tail current sources IB‡ and IBÿ , the circuit becomes a Gilbert multiplier core [4]. More transistor pairs can be added (dashed line) to obtain several outputs, such as it is required to implement a differential current mirror. Each output can be independently tuned by means of changing its tail current. 3.1. Fig. 4. Basic analog building block of the cell. Summer Fig. 5 shows the schematic of a summer with independent tuning of input weights. Additional summation (without independent tuning) can be realized by connecting several signals to each input. (FPAA) Part 1: Design 149 A current normalizing circuit [5] is used to scale the summer tail currents in order to implement (1); see Fig. 6. Currents I1 ±I9 represent ``raw,'' i.e. unscaled, weights. The normalizing circuit produces scaled weight currents Iw1 ±Iw9 , whose sum always equals Iw , and whose ratios equal the ratios of the ``raw'' weight currents I1 ±I9 . Thus by programming the values of I1 ±I9 the weights wi of a summer are determined independently of the summer overall gain ks , while programming the value of Iw determines ks . The latter can be programmed in the range ÿ 40 dB ± ‡ 40 dB. This arrangement leaves the scaling circuitry out of the signal path of the cell. Details of the digital control of the summer are discussed in Section 4.2. 3.2. Multiplier The multiplier [4] is obtained from the basic circuit in Fig. 4 by replacing the two tail current sources IB‡ and IBÿ with signal inputs. Instead of the second summer output, a constant can be connected to the second input of the multiplier. The sign of the multiplier output is also programmed. Fig. 5. Summer. Fig. 6. Controlling the weights of the ®rst summer. 150 3.3. E. Pierzchala and M. Perkowski Ampli®er/Integrator Integration is one of the basic linear signal processing operations, and as such it should be included in a programmable analog device. In many FPAA applications, only some cells will perform integration, therefore the FPAA cell should provide means for turning integration off. It is easy to implement an ampli®er/integrator if some kind of electronic switches, such as MOS passtransistors, are available. Switches can be used to program the unity-gain frequency (by connecting or disconnecting a number of capacitors), or to turn the integration on and off. There are at least two problems with switches: (1) they are not easy to implement in some technologies, such as bipolar, (2) they introduce parasitic timeconstants which can severely degrade the frequency response of the circuit. A successful implementation of a switchless current-mode Miller ampli®er/integrator in a bipolar transistor-array technology has been demonstrated [16]. The input buffer k1 (Fig. 7a) comprising transistors Q11 ±Q16 (Fig. 8) is based on a current ampli®er of Fig. 4. Only one of the buffer outputs is active at a time, Fig. 7. Current-mode ampli®er/integrator: (a) integrator, (b) ampli®er. depending on which one of the bias sources IE11 , IE12 is on. In the integrating mode (Fig. 7a) sources IE12 , IC15 and IC16 are off. The ®rst output of the buffer which is connected to the simpli®ed gm cell (Darlington pairs Fig. 8. Simpli®ed schematic of the ampli®er/integrator. (FPAA) Part 1: Design Q25 ±Q26 , Q27 ±Q28 and to the capacitors C ) is active. A two-stage current ampli®er k2 (Q21 ±Q24 , Q31 ±Q32 , Q35 ±Q36 ) follows gm . Q35 , Q36 with active loads and emitter follower Q37 , Q38 provide voltage output. With IE31 off, differential output current is IC33 , IC34 minus collector currents of Q37 , Q38 . With capacitors C this is a classic Miller integrator in differential form, with an additional current output. The gain (unity-gain frequency) can be changed by changing the bias of the input buffer. In the amplifying mode (Fig. 7b), IE11 is off, the gm cell receives no signal, and IE32 , IE33 are off. Buffer k1 feeds its output current directly to the ampli®er k2 (from collectors of Q15 , Q16 ). The gain of this cascade can be turned up to 60 dB by changing the bias [3,5]. Differential output current is IC33 , IC34 minus collector currents of Q33 , Q34 . Figs. 9 and 10 demonstrate the frequency response in the integrating and amplifying modes, respectively. Adjustment of IE33 allows ®ne tuning of the phase response in the vicinity of ÿ 90 . Two common-mode feedback circuits (not shown), assure proper voltage levels at the input of the gm cell, and the collectors of Q35 and Q36 . Voltage at the emitters of Q21 and Q22 , proportional to the commonmode voltage at the gm input, is compared to a 151 reference level. Correction signals are sent to the bias sources IE11 , IC13 , IC14 . A similar scheme is used for Q35 and Q36 . Changing voltage gain within the integrator results in shifting the useful range of frequencies along the frequency axis. 3.4. Clipping Circuits Each of the clipping blocks shown in Fig. 2 is realized as a circuit of Fig. 4. Additional current sources are connected on the input and the output to enable shifting of the DC transfer characteristic as required. With two blocks one can achieve many nonlinear characteristics, some of them shown in Fig. 3. ki , zi , ai , bi are the slope, zero, lower saturation level and upper saturation level, respectively (see Fig. 3b). 4. Digital Programming and Control The characteristics of a particular circuit implemented in the FPAA are determined by the control circuitry, which in general has a twofold purpose: Fig. 9. Integrating mode frequency response. 152 E. Pierzchala and M. Perkowski Fig. 10. Amplifying mode frequency response. 1. setting up required functions and parameters of each cell, and 2. realizing the active-control functions of the cell (see Section 2.4.2). In [15] a general control scheme for these purposes has been proposed. A modi®ed control scheme, suitable for implementation in a high-density bipolar technology,3 is presented in this paper. Programming an FPAA requires setting up a number of (i) analog parameters and (ii) binary values, such as the signs of the analog parameters, and the enable bits. 4.1. Parametric Programming The lack of EEPROM cells and MOS devices in bipolar technologies makes it dif®cult to design an analog memory cell. A simple analog memory cell and a current source, using JFET devices (available in some bipolar technologies) has been proposed in [20]. The cell holds an analog value for about 200 ms with less than 1% loss, using a capacitor of 0.4 pF. A number of such cells can be connected in a ring, and refreshed using one analog signal line and a single clock signal, and a token passed between the cells. Refreshing 20 such cells would require the clock frequency on the order of 100 kHz. In high-density bipolar processes4 it is feasible to use a number of simple digital-to-analog converters (DACs) for the purpose of parametric programming. The gain of the ®rst summer (i.e. the Iw current (Figs. 2, 6)) is controlled with 12-bit resolution. Each weight current I1 ±I9 is controlled by a 4-bit word. Two more bits: sign si and enable eni are used for each weight wi . Thus it is possible to set the overall gain of the cell with resolution that is higher than the ratio of any two of the input weights. The gain ks of the second summer is constant and equal to 1, and its weights are controlled by 4-bit magnitude words and sign bits. There are no enable bits for the second summer. The ampli®er/integrator's gain (the unity-gain frequency) is programmed by one bit (0 dB or 20 dB). Each of the clipping blocks parameters is programmed by 3-bit words. (FPAA) Part 1: Design 4.2. The Control Hardware All DACs used to control the analog parameters of the cell are connected in a ring (Fig. 11). A token bit, passed between the DACs, determines the response of a DAC to its digital inputs. When the token is present (on), the DAC's output current follows the value input (Fig. 12). When the token is absent (off ), the DAC produces a current corresponding to the last digital value latched. The token is ``captured'' by the DAC on a rising edge of the clock signal when the token input is high. When the token is present, it sets token output to high, enabling the next DAC in the chain to capture the token on the next rising edge of the clock. 4.2.1. Min/Max-Follower. To realize the min/maxfollower function (see Section 2.4.2), the eni (enable) bits of the ®rst summer are controlled by the outputs of the current-mode comparators (Fig. 13). Each of the comparators produces a ``1'' if the corresponding input signal of the cell (connected to the non-inverting input of the comparator) is greater than the output of the ampli®er/integrator, connected to the inverting input of the comparator. When implementing the minfollower function, all comparators whose output is ``0'' indicate these input signals which are at the moment smaller than the output signal of the cell. 153 These signals are selected on the input of the ®rst summer. The weights wi of this summer are made equal in order to implement the average of the selected signals. Thus a feedback scheme is formed which results in all the signals presently smaller than the cell output to be averaged to produce the new cell output. In the case of suf®ciently slowly changing signals, the output rapidly converges to the true minimum signal, and remains ``locked'' onto it due to the hysteresis in the comparator characteristic, so long as it is indeed the smallest input signal. Selecting the average rather than the smallest input signal reduces the convergence speed, but makes this feedback scheme much less likely to be ``fooled'' by a signal that is smallest at the moment only to become larger than other signals a moment later. It also allows simpler hardware to be used. The min=max signal allows inverting of the comparators outputs in order to implement the maximum-follower. The ampli®er/integrator works as an ampli®er by transmitting the current ``maximum'' (or ``minimum'') from the output of the ®rst summer. Its output signal (which is equal to the output signal of the cell) is connected to the inverting inputs of the current comparators. Only the ®rst clipping block is active, with a transfer characteristic shown in Fig. 3a. Fig. 11. A ring of DACs. Fig. 12. Token timing diagram. 154 E. Pierzchala and M. Perkowski Fig. 13. The control circuitry of the cell. Fig. 14 shows results of functional simulation of the maximum-follower. 4.2.2. VCO. In the VCO mode, only one comparator in the control block is enabled. The disabled comparators produce a ``0'' on their outputs. The active comparator's non-inverting input receives a constant signal from the input of the cell. The inverting input receives the output of the integrator, which ramps up or down at the rate determined by the sum of other input signals of the cell. When the output of the integrator achieves the level of the input Fig. 14. Maximum-follower operation. (FPAA) Part 1: Design 155 Fig. 15. VCO operation. threshold signal, the comparator produces (Fig. 13) ``1'' which propagates through the 9-input OR gate to the analog signal inverter and to the sign bit of the multiplier. Inverting the input of the integrator results in a ramp in the opposite direction. On the other hand, since the integrator output signal passes through the signal inverter, the comparator will again see a signal which ramps up. The process continues to produce waveforms shown in Fig. 15. The VCO can be controlled by an input signal, or digitally, by changing the relevant input summer weights. 5. Conclusions The design of a high-frequency, bipolar-technologybased FPAA has been presented. Due to predominantly local signal interconnections and absence of switches in the signal path, high-frequency performance is sacri®ced to the smallest possible degree. A companion paper [17] submitted to this issue demonstrates a variety of applications of the FPAA. These applications effectively prove that limitations imposed on the architecture of the FPAA do not essentially limit its ¯exibility. Notes 1. The upper limit on the current gain of a single-stage current ampli®er of Fig. 4 is near b of the transistors. When several ampli®ers are cascaded, however, controlling of their gain becomes dif®cult unless the gain is limited to about 10. 2. CPI transistor-array process, Maxim Integrated Products; production-quality models were used for simulation. 3. Such as GST-2 from Maxim Integrated Products. 4. Such as GST-2 from Maxim; up to 200,000 transistors on a die. References 1. D. R. D'Mello and P. G. Gulak, ``Design Approaches to Field Programmable Analog Integrated Circuits.'' this issue. 2. EPAC, ``Electronically Programmable Analog Circuit.'' IMP, Inc., San Jose, Calif. 3. B. Gilbert, ``A New Wide-Band Ampli®er Technique.'' IEEE J. Solid-State Circ. SC-3(4), pp. 353±365, Dec. 1968. 4. B. Gilbert, ``A Precise Four-Quadrant Multiplier with Subnanosecond Response.'' IEEE J. Solid-State Circ. SC-3(4), pp. 365±373, Dec 1968. 5. B. Gilbert, ``Current-mode Circuits From a Translinear Viewpoint: A Tutorial.'' in Analogue IC Design: the currentmode approach, ed. C. Toumazou, F. J. Lidgey, and D. G. Haigh, pp. 11±91, Peter Peregrinus Ltd., 1990. 6. F. Goodenough, ``Analog Counterparts of FPGAs Ease System Design.'' Electronic Design, pp. 63±73, Oct. 14, 1994. 7. A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. J. Wiley, 1984. 156 E. Pierzchala and M. Perkowski 8. P. R. Grey and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. 3rd ed., J. Wiley, 1993. 9. A. Hausner, Analog and Analog/Hybrid Computer Programming. Prentice-Hall, Inc., Englewood Cliffs, N.J., 1971. 10. E. K. F. Lee and P. G. Gulak, ``A CMOS Field-Programmable Analog Array.'' IEEE ISSCC Dig. Technical Papers, San Francisco, Calif., Feb. 1991. 11. E. K. F. Lee and P. G. Gulak, ``A CMOS Field-Programmable Analog Array.'' IEEE J. Solid-State Circ. 26(12), pp. 1860± 1867, Dec. 1991. 12. E. K. F. Lee and P. G. Gulak, ``Field Programmable Analogue Array Based on MOSFET Transconductors.'' IEE Electronics Letters 28(1), pp. 28±29, IEE, Jan. 2 1992. 13. E. K. F. Lee and P. G. Gulak, ``MOS Transconductor-Based Field-Programmable Analog Array.'' IEEE ISSCC Dig. Technical Papers, San Francisco, Calif., Feb. 1995. 14. E. Pierzchala and M. A. Perkowski, ``High Speed Field Programmable Analog Array Architecture Design.'' Proc. FPGA Workshop, Berkeley, California, Feb 1994. 15. E. Pierzchala and M. A. Perkowski, ``A Field-Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications.'' Proc. IEEE ISMVL, Boston, Mass., May 1994. 16. E. Pierzchala, M. A. Perkowski, P. Van Halen, and R. Schaumann, ``Current-Mode Ampli®er/Integrator for a FieldProgrammable Analog Array.'' IEEE ISSCC Dig. Technical Papers, San Francisco, Calif., Feb. 1995. 17. E. Pierzchala and M. A. Perkowski, ``A High-Frequency FieldProgrammable Analog Array (FPAA)ÐPart 2: Applications.'' this issue. 18. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog Filters. Prentice Hall, Englewood Cliffs, NJ, 1990. 19. R. Schaumann, personal communication. 20. O. K. Shana'a, ``Circuit Implementation of a High-Speed Continuous-Time Current-Mode Field Programmable Analog Array (FPAA).'' MSc thesis, Portland State Univ., 1996. 21. Martin W. Snelgrove, Panel Discussion ``On the Future of Analog Circuits'', IEEE ISCAS'96, Atlanta, Georgia, May 1996. 22. M. A. Tan, ``Design and Automatic Tuning of Fully Integrated, Transconductance-Grounded Capacitor Filters.'' Ph.D. Thesis, Univ. of Minnesota, 1988. Marek A. Perkowski received his M.S. and Ph.D. degrees from Warsaw University of Technology, Warsaw, Poland. He studied pure mathematics at the University of Warsaw and arti®cial intelligence in Polish Academy of Sciences. He has been on the faculty at the Institute of Automatic Control, Warsaw University of Technology; Department of Electrical Engineering, University of Minnesota; and is currently a Professor at the Department of Electrical Engineering, Portland State University. His interests are in design automation, logic synthesis, machine learning and digital and analog ®eld-programmable gate arrays. He spent the summer of 1994 in Wright Laboratories, WrightPatterson Air Force Base, working on application of boolean decomposition to machine learning and was a Visiting Professor at the university of Montpellier and Technical University of Eindhoven in 1996. He has consulted for several companies in these areas, and also worked for Cypress Semiconductor Corp. as a programmer and system designer of WARP, the ®rst VHDL compiler for EPLDs. Edmund Pierzchala received his M.S. degree in electronic engineering from Warsaw University of Technology, Warsaw, Poland. He worked as a research assistant and a senior research assistant in the Institute of Biocybernetics and Biomedical Engineering of Polish Academy of Sciences in Warsaw, Poland, and  the Nuclear Research Institute in Swierk, Poland. He is presently completing his Ph.D. degree at the Department of Electrical Engineering of Portland State University, where he also taught a number of undergraduate and graduate courses in EE. His research interests include programmable analog circuits, design automation, analog and mixed-signal circuits design, modeling, and simulation.