Analog Signal Processing

Abstract. In the paper, an analysis of the state-of-the-art of active elements for analog signal processing is presented which support–in contrast to the conventional operational amplifiers–not only the voltage-mode but also the current-and mixed-mode operations. Several problems are addressed which are associated with the utilization of these elements in linear applications, particularly in frequency filters. A methodology is proposed which generates a number of fundamentally new active elements with their potential utilization in various ...

Analog signal processing applications such as filter design and oscillators, require the use of different kinds of amplifiers, namely: voltage follower, current conveyors, operational amplifiers and current feedback operational amplifiers. To improve the performances on these applications, it is very much needed to optimize the behavior of the amplifiers. That way, this work shows their optimization by applying two evolutionary algorithms: the Non-Sorting Genetic Algorithm (NSGA-II), and the Multiobjective Evolutionary Algorithm Based on Decomposition (MOEA/D). The analog circuits are sized taking into account design constraints, and linking HSPICE like circuit simulator to evaluate their electrical characteristics. Additionally, we show that differential evolution (DE) enhances the convergence to the Pareto front and controls the evolution of the objectives among different runs. DE also preserves the same time efficiency and increases the dominance on NSGA-II and MOEA/D compared with the one point crossover genetic operator.

A novel interesting type of variable phase angle voltage mode oscillator using modern building block has been presented in this paper. The new proposed oscillator configuration which uses four voltage differencing gain amplifier (VDGA) and two grounded capacitors can generate two sinusoidal signals that change out of phase by 0 to 90 degree. It has four floating and explicit voltage mode outputs where every two outputs have the same phase. The circuit is characterized by (i) the condition of phase angle of the oscillation (PO) (this concept is introduced for the first time in this paper) can be tuned electronically (ii) the gain of the floating outputs can be controlled independently (iii) it provides electronic control of condition of oscillation (CO) and independent control of frequency of oscillation (FO). The Total Harmonic Distortion (THD) of the output waveforms was obtained and the results were reasonability values (less than 4.5%). The non-ideal analysis and simulation resul...

Two new 45o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 μm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.

This paper investigates high-precision validation and multi-domain testing techniques essential for ensuring the reliability and functionality of complex chipsets. It highlights challenges posed by heterogeneous integration, increased design complexity, and tighter performance margins. Advanced methodologies such as hardware-in-the-loop simulation, AI-assisted verification, and cross-domain co-simulation are explored. The study underscores the importance of comprehensive testing frameworks in accelerating time-to-market while maintaining the integrity and robustness of next-generation semiconductor devices.

A limited ability to discriminate between different materials is the fundamental problem with all conventional eddy-current-based metal detectors. This paper presents the use, evaluation and classification of nontraditional excitation signals for eddy-current metal detectors to improve their detection and discrimination ability. The presented multi-frequency excitation signals are as follows: a step sweep sine wave, a linear frequency sweep and sin(x)/x signals. All signals are evaluated in the frequency domain. Amplitude and phase spectra and polar graphs of the detector output signal are used for classification and discrimination of the tested objects. Four different classifiers are presented. The classification results obtained with the use of poly-harmonic signals are compared with those obtained with a classical single-tone method. Multifrequency signals provide more detailed information, due to the response function -the frequency characteristic of a detected object, than standard single-tone methods. Based on the measurements and analysis, a metal object can be better distinguished than when using a single-tone method.

One limiting issue in implementing high-speed wireless systems is the impairment associated with analog processing due to component imperfections. In uplink transmission of multiuser systems, a major source of such impairment is IQI introduced at multiple transmitters. In this paper, we deal with OFDMA and SC-FDMA which have received attention in recent years as physical layer protocol in WiMAX and 3GPP LTE, and analyze the effect of the transmitter (Tx) IQ imbalances on OFDMA and SC-FDMA receivers. To cope with the inter-user interference problem due to Tx IQ imbalances, we propose a widely linear receiver for OFDMA and SC-FDMA systems and also propose a novel subcarrier allocation scheme, which has high tolerance to such Tx IQ distortion.

Using MOSCAPs for compensation can reduce the area needed for their implementation. However; these capacitors are highly nonlinear and their value changes when the voltage across their terminals is changed. Different compensation topologies do not exhibit equal sensitivity to the time-dependent variation of MOSCAP compensation capacitors. Therefore; the selection of a proper compensation technique is considered as an important step before its implementation. In this paper, the goal is to study the existing compensation techniques and their behavior in the presence of compensation capacitor uncertainty and MOSCAP nonlinearity. For such regard, opamps are first designed for equal performance metrics such as: gain bandwidth product, phase margin and settling time. Then the sensitivities of the different structures are evaluated. Ultimately, the least sensitive structures can be chosen as the best choice for implementation. Based on the knowledge of the authors, no such thorough analysis has been ever performed before. A state-space model is suggested to analyze different compensation topologies and to calculate the harmonic distortions and find the most robust structures. These results are compared with circuit level results. It is shown that the CFCC compensation method can lead to creation of least harmonic distortion.

There are many problems which fall into the class of temporal signal processing. These problems have in common the need to relate the temporal properties of their inputs. Conventional solutions to these problems often have high hardware overhead, complex algorithmic solutions, or loss of information through the transformation of temporal properties of the input. To this end, a biologically motivated artificial and neural processing element has been developed. As in biological neurons, processing is time dependent and is implemented using both analog and digital techniques. These characteristics make the PE directly applicable a large class of temporal signal processing problems typically encountered in engineering and science. Multiple aspects of the PE behavior are adjustable, which produces a very wide range of behaviors from simple systems with only a few moderately connected processing elements. The processing element models are custom designed electric circuits based on basic CMOS components and therefore all developed systems can be directly implemented in any standard integrated CMOS technology. The integrated implementation, custom design, and a wide range of adaptable behaviors join to produce a very fast, low-hardware solution to complex spatiotemporal signal processing problems. Seven novel systems based on the hybrid PE are discussed as they relate to commonly encountered temporal signal processing problems.

The phase linearity and electrical stability of the circuit, with any likely reactive load, should be adequate to ensure that there is no significant alteration of the form of a transient or discontinuous waveform such as a fast square or rectangular wave, provided that this would not constitute an output or input overload. There should be no tinging (superimposed spurious oscillation) and, ideally, there should also be no waveform overshoot, under square-wave testing, in which the signal should recover to the undistorted voltage level, +0.5%, within a settling time of 20~ts. 9 The output power delivered by the circuit into a typical load-beating in mind that this may be either higher or lower than the nominal impedance at certain parts of the audio spectrum-must be adequate for the purpose required. 9 If the circuit is driven into overload conditions, it must remain stable, the clipped waveform should be clean and free from instability, and should recover to the normal signal waveform level with the least possible delay-certainly less than 20~ts. In addition to these purely electrical specifications, which would probably be difficult to meet, even in a very high quality solid state design-and most unlikely to be satisfied in any transformer coupled system-there are a number of purely practical considerations, such as that the equipment should be efficient in its use of electrical power, that its heat dissipation should not present problems in housing the equipment, and that the design should be cost-effective, compact and reliable. Since it is improbable that all these performance requirements will be met, in any practical design, it is implicit that the designer will have made certain performance compromises, in which better performance in certain respects has been traded off against a lesser degree of excellence in others. For myself, I think that the total harmonic or intermodulation distortion, which is frequently specified in the makers data sheets, is less important in determining the tonal quality of the system, provided that it is better than 0.05%, than its behaviour under transient conditions, when tested with typical (or accurately simulated) reactive loads, performance in which is seldom or never quoted. Where appropriate, in the following text, I will try to show where various benefits are obtained at the cost of some other potential drawbacks. JLH 1996. This Page Intentionally Left Blank CHAPTER 1 Electronic amplifiers are built up from combinations of active and passive components. The active ones are those, like valves or transistors or integrated circuits, that draw electrical current from suitable voltage supply lines and then use it to generate or modify some electrical signal. The passive components are those, like capacitors, resistors, inductors, potentiometers or switches, which introduce no additional energy into the circuit, but which act upon the input or output voltages and currents of the active devices in order to control the way they operate. Of these, the active components are much more fun, so I will start with these. Although the bulk of modem electronic circuitry is based on 'solid state' components, for very good engineering reasons -one could not, for example, build a compact disc player using valves, and still have room in one's house to sit down and listen to it-all the early audio amplifiers were based on valves, and it is useful to know how these worked, and what the design problems and circuit options were, in order to get a better understanding of the technology. Also, there is still an interest on the part of some 'Hi-Fi' enthusiasts in the construction and use of valve operated audio amplifiers, and additional information on valve based circuitry may be welcomed by them. The term thermionic valve (or valve for short) was given, by its inventor, Sir Ambrose Fleming, to the earliest of these devices, a rectifying diode. Fleming chose the name because of the similarity of its action, in allowing only a one-way flow of current, to that of a one-way air valve on an inflatable tyre, and the way it operated was by controlling the intemal flow of thermally generated electrons, which he called 'thermions', hence the term thermionic valve. In the USA they are called 'vacuum tubes'. These devices consist of a heated cathode, mounted, in vacuum, inside a sealed glass or metal tube. Other electrodes, such as anodes or grids are then arranged around the cathode, so that various different functions can be performed. The descriptive names given to the various types of valve are based on the number of its internal electrodes, so that a valve with two electrodes (a cathode and an anode) will be called a 'diode', one with three electrodes (a cathode, a grid and an anode) will be called a 'triode', one with four (a cathode, two grids and an anode) will be called a 'tetrode', and so on. Williamson gave, though, in the UK, many of the commercial designers judged that 12 watts would be adequate for all normal domestic purposes.

Many practical applications require a comparison of the Hamming weights of two N-bit binary vectors. This comparison can be performed in a fully digital manner or by a mix of analog and digital techniques. In this paper, we propose a design in the latter category that exhibits advantages in speed and power dissipation compared with the best previous designs. The proposed design comprises of two switched-capacitor arrays associated with two comparators placed in parallel, collectively providing a complete comparison outcome of ''['', ''\'', or ''=''. The switchedcapacitor array circuit is composed of uniform capacitances, thus associating identical charges with all bits, independent of their positions in the input bit-vectors. Once charge accumulation has occurred based on the asserted inputs, the two comparators release the final decision concurrently. The structure is shown to support wide input vectors on the order of 64 bits, while requiring a small silicon area for capacitor array structures, CMOS switches, and latched comparators to compute and store the comparison outcome. HSPICE simulation shows a total power consumption of 1.136 mW, evaluated at the operating frequency of 1 GHz (based on input-to-decision delay) for 16 bit input vectors under 0.15 lm TSMC technology.

The use of intelligent controllers applied to indus-trial systems has been getting usual, not only in the process control as in the literature. The most utilized control methodology, within the artificial intelligent techniques, is based in fuzzy logic. Fuzzy logic controllers consist of the ...

A novel analogue power-efficient 2-D programmable finite impulse response image filter is proposed. This solution is based on the current-mode Gilbert-vector-multiplier operating in the weak inversion region, which allows for ultra low power operation. The main advantage is in the asynchronous and parallel calculation of all pixel values without using any clock generator. The filter is a programmable structure that allows programmability of different filter masks both low-pass and high-pass. An experimental filter integrated circuit with a resolution of 6x1 pixels dissipates in measurements a power of 30 μW at a data rate of 30 kframes/s in a 180 nm CMOS technology. One of the intended applications of our proposed image filter is in data compression in wireless endoscopic capsules.

Imaging and Image sensors is a field that is continuously evolving. There are new products coming into the market every day. Some of these have very severe Size, Weight and Power constraints whereas other devices have to handle very high computational loads. Some require both these conditions to be met simultaneously. Current imaging architectures and digital image processing solutions will not be able to meet these ever increasing demands. There is a need to develop novel imaging architectures and image processing solutions to address these requirements. In this work we propose analog signal processing as a solution to this problem. The analog processor is not suggested as a replacement to a digital processor but it will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. In order to show the merits of analog processing the highly computational Normalized Cross Correlation algorithm is implemented. We propose two novel modifications to the algorithm and a new imaging architecture which, significantly reduces the computation time.

In this paper an analog adaptive filter circuit is presented, their coefficients are adapted with analog LMS algorithm using CMOS HP 0.5um technology. The layout simulation result shows fast convergence speed and low power consumption. The performance in configuration as an identifier shows that this circuit can be used in portables VLSI communications systems.

In this paper an analog adaptive filter circuit is presented, their coefficients are adapted with analog LMS algorithm using CMOS HP 0.5um technology. The layout simulation result shows fast convergence speed and low power consumption. The performance in configuration as an identifier shows that this circuit can be used in portables VLSI communications systems.

Many practical applications require a comparison of the Hamming weights of two N-bit binary vectors. This comparison can be performed in a fully digital manner or by a mix of analog and digital techniques. In this paper, we propose a design in the latter category that exhibits advantages in speed and power dissipation compared with the best previous designs. The proposed design comprises of two switched-capacitor arrays associated with two comparators placed in parallel, collectively providing a complete comparison outcome of ''['', ''\'', or ''=''. The switchedcapacitor array circuit is composed of uniform capacitances, thus associating identical charges with all bits, independent of their positions in the input bit-vectors. Once charge accumulation has occurred based on the asserted inputs, the two comparators release the final decision concurrently. The structure is shown to support wide input vectors on the order of 64 bits, while requiring a small silicon area for capacitor array structures, CMOS switches, and latched comparators to compute and store the comparison outcome. HSPICE simulation shows a total power consumption of 1.136 mW, evaluated at the operating frequency of 1 GHz (based on input-to-decision delay) for 16 bit input vectors under 0.15 lm TSMC technology.

Reina Mercedrs s/n 41U12 Sevrlla lSPAlNl. Ye/.. t34 9.55056666. Fur: +34 955056686. L.'-mail; rcamiow Oinire min. e! Same of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear pmessors. In order lo explore the possibilities of these complex spatia-temporal dynamics in image prmessing, a prototype chip has been developed implementing this CNN model with analog sigaal processing blocks. This chip has been designed in a O.Spm CMOS technolo8y. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10 transistors, most of them operating io analog mode) are presented in this pap?.

The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

Slow light systems are particularly attractive for analog signal processing, since their inherent limitation to a delaybandwidth product of 1 is less critical for analog systems such as those used in microwave photonics. We present here the implementation of two basic functions -phase shifting and true time delaying -fully optically controlled using stimulated Brillouin scattering in optical fibers. The combination of these two functions makes possible the implementation of true time delays without limitation on the microwave carrier frequency using the separate carrier tuning technique. This is illustrated by the implementation of the delaying system for the realization of a microwave tunable notch filter.

Slow light systems are particularly attractive for analog signal processing, since their inherent limitation to a delaybandwidth product of 1 is less critical for analog systems such as those used in microwave photonics. We present here the implementation of two basic functions -phase shifting and true time delaying -fully optically controlled using stimulated Brillouin scattering in optical fibers. The combination of these two functions makes possible the implementation of true time delays without limitation on the microwave carrier frequency using the separate carrier tuning technique. This is illustrated by the implementation of the delaying system for the realization of a microwave tunable notch filter.

1 blank line using 9-point font with single spacing A large number of circuit topologies have been proposed in the literature for analog signal processing such as active filters, oscillators, immittance simulators etc. At the beginning, let's say until twenty years ago, the researchers were proposing this type circuit topologies without giving any realization circuit and application example. Therefore, the main problem was how to realize these topologies and how to apply them to practical work. Another important missing main factor was the influence of the limitations caused by the realization topologies and employed active elements such as bandwidth, slew-rate, input and output impedances etc. This paper covers the main features combining the circuit design with the actual realization circuit demonstrating several performance limitations on chosen circuit examples.

This paper presents a high-performance current differencing transconductance amplifier (CDTA), a recently reported active element, especially suitable for analog signal processing applications. A high linearity CMOS configuration for a CDTA is made up of high linearity input and output stages. The proposed CDTA provides high output impedance at port X and excellent input/output current tracking. A biquad filter circuit was chosen as an application example in order to demonstrate the performance of the CDTA. PSpice simulation results using a TSMC 0.35-μ m CMOS process model were included to verify the expected values.

The aim of this thesis was to develop a model of a receiver which could be quickly used to analyze radiated interference levels from data captured at the output of the antenna equipment used to measure radiated energy. Active circuits were mainly used in developing this model for the ease with which the design and simulations could be carried out in OrCAD.The guiding document for the thesis work has been CISPR 16-1-1 (International Special Committee on Radio Interference part 16-1-1) which specifies the characteristics and performance of equipment for the measurement of radiated interference.The testing of this receiver model was carried out as far as possible based on the test setupsrecommended in CISPR, and all results have been compared with the standards laid down for the model.Using the results, it will be shown that a CISPR EMI receiver can be modeled as a simple EMI receiver consisting of filtering, mixing and detecting circuits built according to specifications.

The design of sinusoidal oscillators has been an active area of research in the field of analog electronics. Particularly, oscillators capable of providing waveforms in phase quadrature and circuits capable of generating multip le phase oscillat ing voltage and/or current waveforms are of interest fro m the viewpoint of their applicat ions in communication systems. In this paper, a mixed-mode three phase sinusoidal oscillator, emp loying Second Generation Dual-X Current Conveyor as the active build ing block and grounded passive elements, is p resented. A feedback scheme consisting of three cascaded inverting first-order low-pass sections is employed to obtain a three phase voltage-mode as well as current-mode sinusoidal signals simultaneously. The condition of oscillations and the frequency oscillations are independently controllable. The proposed circuits are co mpatible with CMOS integration by virtue of the fact that only M OSFETs and grounded capacitors are utilized. Circuit simu lations using PSPICE yielded pro mising results in the form of excellent matching between the theoretical and simulated values. Variation of the frequency of oscillation with the capacitor value is exp lored. Electronic control of the frequency of oscillat ion by means of a control voltage is also demonstrated.

The current mode programmable analog modules are realized using digitally controlled low voltage CMOS current conveyors. These programmable modules include current mode amplifiers, integrators, differentiators, first order multifunctional filter and second order multifunctional filters. The realized current mode programmable analog modules can provide digital control to the parameters through an n-bit control word with high resolution capability and reconfigurability. These programmable analog modules are suitable for realizing current mode field programmable analog array. The realized programmable analog modules are designed and verified using PSPICE and the results thus obtained justify the theory.

In this paper an operational transconductance amplifier with temperature compensation is presented. It is a voltagecontrolled current source, which operates in an open loop configuration with a single output connected to a resistive load. The amplifier is internally compensated to keep the gain stable over the -40 °C to 125 °C temperature range. It features low input voltage noise and operates at supply voltages from 3 V to 5.5 V. Additionally, an internal 1.21 V bandgap reference is used to ensure a stable internal voltage reference point. The active area of the proposed integrated circuit designed with 0.18 µm Bipolar, CMOS, DMOS (BCD) technology is 750 µm x 260 µm. It consumes 423 µA of current and it has 8.87 nV/SHz of input noise at 500 kHz. The resulting simulated voltage gain is 40 dB and variations are less than ±0.3 dB over the temperature range of -40 °C to 125 °C.

Impedance cardiography (IC) has been used to monitor the pumping function of the heart in terms of stroke volume or cardiac output. We explored the extent to which IC can be used for monitoring transient effects of cardiac alterations on a beat-to-beat basis. A four-spot-electrode configuration was used in the present design. The spatial arrangement of the four electrodes was carefully selected to obtain an optimal result. A constant current source provided a 4 mA, 20 kHz sinusoidal excitation current. Analog signal processing was developed to demodulate and amplify the resultant impedance information, eliminate low frequency motion artifacts and incidental breathing artifacts. Experiments were performed on normal healthy volunteers. Impedance waveforms were recorded from each subject beginning from a supine position then moving to an upright position. Breath holding was maintained throughout the procedure. The impedance waveform, Z, its first derivative dZ/dt, the DC component, Z(0...

A unified matrix formulation is presented for the analysis of intersymbol and intercarrier interference in orthogonal frequency-division multiplexing (OFDM) systems. The proposed formulation relies on six parameters and allows studying various schemes, including those with windowing in the transmitter and/or in the receiver (called windowed OFDM systems), which may add cyclic suffix and/or cyclic prefix (CP), besides the conventional CP-OFDM. The proposed framework encompasses seven different OFDM systems. It considers the overlap-and-add procedure performed in the transmitter of windowed OFDM systems, being jointly formulated with the channel convolution. The intersymbol and intercarrier interference, caused when the order of the channel impulse response is higher than the number of CP samples, is characterized. A new equivalent channel matrix that is useful for calculating both the received signal and the interference power is defined and characterized. Unlike previous works, this new channel matrix has no restrictions on the length of the channel impulse response, which means that the study is not constrained to the particular case of two or three data blocks interfering in the received signal. Theoretical expressions for the powers of three different kinds of interference are derived. These expressions allow calculating the signal-to-interference-plus-noise ratio, useful for computing the data rate of each OFDM system. The proposed formulation is applied to realistic examples, showing its effectiveness through comparisons based on numerical performance assessments of the considered OFDM systems.

The proposed work aims to examine the use of Tungsten oxide as a suitable transition metal oxide while designing a neuromorphic circuit with memristive device. This reflects the fundamental electrical characterization of the device with the key points of better switching performance. Resistive switching in WOx is bipolar here. The Pd/WOx/W made memristors become more conductive (resistive) when applied with a positive (negative) bias voltage. The conductance or resistance change is controlled by the redistribution of oxygen vacancies (VOx) within the WOx film creating or removing conductive regions between the two electrodes. Here switching is of analog type that refers to the incremental modulation of the device conductance.

Three basic translinear circuit topologies are modified for use at low supply voltage. They are: 1) the balanced translinear loop; 2) the alternating translinear loop; and 3) the instantaneous-companding integrator. The key to this work is the constructive use of nonsaturated MOS transistors operating in weak inversion. This provides two improvements. First, circuit operation is extended to low supply voltage. Second, accurate realization is enabled since the circuits become immune to MOS body-effect. The proposed techniques are suitable for static and dynamic analog signal processing circuits in mixed-signal chips fabricated in digital CMOS technology and operating at the minimum possible supply voltage.

The availability of compact arrays of high speed analog to digital converters and fast field programmable gate arrays allow much of the complex analog signal processing chain in nuclear pulse processing data acquisition to be replaced with digital algorithms. The fully digital approach allows us to evaluate APD based PET detectors and time of flight (TOF) capable fast PMTs using the same digital data acquisition (DAQ) system. We have developed digital processing algorithms for recording the time, position, and energy from a 511 keV photon interaction with a lutetium-oxyortho-silicate (LSO) crystal array coupled to a Position Sensitive Avalanche Photodiode (PSAPD) or to a XP2020 Photonics PMT as the scintillation light photodector. Implementing these algorithms in a Pixie-4 setup, we compared its performance to an analog setup based on NIM electronics modules, and we evaluated its coincidence time performance using utra-fast PMTs. From our initial experiments, the Pixie-4 system performs well in high spatial resolution, high count rate PET applications with our PSAPD detectors and with fast PMTs that are capable of TOF PET applications.

Abstract. In the paper, an analysis of the state-of-the-art of active elements for analog signal processing is presented which support–in contrast to the conventional operational amplifiers–not only the voltage-mode but also the current-and mixed-mode operations. Several problems are addressed which are associated with the utilization of these elements in linear applications, particularly in frequency filters. A methodology is proposed which generates a number of fundamentally new active elements with their potential utilization in various ...

Sensory information coming from natural sensors and being propagated on afferent nerve fibers could be used as feedback for a more efficient closed-loop control of a Functional Electrical Stimulation system. In order to extract and separate these signals according to their nerve fascicule origins, we propose a new architecture of a multipolar cuff electrode and an optimized integrated acquisition circuit. Concerning the electrode, we propose a specific configuration using a large number of poles in order to both reject parasitic signals, such as electromyogram and provide a maximum of recording channels in order to help the signal localization inside the nerve. Moreover, specific low-level analog signal processing was designed to extract the expected low-amplitude signal from its noisy environment. This signal processing is implemented in an ASIC that has to be implanted close to the electrode to achieve the best signal-to-noise ratio.

A single-output CMOS differential amplifier is one of useful analog building blocks for signal-processing applications in mixed-signal circuits. One of advantages of using a differential amplifier instead of other transistor amplifiers is its simple biasing and high amplifier gain. In this paper, in order to improve the differential mode gain, we propose a design for a single-output CMOS differential amplifier with an active load. This circuit can reach a differential-mode gain of 165 while consuming power of 195 µw.

A single-output CMOS differential amplifier is one of useful analog building blocks for signal-processing applications in mixed-signal circuits. One of advantages of using a differential amplifier instead of other transistor amplifiers is its simple biasing and high amplifier gain. In this paper, in order to improve the differential mode gain, we propose a design for a single-output CMOS differential amplifier with an active load. This circuit can reach a differential-mode gain of 165 while consuming power of 195 µw.

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A broadband, Mach-Zehnder-interferometer based silicon optical modulator is demonstrated, with an electrical bandwidth of 26 GHz and V π L of 4 V•cm. The design of this modulator does not require epitaxial overgrowth and is therefore simpler to fabricate than previous devices with similar performance.

The current transfer characteristic of the CMOS symmetrical OTA, operating in the subthreshold region, depends much more on channel length modulation then operating in the strong inversion region. In this paper a new method is proposed to reduce the dependence on channel length modulation and to improve the OTA behaviour by changing one of the MOS transistor dimensions in the CMOS symmetrical OTA. The result is proven by SPICE simulations and by measurements.

Conventional in-air ultrasonic rangefinders for robotic applications employ inexpensive analog signal processing techniques, based on threshold methods, to perform range measurements. Digital signal processing techniques using correlation methods can provide more accurate measurements, at the expense of greater system complexity and cost. We propose using a modified second-order bandwidth sampling technique for making data acquisition concomitant with frequency shift of the sampled narrow-band signals from in-air ultrasonic transducers to their equivalent baseband representations. The reduction of the frequency-analyzing interval allows one to conceive sampled baseband correlators for multiple receiving transducers with a complexity comparable to that of analog receivers. We develop a procedure of sensor calibration that is based on a stochastic model of time-of-flight noise; the effect of the receiver noise on the ranging accuracy is, thus, evaluated separately from the effect, due to environmental changes of the speed of sound. The simulation study and the experimental results obtained with our demonstration system offer promise for multichannel sampled baseband correlators, the time-of-flight estimation accuracy of which is close to the theoretical Cramér-Rao (CR) lower bound for signals in additive white Gaussian noise.

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 5 RTC FPAA testchip was implemented in 0.35-m CMOS technology. A set of various circuit primitives, such as one-and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 W/TE and precision errors below 3%.

This paper presents a novel voltage-follower, implemented in bipolar technology, based on a global feedback technique. The evaluation of the circuit has been carried out using extra fast complimentary transistors and the biasing circuitry followed the same design philosophy. The proposed design exhibits very high input and very low output impedance, due to the feedback technique, for operating frequencies beyond 1GHz. The small-signal bandwidth achieved is higher than 3GHz, the output voltage swing is some ±3.2V, the offset voltage is around 200uV while the input offset current is just above 130nA. The new circuit achieved gain flatness to within 0.1dB up to 170MHz, featuring total harmonic distortion better than-65dB and intermodulation distortion of around-70dB, for capacitive loads up to 10pF. The operation of the novel design is specified from-20 o C to +100 o C and the power dissipation is some 52mW on a ±5V power supply.

Imaging and Image sensors is a field that is continuously evolving. There are new products coming into the market every day. Some of these have very severe Size, Weight and Power constraints whereas other devices have to handle very high computational loads. Some require both these conditions to be met simultaneously. Current imaging architectures and digital image processing solutions will not be able to meet these ever increasing demands. There is a need to develop novel imaging architectures and image processing solutions to address these requirements. In this work we propose analog signal processing as a solution to this problem. The analog processor is not suggested as a replacement to a digital processor but it will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. In order to show the merits of analog processing two stereo correspondence algorithms are implemented. We propose novel modifications to the algorithms and new imaging architectures which, significantly reduces the computation time.

Imaging and Image sensors is a field that is continuously evolving. There are new products coming into the market every day. Some of these have very severe Size, Weight and Power constraints whereas other devices have to handle very high computational loads. Some require both these conditions to be met simultaneously. Current imaging architectures and digital image processing solutions will not be able to meet these ever increasing demands. There is a need to develop novel imaging architectures and image processing solutions to address these requirements. In this work we propose analog signal processing as a solution to this problem. The analog processor is not suggested as a replacement to a digital processor but it will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. In order to show the merits of analog processing the highly computational Normalized Cross Correlation algorithm is implemented. We propose two novel modifications to the algorithm and a new imaging architecture which, significantly reduces the computation time.

In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture, the critical parts of such a terminal were designed and implemented using three different chips. These parts include a baseband processor, a modem and suitable analogue parts. The baseband processor was designed to support multimode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm supports a direct conversion terminal. The analogue circuitry includes analogue filters and Digital-to-Analog and Analog-to-Digital converters. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the multimode terminal are presented.

Although a large number of single current feedback op-amp (CFOA)-based sinusoidal oscillator circuits have been proposed in the literature, to the best knowledge of the authors, no single-CFOA oscillator configuration has been reported earlier which can absorb all the parasitic impedances of the CFOA in the various external passive elements employed. The major intention of this paper is to report such a circuit. The workability of the proposed circuit has been confirmed by experimental results employing an AD844-type CFOA.

A new multiplier-divider circuit using a single Current Differencing Buffered Amplifier (CDBA) and only six MOSFETs has been presented. The proposed circuit has the advantage of simultaneously realizing a multiplier and divider without changing the circuit topology. The basic functions of the proposed circuit have been verified through PSPICE simulations using a CMOS CDBA and NMOS transistors with process parameters of 0.35 µm CMOS technology and some application results of the proposed cell in various modes of operation have been included.